| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(0), |
| 14 | UINT64_C(0), |
| 15 | UINT64_C(0), |
| 16 | UINT64_C(0), |
| 17 | UINT64_C(0), |
| 18 | UINT64_C(0), |
| 19 | UINT64_C(0), |
| 20 | UINT64_C(0), |
| 21 | UINT64_C(0), |
| 22 | UINT64_C(0), |
| 23 | UINT64_C(0), |
| 24 | UINT64_C(0), |
| 25 | UINT64_C(0), |
| 26 | UINT64_C(0), |
| 27 | UINT64_C(0), |
| 28 | UINT64_C(0), |
| 29 | UINT64_C(0), |
| 30 | UINT64_C(0), |
| 31 | UINT64_C(0), |
| 32 | UINT64_C(0), |
| 33 | UINT64_C(0), |
| 34 | UINT64_C(0), |
| 35 | UINT64_C(0), |
| 36 | UINT64_C(0), |
| 37 | UINT64_C(0), |
| 38 | UINT64_C(0), |
| 39 | UINT64_C(0), |
| 40 | UINT64_C(0), |
| 41 | UINT64_C(0), |
| 42 | UINT64_C(0), |
| 43 | UINT64_C(0), |
| 44 | UINT64_C(0), |
| 45 | UINT64_C(0), |
| 46 | UINT64_C(0), |
| 47 | UINT64_C(0), |
| 48 | UINT64_C(0), |
| 49 | UINT64_C(0), |
| 50 | UINT64_C(0), |
| 51 | UINT64_C(0), |
| 52 | UINT64_C(0), |
| 53 | UINT64_C(0), |
| 54 | UINT64_C(0), |
| 55 | UINT64_C(0), |
| 56 | UINT64_C(0), |
| 57 | UINT64_C(0), |
| 58 | UINT64_C(0), |
| 59 | UINT64_C(0), |
| 60 | UINT64_C(0), |
| 61 | UINT64_C(0), |
| 62 | UINT64_C(0), |
| 63 | UINT64_C(0), |
| 64 | UINT64_C(0), |
| 65 | UINT64_C(0), |
| 66 | UINT64_C(0), |
| 67 | UINT64_C(0), |
| 68 | UINT64_C(0), |
| 69 | UINT64_C(0), |
| 70 | UINT64_C(0), |
| 71 | UINT64_C(0), |
| 72 | UINT64_C(0), |
| 73 | UINT64_C(0), |
| 74 | UINT64_C(0), |
| 75 | UINT64_C(0), |
| 76 | UINT64_C(0), |
| 77 | UINT64_C(0), |
| 78 | UINT64_C(0), |
| 79 | UINT64_C(0), |
| 80 | UINT64_C(0), |
| 81 | UINT64_C(0), |
| 82 | UINT64_C(0), |
| 83 | UINT64_C(0), |
| 84 | UINT64_C(0), |
| 85 | UINT64_C(0), |
| 86 | UINT64_C(0), |
| 87 | UINT64_C(0), |
| 88 | UINT64_C(0), |
| 89 | UINT64_C(0), |
| 90 | UINT64_C(0), |
| 91 | UINT64_C(0), |
| 92 | UINT64_C(0), |
| 93 | UINT64_C(0), |
| 94 | UINT64_C(0), |
| 95 | UINT64_C(0), |
| 96 | UINT64_C(0), |
| 97 | UINT64_C(0), |
| 98 | UINT64_C(0), |
| 99 | UINT64_C(0), |
| 100 | UINT64_C(0), |
| 101 | UINT64_C(0), |
| 102 | UINT64_C(0), |
| 103 | UINT64_C(0), |
| 104 | UINT64_C(0), |
| 105 | UINT64_C(0), |
| 106 | UINT64_C(0), |
| 107 | UINT64_C(0), |
| 108 | UINT64_C(0), |
| 109 | UINT64_C(0), |
| 110 | UINT64_C(0), |
| 111 | UINT64_C(0), |
| 112 | UINT64_C(0), |
| 113 | UINT64_C(0), |
| 114 | UINT64_C(0), |
| 115 | UINT64_C(0), |
| 116 | UINT64_C(0), |
| 117 | UINT64_C(0), |
| 118 | UINT64_C(0), |
| 119 | UINT64_C(0), |
| 120 | UINT64_C(0), |
| 121 | UINT64_C(0), |
| 122 | UINT64_C(0), |
| 123 | UINT64_C(0), |
| 124 | UINT64_C(0), |
| 125 | UINT64_C(0), |
| 126 | UINT64_C(0), |
| 127 | UINT64_C(0), |
| 128 | UINT64_C(0), |
| 129 | UINT64_C(0), |
| 130 | UINT64_C(0), |
| 131 | UINT64_C(0), |
| 132 | UINT64_C(0), |
| 133 | UINT64_C(0), |
| 134 | UINT64_C(0), |
| 135 | UINT64_C(0), |
| 136 | UINT64_C(0), |
| 137 | UINT64_C(0), |
| 138 | UINT64_C(0), |
| 139 | UINT64_C(0), |
| 140 | UINT64_C(0), |
| 141 | UINT64_C(0), |
| 142 | UINT64_C(0), |
| 143 | UINT64_C(0), |
| 144 | UINT64_C(0), |
| 145 | UINT64_C(0), |
| 146 | UINT64_C(0), |
| 147 | UINT64_C(0), |
| 148 | UINT64_C(0), |
| 149 | UINT64_C(0), |
| 150 | UINT64_C(0), |
| 151 | UINT64_C(0), |
| 152 | UINT64_C(0), |
| 153 | UINT64_C(0), |
| 154 | UINT64_C(0), |
| 155 | UINT64_C(0), |
| 156 | UINT64_C(0), |
| 157 | UINT64_C(0), |
| 158 | UINT64_C(0), |
| 159 | UINT64_C(0), |
| 160 | UINT64_C(0), |
| 161 | UINT64_C(0), |
| 162 | UINT64_C(0), |
| 163 | UINT64_C(0), |
| 164 | UINT64_C(0), |
| 165 | UINT64_C(0), |
| 166 | UINT64_C(0), |
| 167 | UINT64_C(0), |
| 168 | UINT64_C(0), |
| 169 | UINT64_C(0), |
| 170 | UINT64_C(0), |
| 171 | UINT64_C(0), |
| 172 | UINT64_C(0), |
| 173 | UINT64_C(0), |
| 174 | UINT64_C(0), |
| 175 | UINT64_C(0), |
| 176 | UINT64_C(0), |
| 177 | UINT64_C(0), |
| 178 | UINT64_C(0), |
| 179 | UINT64_C(0), |
| 180 | UINT64_C(0), |
| 181 | UINT64_C(0), |
| 182 | UINT64_C(0), |
| 183 | UINT64_C(0), |
| 184 | UINT64_C(0), |
| 185 | UINT64_C(0), |
| 186 | UINT64_C(0), |
| 187 | UINT64_C(0), |
| 188 | UINT64_C(0), |
| 189 | UINT64_C(0), |
| 190 | UINT64_C(0), |
| 191 | UINT64_C(0), |
| 192 | UINT64_C(0), |
| 193 | UINT64_C(0), |
| 194 | UINT64_C(0), |
| 195 | UINT64_C(0), |
| 196 | UINT64_C(0), |
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| 198 | UINT64_C(0), |
| 199 | UINT64_C(0), |
| 200 | UINT64_C(0), |
| 201 | UINT64_C(0), |
| 202 | UINT64_C(0), |
| 203 | UINT64_C(0), |
| 204 | UINT64_C(0), |
| 205 | UINT64_C(0), |
| 206 | UINT64_C(0), |
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| 210 | UINT64_C(0), |
| 211 | UINT64_C(0), |
| 212 | UINT64_C(0), |
| 213 | UINT64_C(0), |
| 214 | UINT64_C(0), |
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| 227 | UINT64_C(0), |
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| 240 | UINT64_C(0), |
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| 245 | UINT64_C(0), |
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| 249 | UINT64_C(0), |
| 250 | UINT64_C(0), |
| 251 | UINT64_C(0), |
| 252 | UINT64_C(0), |
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| 270 | UINT64_C(0), |
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| 273 | UINT64_C(0), |
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| 624 | UINT64_C(0), |
| 625 | UINT64_C(0), |
| 626 | UINT64_C(0), |
| 627 | UINT64_C(0), |
| 628 | UINT64_C(0), |
| 629 | UINT64_C(0), |
| 630 | UINT64_C(0), |
| 631 | UINT64_C(0), |
| 632 | UINT64_C(0), |
| 633 | UINT64_C(0), |
| 634 | UINT64_C(0), |
| 635 | UINT64_C(0), |
| 636 | UINT64_C(0), |
| 637 | UINT64_C(0), |
| 638 | UINT64_C(0), |
| 639 | UINT64_C(0), |
| 640 | UINT64_C(0), |
| 641 | UINT64_C(0), |
| 642 | UINT64_C(0), |
| 643 | UINT64_C(0), |
| 644 | UINT64_C(0), |
| 645 | UINT64_C(0), |
| 646 | UINT64_C(0), |
| 647 | UINT64_C(0), |
| 648 | UINT64_C(0), |
| 649 | UINT64_C(0), |
| 650 | UINT64_C(0), |
| 651 | UINT64_C(0), |
| 652 | UINT64_C(0), |
| 653 | UINT64_C(0), |
| 654 | UINT64_C(0), |
| 655 | UINT64_C(0), |
| 656 | UINT64_C(0), |
| 657 | UINT64_C(0), |
| 658 | UINT64_C(0), |
| 659 | UINT64_C(0), |
| 660 | UINT64_C(0), |
| 661 | UINT64_C(0), |
| 662 | UINT64_C(0), |
| 663 | UINT64_C(0), |
| 664 | UINT64_C(0), |
| 665 | UINT64_C(0), |
| 666 | UINT64_C(0), |
| 667 | UINT64_C(0), |
| 668 | UINT64_C(0), |
| 669 | UINT64_C(0), |
| 670 | UINT64_C(0), |
| 671 | UINT64_C(0), |
| 672 | UINT64_C(0), |
| 673 | UINT64_C(0), |
| 674 | UINT64_C(0), |
| 675 | UINT64_C(0), |
| 676 | UINT64_C(0), |
| 677 | UINT64_C(0), |
| 678 | UINT64_C(0), |
| 679 | UINT64_C(0), |
| 680 | UINT64_C(0), |
| 681 | UINT64_C(0), |
| 682 | UINT64_C(0), |
| 683 | UINT64_C(0), |
| 684 | UINT64_C(0), |
| 685 | UINT64_C(0), |
| 686 | UINT64_C(0), |
| 687 | UINT64_C(0), |
| 688 | UINT64_C(0), |
| 689 | UINT64_C(0), |
| 690 | UINT64_C(0), |
| 691 | UINT64_C(0), |
| 692 | UINT64_C(0), |
| 693 | UINT64_C(0), |
| 694 | UINT64_C(0), |
| 695 | UINT64_C(0), |
| 696 | UINT64_C(0), |
| 697 | UINT64_C(0), |
| 698 | UINT64_C(0), |
| 699 | UINT64_C(68591616), // ABS_ZPmZ_B |
| 700 | UINT64_C(81174528), // ABS_ZPmZ_D |
| 701 | UINT64_C(72785920), // ABS_ZPmZ_H |
| 702 | UINT64_C(76980224), // ABS_ZPmZ_S |
| 703 | UINT64_C(1310767104), // ABSv16i8 |
| 704 | UINT64_C(1591785472), // ABSv1i64 |
| 705 | UINT64_C(245413888), // ABSv2i32 |
| 706 | UINT64_C(1323350016), // ABSv2i64 |
| 707 | UINT64_C(241219584), // ABSv4i16 |
| 708 | UINT64_C(1319155712), // ABSv4i32 |
| 709 | UINT64_C(1314961408), // ABSv8i16 |
| 710 | UINT64_C(237025280), // ABSv8i8 |
| 711 | UINT64_C(1161875456), // ADCLB_ZZZ_D |
| 712 | UINT64_C(1157681152), // ADCLB_ZZZ_S |
| 713 | UINT64_C(1161876480), // ADCLT_ZZZ_D |
| 714 | UINT64_C(1157682176), // ADCLT_ZZZ_S |
| 715 | UINT64_C(973078528), // ADCSWr |
| 716 | UINT64_C(3120562176), // ADCSXr |
| 717 | UINT64_C(436207616), // ADCWr |
| 718 | UINT64_C(2583691264), // ADCXr |
| 719 | UINT64_C(2441084928), // ADDG |
| 720 | UINT64_C(1163943936), // ADDHNB_ZZZ_B |
| 721 | UINT64_C(1168138240), // ADDHNB_ZZZ_H |
| 722 | UINT64_C(1172332544), // ADDHNB_ZZZ_S |
| 723 | UINT64_C(1163944960), // ADDHNT_ZZZ_B |
| 724 | UINT64_C(1168139264), // ADDHNT_ZZZ_H |
| 725 | UINT64_C(1172333568), // ADDHNT_ZZZ_S |
| 726 | UINT64_C(245383168), // ADDHNv2i64_v2i32 |
| 727 | UINT64_C(1319124992), // ADDHNv2i64_v4i32 |
| 728 | UINT64_C(241188864), // ADDHNv4i32_v4i16 |
| 729 | UINT64_C(1314930688), // ADDHNv4i32_v8i16 |
| 730 | UINT64_C(1310736384), // ADDHNv8i16_v16i8 |
| 731 | UINT64_C(236994560), // ADDHNv8i16_v8i8 |
| 732 | UINT64_C(73420800), // ADDPL_XXI |
| 733 | UINT64_C(1142005760), // ADDP_ZPmZ_B |
| 734 | UINT64_C(1154588672), // ADDP_ZPmZ_D |
| 735 | UINT64_C(1146200064), // ADDP_ZPmZ_H |
| 736 | UINT64_C(1150394368), // ADDP_ZPmZ_S |
| 737 | UINT64_C(1310768128), // ADDPv16i8 |
| 738 | UINT64_C(245414912), // ADDPv2i32 |
| 739 | UINT64_C(1323351040), // ADDPv2i64 |
| 740 | UINT64_C(1592899584), // ADDPv2i64p |
| 741 | UINT64_C(241220608), // ADDPv4i16 |
| 742 | UINT64_C(1319156736), // ADDPv4i32 |
| 743 | UINT64_C(1314962432), // ADDPv8i16 |
| 744 | UINT64_C(237026304), // ADDPv8i8 |
| 745 | UINT64_C(822083584), // ADDSWri |
| 746 | UINT64_C(721420288), // ADDSWrs |
| 747 | UINT64_C(723517440), // ADDSWrx |
| 748 | UINT64_C(2969567232), // ADDSXri |
| 749 | UINT64_C(2868903936), // ADDSXrs |
| 750 | UINT64_C(2871001088), // ADDSXrx |
| 751 | UINT64_C(2871025664), // ADDSXrx64 |
| 752 | UINT64_C(69226496), // ADDVL_XXI |
| 753 | UINT64_C(1311881216), // ADDVv16i8v |
| 754 | UINT64_C(242333696), // ADDVv4i16v |
| 755 | UINT64_C(1320269824), // ADDVv4i32v |
| 756 | UINT64_C(1316075520), // ADDVv8i16v |
| 757 | UINT64_C(238139392), // ADDVv8i8v |
| 758 | UINT64_C(285212672), // ADDWri |
| 759 | UINT64_C(184549376), // ADDWrs |
| 760 | UINT64_C(186646528), // ADDWrx |
| 761 | UINT64_C(2432696320), // ADDXri |
| 762 | UINT64_C(2332033024), // ADDXrs |
| 763 | UINT64_C(2334130176), // ADDXrx |
| 764 | UINT64_C(2334154752), // ADDXrx64 |
| 765 | UINT64_C(622903296), // ADD_ZI_B |
| 766 | UINT64_C(635486208), // ADD_ZI_D |
| 767 | UINT64_C(627097600), // ADD_ZI_H |
| 768 | UINT64_C(631291904), // ADD_ZI_S |
| 769 | UINT64_C(67108864), // ADD_ZPmZ_B |
| 770 | UINT64_C(79691776), // ADD_ZPmZ_D |
| 771 | UINT64_C(71303168), // ADD_ZPmZ_H |
| 772 | UINT64_C(75497472), // ADD_ZPmZ_S |
| 773 | UINT64_C(69206016), // ADD_ZZZ_B |
| 774 | UINT64_C(81788928), // ADD_ZZZ_D |
| 775 | UINT64_C(73400320), // ADD_ZZZ_H |
| 776 | UINT64_C(77594624), // ADD_ZZZ_S |
| 777 | UINT64_C(1310753792), // ADDv16i8 |
| 778 | UINT64_C(1591772160), // ADDv1i64 |
| 779 | UINT64_C(245400576), // ADDv2i32 |
| 780 | UINT64_C(1323336704), // ADDv2i64 |
| 781 | UINT64_C(241206272), // ADDv4i16 |
| 782 | UINT64_C(1319142400), // ADDv4i32 |
| 783 | UINT64_C(1314948096), // ADDv8i16 |
| 784 | UINT64_C(237011968), // ADDv8i8 |
| 785 | UINT64_C(268435456), // ADR |
| 786 | UINT64_C(2415919104), // ADRP |
| 787 | UINT64_C(81829888), // ADR_LSL_ZZZ_D_0 |
| 788 | UINT64_C(81830912), // ADR_LSL_ZZZ_D_1 |
| 789 | UINT64_C(81831936), // ADR_LSL_ZZZ_D_2 |
| 790 | UINT64_C(81832960), // ADR_LSL_ZZZ_D_3 |
| 791 | UINT64_C(77635584), // ADR_LSL_ZZZ_S_0 |
| 792 | UINT64_C(77636608), // ADR_LSL_ZZZ_S_1 |
| 793 | UINT64_C(77637632), // ADR_LSL_ZZZ_S_2 |
| 794 | UINT64_C(77638656), // ADR_LSL_ZZZ_S_3 |
| 795 | UINT64_C(69246976), // ADR_SXTW_ZZZ_D_0 |
| 796 | UINT64_C(69248000), // ADR_SXTW_ZZZ_D_1 |
| 797 | UINT64_C(69249024), // ADR_SXTW_ZZZ_D_2 |
| 798 | UINT64_C(69250048), // ADR_SXTW_ZZZ_D_3 |
| 799 | UINT64_C(73441280), // ADR_UXTW_ZZZ_D_0 |
| 800 | UINT64_C(73442304), // ADR_UXTW_ZZZ_D_1 |
| 801 | UINT64_C(73443328), // ADR_UXTW_ZZZ_D_2 |
| 802 | UINT64_C(73444352), // ADR_UXTW_ZZZ_D_3 |
| 803 | UINT64_C(1159914496), // AESD_ZZZ_B |
| 804 | UINT64_C(1311266816), // AESDrr |
| 805 | UINT64_C(1159913472), // AESE_ZZZ_B |
| 806 | UINT64_C(1311262720), // AESErr |
| 807 | UINT64_C(1159783424), // AESIMC_ZZ_B |
| 808 | UINT64_C(1311275008), // AESIMCrr |
| 809 | UINT64_C(1159782400), // AESMC_ZZ_B |
| 810 | UINT64_C(1311270912), // AESMCrr |
| 811 | UINT64_C(1912602624), // ANDSWri |
| 812 | UINT64_C(1778384896), // ANDSWrs |
| 813 | UINT64_C(4060086272), // ANDSXri |
| 814 | UINT64_C(3925868544), // ANDSXrs |
| 815 | UINT64_C(624967680), // ANDS_PPzPP |
| 816 | UINT64_C(68820992), // ANDV_VPZ_B |
| 817 | UINT64_C(81403904), // ANDV_VPZ_D |
| 818 | UINT64_C(73015296), // ANDV_VPZ_H |
| 819 | UINT64_C(77209600), // ANDV_VPZ_S |
| 820 | UINT64_C(301989888), // ANDWri |
| 821 | UINT64_C(167772160), // ANDWrs |
| 822 | UINT64_C(2449473536), // ANDXri |
| 823 | UINT64_C(2315255808), // ANDXrs |
| 824 | UINT64_C(620773376), // AND_PPzPP |
| 825 | UINT64_C(92274688), // AND_ZI |
| 826 | UINT64_C(68812800), // AND_ZPmZ_B |
| 827 | UINT64_C(81395712), // AND_ZPmZ_D |
| 828 | UINT64_C(73007104), // AND_ZPmZ_H |
| 829 | UINT64_C(77201408), // AND_ZPmZ_S |
| 830 | UINT64_C(69218304), // AND_ZZZ |
| 831 | UINT64_C(1310727168), // ANDv16i8 |
| 832 | UINT64_C(236985344), // ANDv8i8 |
| 833 | UINT64_C(67404032), // ASRD_ZPmI_B |
| 834 | UINT64_C(75792384), // ASRD_ZPmI_D |
| 835 | UINT64_C(67404288), // ASRD_ZPmI_H |
| 836 | UINT64_C(71598080), // ASRD_ZPmI_S |
| 837 | UINT64_C(68452352), // ASRR_ZPmZ_B |
| 838 | UINT64_C(81035264), // ASRR_ZPmZ_D |
| 839 | UINT64_C(72646656), // ASRR_ZPmZ_H |
| 840 | UINT64_C(76840960), // ASRR_ZPmZ_S |
| 841 | UINT64_C(448800768), // ASRVWr |
| 842 | UINT64_C(2596284416), // ASRVXr |
| 843 | UINT64_C(68714496), // ASR_WIDE_ZPmZ_B |
| 844 | UINT64_C(72908800), // ASR_WIDE_ZPmZ_H |
| 845 | UINT64_C(77103104), // ASR_WIDE_ZPmZ_S |
| 846 | UINT64_C(69238784), // ASR_WIDE_ZZZ_B |
| 847 | UINT64_C(73433088), // ASR_WIDE_ZZZ_H |
| 848 | UINT64_C(77627392), // ASR_WIDE_ZZZ_S |
| 849 | UINT64_C(67141888), // ASR_ZPmI_B |
| 850 | UINT64_C(75530240), // ASR_ZPmI_D |
| 851 | UINT64_C(67142144), // ASR_ZPmI_H |
| 852 | UINT64_C(71335936), // ASR_ZPmI_S |
| 853 | UINT64_C(68190208), // ASR_ZPmZ_B |
| 854 | UINT64_C(80773120), // ASR_ZPmZ_D |
| 855 | UINT64_C(72384512), // ASR_ZPmZ_H |
| 856 | UINT64_C(76578816), // ASR_ZPmZ_S |
| 857 | UINT64_C(69767168), // ASR_ZZI_B |
| 858 | UINT64_C(77631488), // ASR_ZZI_D |
| 859 | UINT64_C(70291456), // ASR_ZZI_H |
| 860 | UINT64_C(73437184), // ASR_ZZI_S |
| 861 | UINT64_C(3670087680), // AUTDA |
| 862 | UINT64_C(3670088704), // AUTDB |
| 863 | UINT64_C(3670096864), // AUTDZA |
| 864 | UINT64_C(3670097888), // AUTDZB |
| 865 | UINT64_C(3670085632), // AUTIA |
| 866 | UINT64_C(3573752223), // AUTIA1716 |
| 867 | UINT64_C(3573752767), // AUTIASP |
| 868 | UINT64_C(3573752735), // AUTIAZ |
| 869 | UINT64_C(3670086656), // AUTIB |
| 870 | UINT64_C(3573752287), // AUTIB1716 |
| 871 | UINT64_C(3573752831), // AUTIBSP |
| 872 | UINT64_C(3573752799), // AUTIBZ |
| 873 | UINT64_C(3670094816), // AUTIZA |
| 874 | UINT64_C(3670095840), // AUTIZB |
| 875 | UINT64_C(3573563487), // AXFLAG |
| 876 | UINT64_C(335544320), // B |
| 877 | UINT64_C(3458203648), // BCAX |
| 878 | UINT64_C(73414656), // BCAX_ZZZZ |
| 879 | UINT64_C(1157673984), // BDEP_ZZZ_B |
| 880 | UINT64_C(1170256896), // BDEP_ZZZ_D |
| 881 | UINT64_C(1161868288), // BDEP_ZZZ_H |
| 882 | UINT64_C(1166062592), // BDEP_ZZZ_S |
| 883 | UINT64_C(1157672960), // BEXT_ZZZ_B |
| 884 | UINT64_C(1170255872), // BEXT_ZZZ_D |
| 885 | UINT64_C(1161867264), // BEXT_ZZZ_H |
| 886 | UINT64_C(1166061568), // BEXT_ZZZ_S |
| 887 | UINT64_C(255913984), // BF16DOTlanev4bf16 |
| 888 | UINT64_C(1329655808), // BF16DOTlanev8bf16 |
| 889 | UINT64_C(509820928), // BFCVT |
| 890 | UINT64_C(245458944), // BFCVTN |
| 891 | UINT64_C(1319200768), // BFCVTN2 |
| 892 | UINT64_C(1686806528), // BFCVTNT_ZPmZ |
| 893 | UINT64_C(1703583744), // BFCVT_ZPmZ |
| 894 | UINT64_C(1684029440), // BFDOT_ZZI |
| 895 | UINT64_C(1684045824), // BFDOT_ZZZ |
| 896 | UINT64_C(776010752), // BFDOTv4bf16 |
| 897 | UINT64_C(1849752576), // BFDOTv8bf16 |
| 898 | UINT64_C(784399360), // BFMLALB |
| 899 | UINT64_C(264302592), // BFMLALBIdx |
| 900 | UINT64_C(1858141184), // BFMLALT |
| 901 | UINT64_C(1338044416), // BFMLALTIdx |
| 902 | UINT64_C(1849748480), // BFMMLA |
| 903 | UINT64_C(1692418048), // BFMMLA_B_ZZI |
| 904 | UINT64_C(1692434432), // BFMMLA_B_ZZZ |
| 905 | UINT64_C(1692419072), // BFMMLA_T_ZZI |
| 906 | UINT64_C(1692435456), // BFMMLA_T_ZZZ |
| 907 | UINT64_C(1684071424), // BFMMLA_ZZZ |
| 908 | UINT64_C(855638016), // BFMWri |
| 909 | UINT64_C(3007315968), // BFMXri |
| 910 | UINT64_C(1157675008), // BGRP_ZZZ_B |
| 911 | UINT64_C(1170257920), // BGRP_ZZZ_D |
| 912 | UINT64_C(1161869312), // BGRP_ZZZ_H |
| 913 | UINT64_C(1166063616), // BGRP_ZZZ_S |
| 914 | UINT64_C(1780482048), // BICSWrs |
| 915 | UINT64_C(3927965696), // BICSXrs |
| 916 | UINT64_C(624967696), // BICS_PPzPP |
| 917 | UINT64_C(169869312), // BICWrs |
| 918 | UINT64_C(2317352960), // BICXrs |
| 919 | UINT64_C(620773392), // BIC_PPzPP |
| 920 | UINT64_C(68878336), // BIC_ZPmZ_B |
| 921 | UINT64_C(81461248), // BIC_ZPmZ_D |
| 922 | UINT64_C(73072640), // BIC_ZPmZ_H |
| 923 | UINT64_C(77266944), // BIC_ZPmZ_S |
| 924 | UINT64_C(81801216), // BIC_ZZZ |
| 925 | UINT64_C(1314921472), // BICv16i8 |
| 926 | UINT64_C(788534272), // BICv2i32 |
| 927 | UINT64_C(788567040), // BICv4i16 |
| 928 | UINT64_C(1862276096), // BICv4i32 |
| 929 | UINT64_C(1862308864), // BICv8i16 |
| 930 | UINT64_C(241179648), // BICv8i8 |
| 931 | UINT64_C(1860180992), // BIFv16i8 |
| 932 | UINT64_C(786439168), // BIFv8i8 |
| 933 | UINT64_C(1855986688), // BITv16i8 |
| 934 | UINT64_C(782244864), // BITv8i8 |
| 935 | UINT64_C(2483027968), // BL |
| 936 | UINT64_C(3594452992), // BLR |
| 937 | UINT64_C(3611232256), // BLRAA |
| 938 | UINT64_C(3594455071), // BLRAAZ |
| 939 | UINT64_C(3611233280), // BLRAB |
| 940 | UINT64_C(3594456095), // BLRABZ |
| 941 | UINT64_C(3592355840), // BR |
| 942 | UINT64_C(3609135104), // BRAA |
| 943 | UINT64_C(3592357919), // BRAAZ |
| 944 | UINT64_C(3609136128), // BRAB |
| 945 | UINT64_C(3592358943), // BRABZ |
| 946 | UINT64_C(3574166175), // BRB_IALL |
| 947 | UINT64_C(3574166207), // BRB_INJ |
| 948 | UINT64_C(3558866944), // BRK |
| 949 | UINT64_C(626016256), // BRKAS_PPzP |
| 950 | UINT64_C(621821968), // BRKA_PPmP |
| 951 | UINT64_C(621821952), // BRKA_PPzP |
| 952 | UINT64_C(634404864), // BRKBS_PPzP |
| 953 | UINT64_C(630210576), // BRKB_PPmP |
| 954 | UINT64_C(630210560), // BRKB_PPzP |
| 955 | UINT64_C(626540544), // BRKNS_PPzP |
| 956 | UINT64_C(622346240), // BRKN_PPzP |
| 957 | UINT64_C(625000448), // BRKPAS_PPzPP |
| 958 | UINT64_C(620806144), // BRKPA_PPzPP |
| 959 | UINT64_C(625000464), // BRKPBS_PPzPP |
| 960 | UINT64_C(620806160), // BRKPB_PPzPP |
| 961 | UINT64_C(73415680), // BSL1N_ZZZZ |
| 962 | UINT64_C(77609984), // BSL2N_ZZZZ |
| 963 | UINT64_C(69221376), // BSL_ZZZZ |
| 964 | UINT64_C(1851792384), // BSLv16i8 |
| 965 | UINT64_C(778050560), // BSLv8i8 |
| 966 | UINT64_C(1409286144), // Bcc |
| 967 | UINT64_C(1157683200), // CADD_ZZI_B |
| 968 | UINT64_C(1170266112), // CADD_ZZI_D |
| 969 | UINT64_C(1161877504), // CADD_ZZI_H |
| 970 | UINT64_C(1166071808), // CADD_ZZI_S |
| 971 | UINT64_C(148929536), // CASAB |
| 972 | UINT64_C(1222671360), // CASAH |
| 973 | UINT64_C(148962304), // CASALB |
| 974 | UINT64_C(1222704128), // CASALH |
| 975 | UINT64_C(2296445952), // CASALW |
| 976 | UINT64_C(3370187776), // CASALX |
| 977 | UINT64_C(2296413184), // CASAW |
| 978 | UINT64_C(3370155008), // CASAX |
| 979 | UINT64_C(144735232), // CASB |
| 980 | UINT64_C(1218477056), // CASH |
| 981 | UINT64_C(144768000), // CASLB |
| 982 | UINT64_C(1218509824), // CASLH |
| 983 | UINT64_C(2292251648), // CASLW |
| 984 | UINT64_C(3365993472), // CASLX |
| 985 | UINT64_C(140573696), // CASPALW |
| 986 | UINT64_C(1214315520), // CASPALX |
| 987 | UINT64_C(140540928), // CASPAW |
| 988 | UINT64_C(1214282752), // CASPAX |
| 989 | UINT64_C(136379392), // CASPLW |
| 990 | UINT64_C(1210121216), // CASPLX |
| 991 | UINT64_C(136346624), // CASPW |
| 992 | UINT64_C(1210088448), // CASPX |
| 993 | UINT64_C(2292218880), // CASW |
| 994 | UINT64_C(3365960704), // CASX |
| 995 | UINT64_C(889192448), // CBNZW |
| 996 | UINT64_C(3036676096), // CBNZX |
| 997 | UINT64_C(872415232), // CBZW |
| 998 | UINT64_C(3019898880), // CBZX |
| 999 | UINT64_C(977274880), // CCMNWi |
| 1000 | UINT64_C(977272832), // CCMNWr |
| 1001 | UINT64_C(3124758528), // CCMNXi |
| 1002 | UINT64_C(3124756480), // CCMNXr |
| 1003 | UINT64_C(2051016704), // CCMPWi |
| 1004 | UINT64_C(2051014656), // CCMPWr |
| 1005 | UINT64_C(4198500352), // CCMPXi |
| 1006 | UINT64_C(4198498304), // CCMPXr |
| 1007 | UINT64_C(1155547136), // CDOT_ZZZI_D |
| 1008 | UINT64_C(1151352832), // CDOT_ZZZI_S |
| 1009 | UINT64_C(1153437696), // CDOT_ZZZ_D |
| 1010 | UINT64_C(1149243392), // CDOT_ZZZ_S |
| 1011 | UINT64_C(3573563423), // CFINV |
| 1012 | UINT64_C(87072768), // CLASTA_RPZ_B |
| 1013 | UINT64_C(99655680), // CLASTA_RPZ_D |
| 1014 | UINT64_C(91267072), // CLASTA_RPZ_H |
| 1015 | UINT64_C(95461376), // CLASTA_RPZ_S |
| 1016 | UINT64_C(86671360), // CLASTA_VPZ_B |
| 1017 | UINT64_C(99254272), // CLASTA_VPZ_D |
| 1018 | UINT64_C(90865664), // CLASTA_VPZ_H |
| 1019 | UINT64_C(95059968), // CLASTA_VPZ_S |
| 1020 | UINT64_C(86540288), // CLASTA_ZPZ_B |
| 1021 | UINT64_C(99123200), // CLASTA_ZPZ_D |
| 1022 | UINT64_C(90734592), // CLASTA_ZPZ_H |
| 1023 | UINT64_C(94928896), // CLASTA_ZPZ_S |
| 1024 | UINT64_C(87138304), // CLASTB_RPZ_B |
| 1025 | UINT64_C(99721216), // CLASTB_RPZ_D |
| 1026 | UINT64_C(91332608), // CLASTB_RPZ_H |
| 1027 | UINT64_C(95526912), // CLASTB_RPZ_S |
| 1028 | UINT64_C(86736896), // CLASTB_VPZ_B |
| 1029 | UINT64_C(99319808), // CLASTB_VPZ_D |
| 1030 | UINT64_C(90931200), // CLASTB_VPZ_H |
| 1031 | UINT64_C(95125504), // CLASTB_VPZ_S |
| 1032 | UINT64_C(86605824), // CLASTB_ZPZ_B |
| 1033 | UINT64_C(99188736), // CLASTB_ZPZ_D |
| 1034 | UINT64_C(90800128), // CLASTB_ZPZ_H |
| 1035 | UINT64_C(94994432), // CLASTB_ZPZ_S |
| 1036 | UINT64_C(3573755999), // CLREX |
| 1037 | UINT64_C(1522537472), // CLSWr |
| 1038 | UINT64_C(3670021120), // CLSXr |
| 1039 | UINT64_C(68722688), // CLS_ZPmZ_B |
| 1040 | UINT64_C(81305600), // CLS_ZPmZ_D |
| 1041 | UINT64_C(72916992), // CLS_ZPmZ_H |
| 1042 | UINT64_C(77111296), // CLS_ZPmZ_S |
| 1043 | UINT64_C(1310738432), // CLSv16i8 |
| 1044 | UINT64_C(245385216), // CLSv2i32 |
| 1045 | UINT64_C(241190912), // CLSv4i16 |
| 1046 | UINT64_C(1319127040), // CLSv4i32 |
| 1047 | UINT64_C(1314932736), // CLSv8i16 |
| 1048 | UINT64_C(236996608), // CLSv8i8 |
| 1049 | UINT64_C(1522536448), // CLZWr |
| 1050 | UINT64_C(3670020096), // CLZXr |
| 1051 | UINT64_C(68788224), // CLZ_ZPmZ_B |
| 1052 | UINT64_C(81371136), // CLZ_ZPmZ_D |
| 1053 | UINT64_C(72982528), // CLZ_ZPmZ_H |
| 1054 | UINT64_C(77176832), // CLZ_ZPmZ_S |
| 1055 | UINT64_C(1847609344), // CLZv16i8 |
| 1056 | UINT64_C(782256128), // CLZv2i32 |
| 1057 | UINT64_C(778061824), // CLZv4i16 |
| 1058 | UINT64_C(1855997952), // CLZv4i32 |
| 1059 | UINT64_C(1851803648), // CLZv8i16 |
| 1060 | UINT64_C(773867520), // CLZv8i8 |
| 1061 | UINT64_C(1847626752), // CMEQv16i8 |
| 1062 | UINT64_C(1310758912), // CMEQv16i8rz |
| 1063 | UINT64_C(2128645120), // CMEQv1i64 |
| 1064 | UINT64_C(1591777280), // CMEQv1i64rz |
| 1065 | UINT64_C(782273536), // CMEQv2i32 |
| 1066 | UINT64_C(245405696), // CMEQv2i32rz |
| 1067 | UINT64_C(1860209664), // CMEQv2i64 |
| 1068 | UINT64_C(1323341824), // CMEQv2i64rz |
| 1069 | UINT64_C(778079232), // CMEQv4i16 |
| 1070 | UINT64_C(241211392), // CMEQv4i16rz |
| 1071 | UINT64_C(1856015360), // CMEQv4i32 |
| 1072 | UINT64_C(1319147520), // CMEQv4i32rz |
| 1073 | UINT64_C(1851821056), // CMEQv8i16 |
| 1074 | UINT64_C(1314953216), // CMEQv8i16rz |
| 1075 | UINT64_C(773884928), // CMEQv8i8 |
| 1076 | UINT64_C(237017088), // CMEQv8i8rz |
| 1077 | UINT64_C(1310735360), // CMGEv16i8 |
| 1078 | UINT64_C(1847625728), // CMGEv16i8rz |
| 1079 | UINT64_C(1591753728), // CMGEv1i64 |
| 1080 | UINT64_C(2128644096), // CMGEv1i64rz |
| 1081 | UINT64_C(245382144), // CMGEv2i32 |
| 1082 | UINT64_C(782272512), // CMGEv2i32rz |
| 1083 | UINT64_C(1323318272), // CMGEv2i64 |
| 1084 | UINT64_C(1860208640), // CMGEv2i64rz |
| 1085 | UINT64_C(241187840), // CMGEv4i16 |
| 1086 | UINT64_C(778078208), // CMGEv4i16rz |
| 1087 | UINT64_C(1319123968), // CMGEv4i32 |
| 1088 | UINT64_C(1856014336), // CMGEv4i32rz |
| 1089 | UINT64_C(1314929664), // CMGEv8i16 |
| 1090 | UINT64_C(1851820032), // CMGEv8i16rz |
| 1091 | UINT64_C(236993536), // CMGEv8i8 |
| 1092 | UINT64_C(773883904), // CMGEv8i8rz |
| 1093 | UINT64_C(1310733312), // CMGTv16i8 |
| 1094 | UINT64_C(1310754816), // CMGTv16i8rz |
| 1095 | UINT64_C(1591751680), // CMGTv1i64 |
| 1096 | UINT64_C(1591773184), // CMGTv1i64rz |
| 1097 | UINT64_C(245380096), // CMGTv2i32 |
| 1098 | UINT64_C(245401600), // CMGTv2i32rz |
| 1099 | UINT64_C(1323316224), // CMGTv2i64 |
| 1100 | UINT64_C(1323337728), // CMGTv2i64rz |
| 1101 | UINT64_C(241185792), // CMGTv4i16 |
| 1102 | UINT64_C(241207296), // CMGTv4i16rz |
| 1103 | UINT64_C(1319121920), // CMGTv4i32 |
| 1104 | UINT64_C(1319143424), // CMGTv4i32rz |
| 1105 | UINT64_C(1314927616), // CMGTv8i16 |
| 1106 | UINT64_C(1314949120), // CMGTv8i16rz |
| 1107 | UINT64_C(236991488), // CMGTv8i8 |
| 1108 | UINT64_C(237012992), // CMGTv8i8rz |
| 1109 | UINT64_C(1847604224), // CMHIv16i8 |
| 1110 | UINT64_C(2128622592), // CMHIv1i64 |
| 1111 | UINT64_C(782251008), // CMHIv2i32 |
| 1112 | UINT64_C(1860187136), // CMHIv2i64 |
| 1113 | UINT64_C(778056704), // CMHIv4i16 |
| 1114 | UINT64_C(1855992832), // CMHIv4i32 |
| 1115 | UINT64_C(1851798528), // CMHIv8i16 |
| 1116 | UINT64_C(773862400), // CMHIv8i8 |
| 1117 | UINT64_C(1847606272), // CMHSv16i8 |
| 1118 | UINT64_C(2128624640), // CMHSv1i64 |
| 1119 | UINT64_C(782253056), // CMHSv2i32 |
| 1120 | UINT64_C(1860189184), // CMHSv2i64 |
| 1121 | UINT64_C(778058752), // CMHSv4i16 |
| 1122 | UINT64_C(1855994880), // CMHSv4i32 |
| 1123 | UINT64_C(1851800576), // CMHSv8i16 |
| 1124 | UINT64_C(773864448), // CMHSv8i8 |
| 1125 | UINT64_C(1151361024), // CMLA_ZZZI_H |
| 1126 | UINT64_C(1155555328), // CMLA_ZZZI_S |
| 1127 | UINT64_C(1140858880), // CMLA_ZZZ_B |
| 1128 | UINT64_C(1153441792), // CMLA_ZZZ_D |
| 1129 | UINT64_C(1145053184), // CMLA_ZZZ_H |
| 1130 | UINT64_C(1149247488), // CMLA_ZZZ_S |
| 1131 | UINT64_C(1847629824), // CMLEv16i8rz |
| 1132 | UINT64_C(2128648192), // CMLEv1i64rz |
| 1133 | UINT64_C(782276608), // CMLEv2i32rz |
| 1134 | UINT64_C(1860212736), // CMLEv2i64rz |
| 1135 | UINT64_C(778082304), // CMLEv4i16rz |
| 1136 | UINT64_C(1856018432), // CMLEv4i32rz |
| 1137 | UINT64_C(1851824128), // CMLEv8i16rz |
| 1138 | UINT64_C(773888000), // CMLEv8i8rz |
| 1139 | UINT64_C(1310763008), // CMLTv16i8rz |
| 1140 | UINT64_C(1591781376), // CMLTv1i64rz |
| 1141 | UINT64_C(245409792), // CMLTv2i32rz |
| 1142 | UINT64_C(1323345920), // CMLTv2i64rz |
| 1143 | UINT64_C(241215488), // CMLTv4i16rz |
| 1144 | UINT64_C(1319151616), // CMLTv4i32rz |
| 1145 | UINT64_C(1314957312), // CMLTv8i16rz |
| 1146 | UINT64_C(237021184), // CMLTv8i8rz |
| 1147 | UINT64_C(620789760), // CMPEQ_PPzZI_B |
| 1148 | UINT64_C(633372672), // CMPEQ_PPzZI_D |
| 1149 | UINT64_C(624984064), // CMPEQ_PPzZI_H |
| 1150 | UINT64_C(629178368), // CMPEQ_PPzZI_S |
| 1151 | UINT64_C(604020736), // CMPEQ_PPzZZ_B |
| 1152 | UINT64_C(616603648), // CMPEQ_PPzZZ_D |
| 1153 | UINT64_C(608215040), // CMPEQ_PPzZZ_H |
| 1154 | UINT64_C(612409344), // CMPEQ_PPzZZ_S |
| 1155 | UINT64_C(603987968), // CMPEQ_WIDE_PPzZZ_B |
| 1156 | UINT64_C(608182272), // CMPEQ_WIDE_PPzZZ_H |
| 1157 | UINT64_C(612376576), // CMPEQ_WIDE_PPzZZ_S |
| 1158 | UINT64_C(620756992), // CMPGE_PPzZI_B |
| 1159 | UINT64_C(633339904), // CMPGE_PPzZI_D |
| 1160 | UINT64_C(624951296), // CMPGE_PPzZI_H |
| 1161 | UINT64_C(629145600), // CMPGE_PPzZI_S |
| 1162 | UINT64_C(604012544), // CMPGE_PPzZZ_B |
| 1163 | UINT64_C(616595456), // CMPGE_PPzZZ_D |
| 1164 | UINT64_C(608206848), // CMPGE_PPzZZ_H |
| 1165 | UINT64_C(612401152), // CMPGE_PPzZZ_S |
| 1166 | UINT64_C(603996160), // CMPGE_WIDE_PPzZZ_B |
| 1167 | UINT64_C(608190464), // CMPGE_WIDE_PPzZZ_H |
| 1168 | UINT64_C(612384768), // CMPGE_WIDE_PPzZZ_S |
| 1169 | UINT64_C(620757008), // CMPGT_PPzZI_B |
| 1170 | UINT64_C(633339920), // CMPGT_PPzZI_D |
| 1171 | UINT64_C(624951312), // CMPGT_PPzZI_H |
| 1172 | UINT64_C(629145616), // CMPGT_PPzZI_S |
| 1173 | UINT64_C(604012560), // CMPGT_PPzZZ_B |
| 1174 | UINT64_C(616595472), // CMPGT_PPzZZ_D |
| 1175 | UINT64_C(608206864), // CMPGT_PPzZZ_H |
| 1176 | UINT64_C(612401168), // CMPGT_PPzZZ_S |
| 1177 | UINT64_C(603996176), // CMPGT_WIDE_PPzZZ_B |
| 1178 | UINT64_C(608190480), // CMPGT_WIDE_PPzZZ_H |
| 1179 | UINT64_C(612384784), // CMPGT_WIDE_PPzZZ_S |
| 1180 | UINT64_C(606076944), // CMPHI_PPzZI_B |
| 1181 | UINT64_C(618659856), // CMPHI_PPzZI_D |
| 1182 | UINT64_C(610271248), // CMPHI_PPzZI_H |
| 1183 | UINT64_C(614465552), // CMPHI_PPzZI_S |
| 1184 | UINT64_C(603979792), // CMPHI_PPzZZ_B |
| 1185 | UINT64_C(616562704), // CMPHI_PPzZZ_D |
| 1186 | UINT64_C(608174096), // CMPHI_PPzZZ_H |
| 1187 | UINT64_C(612368400), // CMPHI_PPzZZ_S |
| 1188 | UINT64_C(604028944), // CMPHI_WIDE_PPzZZ_B |
| 1189 | UINT64_C(608223248), // CMPHI_WIDE_PPzZZ_H |
| 1190 | UINT64_C(612417552), // CMPHI_WIDE_PPzZZ_S |
| 1191 | UINT64_C(606076928), // CMPHS_PPzZI_B |
| 1192 | UINT64_C(618659840), // CMPHS_PPzZI_D |
| 1193 | UINT64_C(610271232), // CMPHS_PPzZI_H |
| 1194 | UINT64_C(614465536), // CMPHS_PPzZI_S |
| 1195 | UINT64_C(603979776), // CMPHS_PPzZZ_B |
| 1196 | UINT64_C(616562688), // CMPHS_PPzZZ_D |
| 1197 | UINT64_C(608174080), // CMPHS_PPzZZ_H |
| 1198 | UINT64_C(612368384), // CMPHS_PPzZZ_S |
| 1199 | UINT64_C(604028928), // CMPHS_WIDE_PPzZZ_B |
| 1200 | UINT64_C(608223232), // CMPHS_WIDE_PPzZZ_H |
| 1201 | UINT64_C(612417536), // CMPHS_WIDE_PPzZZ_S |
| 1202 | UINT64_C(620765200), // CMPLE_PPzZI_B |
| 1203 | UINT64_C(633348112), // CMPLE_PPzZI_D |
| 1204 | UINT64_C(624959504), // CMPLE_PPzZI_H |
| 1205 | UINT64_C(629153808), // CMPLE_PPzZI_S |
| 1206 | UINT64_C(604004368), // CMPLE_WIDE_PPzZZ_B |
| 1207 | UINT64_C(608198672), // CMPLE_WIDE_PPzZZ_H |
| 1208 | UINT64_C(612392976), // CMPLE_WIDE_PPzZZ_S |
| 1209 | UINT64_C(606085120), // CMPLO_PPzZI_B |
| 1210 | UINT64_C(618668032), // CMPLO_PPzZI_D |
| 1211 | UINT64_C(610279424), // CMPLO_PPzZI_H |
| 1212 | UINT64_C(614473728), // CMPLO_PPzZI_S |
| 1213 | UINT64_C(604037120), // CMPLO_WIDE_PPzZZ_B |
| 1214 | UINT64_C(608231424), // CMPLO_WIDE_PPzZZ_H |
| 1215 | UINT64_C(612425728), // CMPLO_WIDE_PPzZZ_S |
| 1216 | UINT64_C(606085136), // CMPLS_PPzZI_B |
| 1217 | UINT64_C(618668048), // CMPLS_PPzZI_D |
| 1218 | UINT64_C(610279440), // CMPLS_PPzZI_H |
| 1219 | UINT64_C(614473744), // CMPLS_PPzZI_S |
| 1220 | UINT64_C(604037136), // CMPLS_WIDE_PPzZZ_B |
| 1221 | UINT64_C(608231440), // CMPLS_WIDE_PPzZZ_H |
| 1222 | UINT64_C(612425744), // CMPLS_WIDE_PPzZZ_S |
| 1223 | UINT64_C(620765184), // CMPLT_PPzZI_B |
| 1224 | UINT64_C(633348096), // CMPLT_PPzZI_D |
| 1225 | UINT64_C(624959488), // CMPLT_PPzZI_H |
| 1226 | UINT64_C(629153792), // CMPLT_PPzZI_S |
| 1227 | UINT64_C(604004352), // CMPLT_WIDE_PPzZZ_B |
| 1228 | UINT64_C(608198656), // CMPLT_WIDE_PPzZZ_H |
| 1229 | UINT64_C(612392960), // CMPLT_WIDE_PPzZZ_S |
| 1230 | UINT64_C(620789776), // CMPNE_PPzZI_B |
| 1231 | UINT64_C(633372688), // CMPNE_PPzZI_D |
| 1232 | UINT64_C(624984080), // CMPNE_PPzZI_H |
| 1233 | UINT64_C(629178384), // CMPNE_PPzZI_S |
| 1234 | UINT64_C(604020752), // CMPNE_PPzZZ_B |
| 1235 | UINT64_C(616603664), // CMPNE_PPzZZ_D |
| 1236 | UINT64_C(608215056), // CMPNE_PPzZZ_H |
| 1237 | UINT64_C(612409360), // CMPNE_PPzZZ_S |
| 1238 | UINT64_C(603987984), // CMPNE_WIDE_PPzZZ_B |
| 1239 | UINT64_C(608182288), // CMPNE_WIDE_PPzZZ_H |
| 1240 | UINT64_C(612376592), // CMPNE_WIDE_PPzZZ_S |
| 1241 | UINT64_C(1310755840), // CMTSTv16i8 |
| 1242 | UINT64_C(1591774208), // CMTSTv1i64 |
| 1243 | UINT64_C(245402624), // CMTSTv2i32 |
| 1244 | UINT64_C(1323338752), // CMTSTv2i64 |
| 1245 | UINT64_C(241208320), // CMTSTv4i16 |
| 1246 | UINT64_C(1319144448), // CMTSTv4i32 |
| 1247 | UINT64_C(1314950144), // CMTSTv8i16 |
| 1248 | UINT64_C(237014016), // CMTSTv8i8 |
| 1249 | UINT64_C(68919296), // CNOT_ZPmZ_B |
| 1250 | UINT64_C(81502208), // CNOT_ZPmZ_D |
| 1251 | UINT64_C(73113600), // CNOT_ZPmZ_H |
| 1252 | UINT64_C(77307904), // CNOT_ZPmZ_S |
| 1253 | UINT64_C(69263360), // CNTB_XPiI |
| 1254 | UINT64_C(81846272), // CNTD_XPiI |
| 1255 | UINT64_C(73457664), // CNTH_XPiI |
| 1256 | UINT64_C(622886912), // CNTP_XPP_B |
| 1257 | UINT64_C(635469824), // CNTP_XPP_D |
| 1258 | UINT64_C(627081216), // CNTP_XPP_H |
| 1259 | UINT64_C(631275520), // CNTP_XPP_S |
| 1260 | UINT64_C(77651968), // CNTW_XPiI |
| 1261 | UINT64_C(68853760), // CNT_ZPmZ_B |
| 1262 | UINT64_C(81436672), // CNT_ZPmZ_D |
| 1263 | UINT64_C(73048064), // CNT_ZPmZ_H |
| 1264 | UINT64_C(77242368), // CNT_ZPmZ_S |
| 1265 | UINT64_C(1310742528), // CNTv16i8 |
| 1266 | UINT64_C(237000704), // CNTv8i8 |
| 1267 | UINT64_C(98664448), // COMPACT_ZPZ_D |
| 1268 | UINT64_C(94470144), // COMPACT_ZPZ_S |
| 1269 | UINT64_C(84951040), // CPY_ZPmI_B |
| 1270 | UINT64_C(97533952), // CPY_ZPmI_D |
| 1271 | UINT64_C(89145344), // CPY_ZPmI_H |
| 1272 | UINT64_C(93339648), // CPY_ZPmI_S |
| 1273 | UINT64_C(86548480), // CPY_ZPmR_B |
| 1274 | UINT64_C(99131392), // CPY_ZPmR_D |
| 1275 | UINT64_C(90742784), // CPY_ZPmR_H |
| 1276 | UINT64_C(94937088), // CPY_ZPmR_S |
| 1277 | UINT64_C(86016000), // CPY_ZPmV_B |
| 1278 | UINT64_C(98598912), // CPY_ZPmV_D |
| 1279 | UINT64_C(90210304), // CPY_ZPmV_H |
| 1280 | UINT64_C(94404608), // CPY_ZPmV_S |
| 1281 | UINT64_C(84934656), // CPY_ZPzI_B |
| 1282 | UINT64_C(97517568), // CPY_ZPzI_D |
| 1283 | UINT64_C(89128960), // CPY_ZPzI_H |
| 1284 | UINT64_C(93323264), // CPY_ZPzI_S |
| 1285 | UINT64_C(1577190400), // CPYi16 |
| 1286 | UINT64_C(1577321472), // CPYi32 |
| 1287 | UINT64_C(1577583616), // CPYi64 |
| 1288 | UINT64_C(1577124864), // CPYi8 |
| 1289 | UINT64_C(448806912), // CRC32Brr |
| 1290 | UINT64_C(448811008), // CRC32CBrr |
| 1291 | UINT64_C(448812032), // CRC32CHrr |
| 1292 | UINT64_C(448813056), // CRC32CWrr |
| 1293 | UINT64_C(2596297728), // CRC32CXrr |
| 1294 | UINT64_C(448807936), // CRC32Hrr |
| 1295 | UINT64_C(448808960), // CRC32Wrr |
| 1296 | UINT64_C(2596293632), // CRC32Xrr |
| 1297 | UINT64_C(444596224), // CSELWr |
| 1298 | UINT64_C(2592079872), // CSELXr |
| 1299 | UINT64_C(444597248), // CSINCWr |
| 1300 | UINT64_C(2592080896), // CSINCXr |
| 1301 | UINT64_C(1518338048), // CSINVWr |
| 1302 | UINT64_C(3665821696), // CSINVXr |
| 1303 | UINT64_C(1518339072), // CSNEGWr |
| 1304 | UINT64_C(3665822720), // CSNEGXr |
| 1305 | UINT64_C(631250944), // CTERMEQ_WW |
| 1306 | UINT64_C(635445248), // CTERMEQ_XX |
| 1307 | UINT64_C(631250960), // CTERMNE_WW |
| 1308 | UINT64_C(635445264), // CTERMNE_XX |
| 1309 | UINT64_C(3567255553), // DCPS1 |
| 1310 | UINT64_C(3567255554), // DCPS2 |
| 1311 | UINT64_C(3567255555), // DCPS3 |
| 1312 | UINT64_C(70312960), // DECB_XPiI |
| 1313 | UINT64_C(82895872), // DECD_XPiI |
| 1314 | UINT64_C(82887680), // DECD_ZPiI |
| 1315 | UINT64_C(74507264), // DECH_XPiI |
| 1316 | UINT64_C(74499072), // DECH_ZPiI |
| 1317 | UINT64_C(623740928), // DECP_XP_B |
| 1318 | UINT64_C(636323840), // DECP_XP_D |
| 1319 | UINT64_C(627935232), // DECP_XP_H |
| 1320 | UINT64_C(632129536), // DECP_XP_S |
| 1321 | UINT64_C(636321792), // DECP_ZP_D |
| 1322 | UINT64_C(627933184), // DECP_ZP_H |
| 1323 | UINT64_C(632127488), // DECP_ZP_S |
| 1324 | UINT64_C(78701568), // DECW_XPiI |
| 1325 | UINT64_C(78693376), // DECW_ZPiI |
| 1326 | UINT64_C(3573756095), // DMB |
| 1327 | UINT64_C(3602842592), // DRPS |
| 1328 | UINT64_C(3573756063), // DSB |
| 1329 | UINT64_C(3573756479), // DSBnXS |
| 1330 | UINT64_C(96468992), // DUPM_ZI |
| 1331 | UINT64_C(624476160), // DUP_ZI_B |
| 1332 | UINT64_C(637059072), // DUP_ZI_D |
| 1333 | UINT64_C(628670464), // DUP_ZI_H |
| 1334 | UINT64_C(632864768), // DUP_ZI_S |
| 1335 | UINT64_C(85997568), // DUP_ZR_B |
| 1336 | UINT64_C(98580480), // DUP_ZR_D |
| 1337 | UINT64_C(90191872), // DUP_ZR_H |
| 1338 | UINT64_C(94386176), // DUP_ZR_S |
| 1339 | UINT64_C(86056960), // DUP_ZZI_B |
| 1340 | UINT64_C(86515712), // DUP_ZZI_D |
| 1341 | UINT64_C(86122496), // DUP_ZZI_H |
| 1342 | UINT64_C(87040000), // DUP_ZZI_Q |
| 1343 | UINT64_C(86253568), // DUP_ZZI_S |
| 1344 | UINT64_C(1308691456), // DUPv16i8gpr |
| 1345 | UINT64_C(1308689408), // DUPv16i8lane |
| 1346 | UINT64_C(235146240), // DUPv2i32gpr |
| 1347 | UINT64_C(235144192), // DUPv2i32lane |
| 1348 | UINT64_C(1309150208), // DUPv2i64gpr |
| 1349 | UINT64_C(1309148160), // DUPv2i64lane |
| 1350 | UINT64_C(235015168), // DUPv4i16gpr |
| 1351 | UINT64_C(235013120), // DUPv4i16lane |
| 1352 | UINT64_C(1308888064), // DUPv4i32gpr |
| 1353 | UINT64_C(1308886016), // DUPv4i32lane |
| 1354 | UINT64_C(1308756992), // DUPv8i16gpr |
| 1355 | UINT64_C(1308754944), // DUPv8i16lane |
| 1356 | UINT64_C(234949632), // DUPv8i8gpr |
| 1357 | UINT64_C(234947584), // DUPv8i8lane |
| 1358 | UINT64_C(1243611136), // EONWrs |
| 1359 | UINT64_C(3391094784), // EONXrs |
| 1360 | UINT64_C(3456106496), // EOR3 |
| 1361 | UINT64_C(69220352), // EOR3_ZZZZ |
| 1362 | UINT64_C(1157664768), // EORBT_ZZZ_B |
| 1363 | UINT64_C(1170247680), // EORBT_ZZZ_D |
| 1364 | UINT64_C(1161859072), // EORBT_ZZZ_H |
| 1365 | UINT64_C(1166053376), // EORBT_ZZZ_S |
| 1366 | UINT64_C(624968192), // EORS_PPzPP |
| 1367 | UINT64_C(1157665792), // EORTB_ZZZ_B |
| 1368 | UINT64_C(1170248704), // EORTB_ZZZ_D |
| 1369 | UINT64_C(1161860096), // EORTB_ZZZ_H |
| 1370 | UINT64_C(1166054400), // EORTB_ZZZ_S |
| 1371 | UINT64_C(68755456), // EORV_VPZ_B |
| 1372 | UINT64_C(81338368), // EORV_VPZ_D |
| 1373 | UINT64_C(72949760), // EORV_VPZ_H |
| 1374 | UINT64_C(77144064), // EORV_VPZ_S |
| 1375 | UINT64_C(1375731712), // EORWri |
| 1376 | UINT64_C(1241513984), // EORWrs |
| 1377 | UINT64_C(3523215360), // EORXri |
| 1378 | UINT64_C(3388997632), // EORXrs |
| 1379 | UINT64_C(620773888), // EOR_PPzPP |
| 1380 | UINT64_C(88080384), // EOR_ZI |
| 1381 | UINT64_C(68747264), // EOR_ZPmZ_B |
| 1382 | UINT64_C(81330176), // EOR_ZPmZ_D |
| 1383 | UINT64_C(72941568), // EOR_ZPmZ_H |
| 1384 | UINT64_C(77135872), // EOR_ZPmZ_S |
| 1385 | UINT64_C(77606912), // EOR_ZZZ |
| 1386 | UINT64_C(1847598080), // EORv16i8 |
| 1387 | UINT64_C(773856256), // EORv8i8 |
| 1388 | UINT64_C(3600745440), // ERET |
| 1389 | UINT64_C(3600747519), // ERETAA |
| 1390 | UINT64_C(3600748543), // ERETAB |
| 1391 | UINT64_C(327155712), // EXTRWrri |
| 1392 | UINT64_C(2478833664), // EXTRXrri |
| 1393 | UINT64_C(85983232), // EXT_ZZI |
| 1394 | UINT64_C(90177536), // EXT_ZZI_B |
| 1395 | UINT64_C(1845493760), // EXTv16i8 |
| 1396 | UINT64_C(771751936), // EXTv8i8 |
| 1397 | UINT64_C(2126517248), // FABD16 |
| 1398 | UINT64_C(2124469248), // FABD32 |
| 1399 | UINT64_C(2128663552), // FABD64 |
| 1400 | UINT64_C(1707638784), // FABD_ZPmZ_D |
| 1401 | UINT64_C(1699250176), // FABD_ZPmZ_H |
| 1402 | UINT64_C(1703444480), // FABD_ZPmZ_S |
| 1403 | UINT64_C(782291968), // FABDv2f32 |
| 1404 | UINT64_C(1860228096), // FABDv2f64 |
| 1405 | UINT64_C(784339968), // FABDv4f16 |
| 1406 | UINT64_C(1856033792), // FABDv4f32 |
| 1407 | UINT64_C(1858081792), // FABDv8f16 |
| 1408 | UINT64_C(509657088), // FABSDr |
| 1409 | UINT64_C(518045696), // FABSHr |
| 1410 | UINT64_C(505462784), // FABSSr |
| 1411 | UINT64_C(81567744), // FABS_ZPmZ_D |
| 1412 | UINT64_C(73179136), // FABS_ZPmZ_H |
| 1413 | UINT64_C(77373440), // FABS_ZPmZ_S |
| 1414 | UINT64_C(245430272), // FABSv2f32 |
| 1415 | UINT64_C(1323366400), // FABSv2f64 |
| 1416 | UINT64_C(251197440), // FABSv4f16 |
| 1417 | UINT64_C(1319172096), // FABSv4f32 |
| 1418 | UINT64_C(1324939264), // FABSv8f16 |
| 1419 | UINT64_C(2118134784), // FACGE16 |
| 1420 | UINT64_C(2116086784), // FACGE32 |
| 1421 | UINT64_C(2120281088), // FACGE64 |
| 1422 | UINT64_C(1707130896), // FACGE_PPzZZ_D |
| 1423 | UINT64_C(1698742288), // FACGE_PPzZZ_H |
| 1424 | UINT64_C(1702936592), // FACGE_PPzZZ_S |
| 1425 | UINT64_C(773909504), // FACGEv2f32 |
| 1426 | UINT64_C(1851845632), // FACGEv2f64 |
| 1427 | UINT64_C(775957504), // FACGEv4f16 |
| 1428 | UINT64_C(1847651328), // FACGEv4f32 |
| 1429 | UINT64_C(1849699328), // FACGEv8f16 |
| 1430 | UINT64_C(2126523392), // FACGT16 |
| 1431 | UINT64_C(2124475392), // FACGT32 |
| 1432 | UINT64_C(2128669696), // FACGT64 |
| 1433 | UINT64_C(1707139088), // FACGT_PPzZZ_D |
| 1434 | UINT64_C(1698750480), // FACGT_PPzZZ_H |
| 1435 | UINT64_C(1702944784), // FACGT_PPzZZ_S |
| 1436 | UINT64_C(782298112), // FACGTv2f32 |
| 1437 | UINT64_C(1860234240), // FACGTv2f64 |
| 1438 | UINT64_C(784346112), // FACGTv4f16 |
| 1439 | UINT64_C(1856039936), // FACGTv4f32 |
| 1440 | UINT64_C(1858087936), // FACGTv8f16 |
| 1441 | UINT64_C(1708662784), // FADDA_VPZ_D |
| 1442 | UINT64_C(1700274176), // FADDA_VPZ_H |
| 1443 | UINT64_C(1704468480), // FADDA_VPZ_S |
| 1444 | UINT64_C(509618176), // FADDDrr |
| 1445 | UINT64_C(518006784), // FADDHrr |
| 1446 | UINT64_C(1691385856), // FADDP_ZPmZZ_D |
| 1447 | UINT64_C(1682997248), // FADDP_ZPmZZ_H |
| 1448 | UINT64_C(1687191552), // FADDP_ZPmZZ_S |
| 1449 | UINT64_C(773903360), // FADDPv2f32 |
| 1450 | UINT64_C(1851839488), // FADDPv2f64 |
| 1451 | UINT64_C(1580259328), // FADDPv2i16p |
| 1452 | UINT64_C(2117130240), // FADDPv2i32p |
| 1453 | UINT64_C(2121324544), // FADDPv2i64p |
| 1454 | UINT64_C(775951360), // FADDPv4f16 |
| 1455 | UINT64_C(1847645184), // FADDPv4f32 |
| 1456 | UINT64_C(1849693184), // FADDPv8f16 |
| 1457 | UINT64_C(505423872), // FADDSrr |
| 1458 | UINT64_C(1707089920), // FADDV_VPZ_D |
| 1459 | UINT64_C(1698701312), // FADDV_VPZ_H |
| 1460 | UINT64_C(1702895616), // FADDV_VPZ_S |
| 1461 | UINT64_C(1708687360), // FADD_ZPmI_D |
| 1462 | UINT64_C(1700298752), // FADD_ZPmI_H |
| 1463 | UINT64_C(1704493056), // FADD_ZPmI_S |
| 1464 | UINT64_C(1707114496), // FADD_ZPmZ_D |
| 1465 | UINT64_C(1698725888), // FADD_ZPmZ_H |
| 1466 | UINT64_C(1702920192), // FADD_ZPmZ_S |
| 1467 | UINT64_C(1707081728), // FADD_ZZZ_D |
| 1468 | UINT64_C(1698693120), // FADD_ZZZ_H |
| 1469 | UINT64_C(1702887424), // FADD_ZZZ_S |
| 1470 | UINT64_C(237032448), // FADDv2f32 |
| 1471 | UINT64_C(1314968576), // FADDv2f64 |
| 1472 | UINT64_C(239080448), // FADDv4f16 |
| 1473 | UINT64_C(1310774272), // FADDv4f32 |
| 1474 | UINT64_C(1312822272), // FADDv8f16 |
| 1475 | UINT64_C(1690337280), // FCADD_ZPmZ_D |
| 1476 | UINT64_C(1681948672), // FCADD_ZPmZ_H |
| 1477 | UINT64_C(1686142976), // FCADD_ZPmZ_S |
| 1478 | UINT64_C(780198912), // FCADDv2f32 |
| 1479 | UINT64_C(1858135040), // FCADDv2f64 |
| 1480 | UINT64_C(776004608), // FCADDv4f16 |
| 1481 | UINT64_C(1853940736), // FCADDv4f32 |
| 1482 | UINT64_C(1849746432), // FCADDv8f16 |
| 1483 | UINT64_C(509608960), // FCCMPDrr |
| 1484 | UINT64_C(509608976), // FCCMPEDrr |
| 1485 | UINT64_C(517997584), // FCCMPEHrr |
| 1486 | UINT64_C(505414672), // FCCMPESrr |
| 1487 | UINT64_C(517997568), // FCCMPHrr |
| 1488 | UINT64_C(505414656), // FCCMPSrr |
| 1489 | UINT64_C(1581261824), // FCMEQ16 |
| 1490 | UINT64_C(1579213824), // FCMEQ32 |
| 1491 | UINT64_C(1583408128), // FCMEQ64 |
| 1492 | UINT64_C(1708269568), // FCMEQ_PPzZ0_D |
| 1493 | UINT64_C(1699880960), // FCMEQ_PPzZ0_H |
| 1494 | UINT64_C(1704075264), // FCMEQ_PPzZ0_S |
| 1495 | UINT64_C(1707106304), // FCMEQ_PPzZZ_D |
| 1496 | UINT64_C(1698717696), // FCMEQ_PPzZZ_H |
| 1497 | UINT64_C(1702912000), // FCMEQ_PPzZZ_S |
| 1498 | UINT64_C(1593366528), // FCMEQv1i16rz |
| 1499 | UINT64_C(1587599360), // FCMEQv1i32rz |
| 1500 | UINT64_C(1591793664), // FCMEQv1i64rz |
| 1501 | UINT64_C(237036544), // FCMEQv2f32 |
| 1502 | UINT64_C(1314972672), // FCMEQv2f64 |
| 1503 | UINT64_C(245422080), // FCMEQv2i32rz |
| 1504 | UINT64_C(1323358208), // FCMEQv2i64rz |
| 1505 | UINT64_C(239084544), // FCMEQv4f16 |
| 1506 | UINT64_C(1310778368), // FCMEQv4f32 |
| 1507 | UINT64_C(251189248), // FCMEQv4i16rz |
| 1508 | UINT64_C(1319163904), // FCMEQv4i32rz |
| 1509 | UINT64_C(1312826368), // FCMEQv8f16 |
| 1510 | UINT64_C(1324931072), // FCMEQv8i16rz |
| 1511 | UINT64_C(2118132736), // FCMGE16 |
| 1512 | UINT64_C(2116084736), // FCMGE32 |
| 1513 | UINT64_C(2120279040), // FCMGE64 |
| 1514 | UINT64_C(1708138496), // FCMGE_PPzZ0_D |
| 1515 | UINT64_C(1699749888), // FCMGE_PPzZ0_H |
| 1516 | UINT64_C(1703944192), // FCMGE_PPzZ0_S |
| 1517 | UINT64_C(1707098112), // FCMGE_PPzZZ_D |
| 1518 | UINT64_C(1698709504), // FCMGE_PPzZZ_H |
| 1519 | UINT64_C(1702903808), // FCMGE_PPzZZ_S |
| 1520 | UINT64_C(2130233344), // FCMGEv1i16rz |
| 1521 | UINT64_C(2124466176), // FCMGEv1i32rz |
| 1522 | UINT64_C(2128660480), // FCMGEv1i64rz |
| 1523 | UINT64_C(773907456), // FCMGEv2f32 |
| 1524 | UINT64_C(1851843584), // FCMGEv2f64 |
| 1525 | UINT64_C(782288896), // FCMGEv2i32rz |
| 1526 | UINT64_C(1860225024), // FCMGEv2i64rz |
| 1527 | UINT64_C(775955456), // FCMGEv4f16 |
| 1528 | UINT64_C(1847649280), // FCMGEv4f32 |
| 1529 | UINT64_C(788056064), // FCMGEv4i16rz |
| 1530 | UINT64_C(1856030720), // FCMGEv4i32rz |
| 1531 | UINT64_C(1849697280), // FCMGEv8f16 |
| 1532 | UINT64_C(1861797888), // FCMGEv8i16rz |
| 1533 | UINT64_C(2126521344), // FCMGT16 |
| 1534 | UINT64_C(2124473344), // FCMGT32 |
| 1535 | UINT64_C(2128667648), // FCMGT64 |
| 1536 | UINT64_C(1708138512), // FCMGT_PPzZ0_D |
| 1537 | UINT64_C(1699749904), // FCMGT_PPzZ0_H |
| 1538 | UINT64_C(1703944208), // FCMGT_PPzZ0_S |
| 1539 | UINT64_C(1707098128), // FCMGT_PPzZZ_D |
| 1540 | UINT64_C(1698709520), // FCMGT_PPzZZ_H |
| 1541 | UINT64_C(1702903824), // FCMGT_PPzZZ_S |
| 1542 | UINT64_C(1593362432), // FCMGTv1i16rz |
| 1543 | UINT64_C(1587595264), // FCMGTv1i32rz |
| 1544 | UINT64_C(1591789568), // FCMGTv1i64rz |
| 1545 | UINT64_C(782296064), // FCMGTv2f32 |
| 1546 | UINT64_C(1860232192), // FCMGTv2f64 |
| 1547 | UINT64_C(245417984), // FCMGTv2i32rz |
| 1548 | UINT64_C(1323354112), // FCMGTv2i64rz |
| 1549 | UINT64_C(784344064), // FCMGTv4f16 |
| 1550 | UINT64_C(1856037888), // FCMGTv4f32 |
| 1551 | UINT64_C(251185152), // FCMGTv4i16rz |
| 1552 | UINT64_C(1319159808), // FCMGTv4i32rz |
| 1553 | UINT64_C(1858085888), // FCMGTv8f16 |
| 1554 | UINT64_C(1324926976), // FCMGTv8i16rz |
| 1555 | UINT64_C(1690304512), // FCMLA_ZPmZZ_D |
| 1556 | UINT64_C(1681915904), // FCMLA_ZPmZZ_H |
| 1557 | UINT64_C(1686110208), // FCMLA_ZPmZZ_S |
| 1558 | UINT64_C(1688211456), // FCMLA_ZZZI_H |
| 1559 | UINT64_C(1692405760), // FCMLA_ZZZI_S |
| 1560 | UINT64_C(780190720), // FCMLAv2f32 |
| 1561 | UINT64_C(1858126848), // FCMLAv2f64 |
| 1562 | UINT64_C(775996416), // FCMLAv4f16 |
| 1563 | UINT64_C(792727552), // FCMLAv4f16_indexed |
| 1564 | UINT64_C(1853932544), // FCMLAv4f32 |
| 1565 | UINT64_C(1870663680), // FCMLAv4f32_indexed |
| 1566 | UINT64_C(1849738240), // FCMLAv8f16 |
| 1567 | UINT64_C(1866469376), // FCMLAv8f16_indexed |
| 1568 | UINT64_C(1708204048), // FCMLE_PPzZ0_D |
| 1569 | UINT64_C(1699815440), // FCMLE_PPzZ0_H |
| 1570 | UINT64_C(1704009744), // FCMLE_PPzZ0_S |
| 1571 | UINT64_C(2130237440), // FCMLEv1i16rz |
| 1572 | UINT64_C(2124470272), // FCMLEv1i32rz |
| 1573 | UINT64_C(2128664576), // FCMLEv1i64rz |
| 1574 | UINT64_C(782292992), // FCMLEv2i32rz |
| 1575 | UINT64_C(1860229120), // FCMLEv2i64rz |
| 1576 | UINT64_C(788060160), // FCMLEv4i16rz |
| 1577 | UINT64_C(1856034816), // FCMLEv4i32rz |
| 1578 | UINT64_C(1861801984), // FCMLEv8i16rz |
| 1579 | UINT64_C(1708204032), // FCMLT_PPzZ0_D |
| 1580 | UINT64_C(1699815424), // FCMLT_PPzZ0_H |
| 1581 | UINT64_C(1704009728), // FCMLT_PPzZ0_S |
| 1582 | UINT64_C(1593370624), // FCMLTv1i16rz |
| 1583 | UINT64_C(1587603456), // FCMLTv1i32rz |
| 1584 | UINT64_C(1591797760), // FCMLTv1i64rz |
| 1585 | UINT64_C(245426176), // FCMLTv2i32rz |
| 1586 | UINT64_C(1323362304), // FCMLTv2i64rz |
| 1587 | UINT64_C(251193344), // FCMLTv4i16rz |
| 1588 | UINT64_C(1319168000), // FCMLTv4i32rz |
| 1589 | UINT64_C(1324935168), // FCMLTv8i16rz |
| 1590 | UINT64_C(1708335104), // FCMNE_PPzZ0_D |
| 1591 | UINT64_C(1699946496), // FCMNE_PPzZ0_H |
| 1592 | UINT64_C(1704140800), // FCMNE_PPzZ0_S |
| 1593 | UINT64_C(1707106320), // FCMNE_PPzZZ_D |
| 1594 | UINT64_C(1698717712), // FCMNE_PPzZZ_H |
| 1595 | UINT64_C(1702912016), // FCMNE_PPzZZ_S |
| 1596 | UINT64_C(509616136), // FCMPDri |
| 1597 | UINT64_C(509616128), // FCMPDrr |
| 1598 | UINT64_C(509616152), // FCMPEDri |
| 1599 | UINT64_C(509616144), // FCMPEDrr |
| 1600 | UINT64_C(518004760), // FCMPEHri |
| 1601 | UINT64_C(518004752), // FCMPEHrr |
| 1602 | UINT64_C(505421848), // FCMPESri |
| 1603 | UINT64_C(505421840), // FCMPESrr |
| 1604 | UINT64_C(518004744), // FCMPHri |
| 1605 | UINT64_C(518004736), // FCMPHrr |
| 1606 | UINT64_C(505421832), // FCMPSri |
| 1607 | UINT64_C(505421824), // FCMPSrr |
| 1608 | UINT64_C(1707130880), // FCMUO_PPzZZ_D |
| 1609 | UINT64_C(1698742272), // FCMUO_PPzZZ_H |
| 1610 | UINT64_C(1702936576), // FCMUO_PPzZZ_S |
| 1611 | UINT64_C(97566720), // FCPY_ZPmI_D |
| 1612 | UINT64_C(89178112), // FCPY_ZPmI_H |
| 1613 | UINT64_C(93372416), // FCPY_ZPmI_S |
| 1614 | UINT64_C(509611008), // FCSELDrrr |
| 1615 | UINT64_C(517999616), // FCSELHrrr |
| 1616 | UINT64_C(505416704), // FCSELSrrr |
| 1617 | UINT64_C(509870080), // FCVTASUWDr |
| 1618 | UINT64_C(518258688), // FCVTASUWHr |
| 1619 | UINT64_C(505675776), // FCVTASUWSr |
| 1620 | UINT64_C(2657353728), // FCVTASUXDr |
| 1621 | UINT64_C(2665742336), // FCVTASUXHr |
| 1622 | UINT64_C(2653159424), // FCVTASUXSr |
| 1623 | UINT64_C(1585039360), // FCVTASv1f16 |
| 1624 | UINT64_C(1579272192), // FCVTASv1i32 |
| 1625 | UINT64_C(1583466496), // FCVTASv1i64 |
| 1626 | UINT64_C(237094912), // FCVTASv2f32 |
| 1627 | UINT64_C(1315031040), // FCVTASv2f64 |
| 1628 | UINT64_C(242862080), // FCVTASv4f16 |
| 1629 | UINT64_C(1310836736), // FCVTASv4f32 |
| 1630 | UINT64_C(1316603904), // FCVTASv8f16 |
| 1631 | UINT64_C(509935616), // FCVTAUUWDr |
| 1632 | UINT64_C(518324224), // FCVTAUUWHr |
| 1633 | UINT64_C(505741312), // FCVTAUUWSr |
| 1634 | UINT64_C(2657419264), // FCVTAUUXDr |
| 1635 | UINT64_C(2665807872), // FCVTAUUXHr |
| 1636 | UINT64_C(2653224960), // FCVTAUUXSr |
| 1637 | UINT64_C(2121910272), // FCVTAUv1f16 |
| 1638 | UINT64_C(2116143104), // FCVTAUv1i32 |
| 1639 | UINT64_C(2120337408), // FCVTAUv1i64 |
| 1640 | UINT64_C(773965824), // FCVTAUv2f32 |
| 1641 | UINT64_C(1851901952), // FCVTAUv2f64 |
| 1642 | UINT64_C(779732992), // FCVTAUv4f16 |
| 1643 | UINT64_C(1847707648), // FCVTAUv4f32 |
| 1644 | UINT64_C(1853474816), // FCVTAUv8f16 |
| 1645 | UINT64_C(518176768), // FCVTDHr |
| 1646 | UINT64_C(505593856), // FCVTDSr |
| 1647 | UINT64_C(509853696), // FCVTHDr |
| 1648 | UINT64_C(505659392), // FCVTHSr |
| 1649 | UINT64_C(1686740992), // FCVTLT_ZPmZ_HtoS |
| 1650 | UINT64_C(1691066368), // FCVTLT_ZPmZ_StoD |
| 1651 | UINT64_C(241268736), // FCVTLv2i32 |
| 1652 | UINT64_C(237074432), // FCVTLv4i16 |
| 1653 | UINT64_C(1315010560), // FCVTLv4i32 |
| 1654 | UINT64_C(1310816256), // FCVTLv8i16 |
| 1655 | UINT64_C(510656512), // FCVTMSUWDr |
| 1656 | UINT64_C(519045120), // FCVTMSUWHr |
| 1657 | UINT64_C(506462208), // FCVTMSUWSr |
| 1658 | UINT64_C(2658140160), // FCVTMSUXDr |
| 1659 | UINT64_C(2666528768), // FCVTMSUXHr |
| 1660 | UINT64_C(2653945856), // FCVTMSUXSr |
| 1661 | UINT64_C(1585035264), // FCVTMSv1f16 |
| 1662 | UINT64_C(1579268096), // FCVTMSv1i32 |
| 1663 | UINT64_C(1583462400), // FCVTMSv1i64 |
| 1664 | UINT64_C(237090816), // FCVTMSv2f32 |
| 1665 | UINT64_C(1315026944), // FCVTMSv2f64 |
| 1666 | UINT64_C(242857984), // FCVTMSv4f16 |
| 1667 | UINT64_C(1310832640), // FCVTMSv4f32 |
| 1668 | UINT64_C(1316599808), // FCVTMSv8f16 |
| 1669 | UINT64_C(510722048), // FCVTMUUWDr |
| 1670 | UINT64_C(519110656), // FCVTMUUWHr |
| 1671 | UINT64_C(506527744), // FCVTMUUWSr |
| 1672 | UINT64_C(2658205696), // FCVTMUUXDr |
| 1673 | UINT64_C(2666594304), // FCVTMUUXHr |
| 1674 | UINT64_C(2654011392), // FCVTMUUXSr |
| 1675 | UINT64_C(2121906176), // FCVTMUv1f16 |
| 1676 | UINT64_C(2116139008), // FCVTMUv1i32 |
| 1677 | UINT64_C(2120333312), // FCVTMUv1i64 |
| 1678 | UINT64_C(773961728), // FCVTMUv2f32 |
| 1679 | UINT64_C(1851897856), // FCVTMUv2f64 |
| 1680 | UINT64_C(779728896), // FCVTMUv4f16 |
| 1681 | UINT64_C(1847703552), // FCVTMUv4f32 |
| 1682 | UINT64_C(1853470720), // FCVTMUv8f16 |
| 1683 | UINT64_C(509607936), // FCVTNSUWDr |
| 1684 | UINT64_C(517996544), // FCVTNSUWHr |
| 1685 | UINT64_C(505413632), // FCVTNSUWSr |
| 1686 | UINT64_C(2657091584), // FCVTNSUXDr |
| 1687 | UINT64_C(2665480192), // FCVTNSUXHr |
| 1688 | UINT64_C(2652897280), // FCVTNSUXSr |
| 1689 | UINT64_C(1585031168), // FCVTNSv1f16 |
| 1690 | UINT64_C(1579264000), // FCVTNSv1i32 |
| 1691 | UINT64_C(1583458304), // FCVTNSv1i64 |
| 1692 | UINT64_C(237086720), // FCVTNSv2f32 |
| 1693 | UINT64_C(1315022848), // FCVTNSv2f64 |
| 1694 | UINT64_C(242853888), // FCVTNSv4f16 |
| 1695 | UINT64_C(1310828544), // FCVTNSv4f32 |
| 1696 | UINT64_C(1316595712), // FCVTNSv8f16 |
| 1697 | UINT64_C(1691000832), // FCVTNT_ZPmZ_DtoS |
| 1698 | UINT64_C(1686675456), // FCVTNT_ZPmZ_StoH |
| 1699 | UINT64_C(509673472), // FCVTNUUWDr |
| 1700 | UINT64_C(518062080), // FCVTNUUWHr |
| 1701 | UINT64_C(505479168), // FCVTNUUWSr |
| 1702 | UINT64_C(2657157120), // FCVTNUUXDr |
| 1703 | UINT64_C(2665545728), // FCVTNUUXHr |
| 1704 | UINT64_C(2652962816), // FCVTNUUXSr |
| 1705 | UINT64_C(2121902080), // FCVTNUv1f16 |
| 1706 | UINT64_C(2116134912), // FCVTNUv1i32 |
| 1707 | UINT64_C(2120329216), // FCVTNUv1i64 |
| 1708 | UINT64_C(773957632), // FCVTNUv2f32 |
| 1709 | UINT64_C(1851893760), // FCVTNUv2f64 |
| 1710 | UINT64_C(779724800), // FCVTNUv4f16 |
| 1711 | UINT64_C(1847699456), // FCVTNUv4f32 |
| 1712 | UINT64_C(1853466624), // FCVTNUv8f16 |
| 1713 | UINT64_C(241264640), // FCVTNv2i32 |
| 1714 | UINT64_C(237070336), // FCVTNv4i16 |
| 1715 | UINT64_C(1315006464), // FCVTNv4i32 |
| 1716 | UINT64_C(1310812160), // FCVTNv8i16 |
| 1717 | UINT64_C(510132224), // FCVTPSUWDr |
| 1718 | UINT64_C(518520832), // FCVTPSUWHr |
| 1719 | UINT64_C(505937920), // FCVTPSUWSr |
| 1720 | UINT64_C(2657615872), // FCVTPSUXDr |
| 1721 | UINT64_C(2666004480), // FCVTPSUXHr |
| 1722 | UINT64_C(2653421568), // FCVTPSUXSr |
| 1723 | UINT64_C(1593419776), // FCVTPSv1f16 |
| 1724 | UINT64_C(1587652608), // FCVTPSv1i32 |
| 1725 | UINT64_C(1591846912), // FCVTPSv1i64 |
| 1726 | UINT64_C(245475328), // FCVTPSv2f32 |
| 1727 | UINT64_C(1323411456), // FCVTPSv2f64 |
| 1728 | UINT64_C(251242496), // FCVTPSv4f16 |
| 1729 | UINT64_C(1319217152), // FCVTPSv4f32 |
| 1730 | UINT64_C(1324984320), // FCVTPSv8f16 |
| 1731 | UINT64_C(510197760), // FCVTPUUWDr |
| 1732 | UINT64_C(518586368), // FCVTPUUWHr |
| 1733 | UINT64_C(506003456), // FCVTPUUWSr |
| 1734 | UINT64_C(2657681408), // FCVTPUUXDr |
| 1735 | UINT64_C(2666070016), // FCVTPUUXHr |
| 1736 | UINT64_C(2653487104), // FCVTPUUXSr |
| 1737 | UINT64_C(2130290688), // FCVTPUv1f16 |
| 1738 | UINT64_C(2124523520), // FCVTPUv1i32 |
| 1739 | UINT64_C(2128717824), // FCVTPUv1i64 |
| 1740 | UINT64_C(782346240), // FCVTPUv2f32 |
| 1741 | UINT64_C(1860282368), // FCVTPUv2f64 |
| 1742 | UINT64_C(788113408), // FCVTPUv4f16 |
| 1743 | UINT64_C(1856088064), // FCVTPUv4f32 |
| 1744 | UINT64_C(1861855232), // FCVTPUv8f16 |
| 1745 | UINT64_C(509755392), // FCVTSDr |
| 1746 | UINT64_C(518144000), // FCVTSHr |
| 1747 | UINT64_C(1678417920), // FCVTXNT_ZPmZ_DtoS |
| 1748 | UINT64_C(2120312832), // FCVTXNv1i64 |
| 1749 | UINT64_C(778135552), // FCVTXNv2f32 |
| 1750 | UINT64_C(1851877376), // FCVTXNv4f32 |
| 1751 | UINT64_C(1695195136), // FCVTX_ZPmZ_DtoS |
| 1752 | UINT64_C(509116416), // FCVTZSSWDri |
| 1753 | UINT64_C(517505024), // FCVTZSSWHri |
| 1754 | UINT64_C(504922112), // FCVTZSSWSri |
| 1755 | UINT64_C(2656567296), // FCVTZSSXDri |
| 1756 | UINT64_C(2664955904), // FCVTZSSXHri |
| 1757 | UINT64_C(2652372992), // FCVTZSSXSri |
| 1758 | UINT64_C(511180800), // FCVTZSUWDr |
| 1759 | UINT64_C(519569408), // FCVTZSUWHr |
| 1760 | UINT64_C(506986496), // FCVTZSUWSr |
| 1761 | UINT64_C(2658664448), // FCVTZSUXDr |
| 1762 | UINT64_C(2667053056), // FCVTZSUXHr |
| 1763 | UINT64_C(2654470144), // FCVTZSUXSr |
| 1764 | UINT64_C(1709088768), // FCVTZS_ZPmZ_DtoD |
| 1765 | UINT64_C(1708695552), // FCVTZS_ZPmZ_DtoS |
| 1766 | UINT64_C(1700700160), // FCVTZS_ZPmZ_HtoD |
| 1767 | UINT64_C(1700438016), // FCVTZS_ZPmZ_HtoH |
| 1768 | UINT64_C(1700569088), // FCVTZS_ZPmZ_HtoS |
| 1769 | UINT64_C(1708957696), // FCVTZS_ZPmZ_StoD |
| 1770 | UINT64_C(1704763392), // FCVTZS_ZPmZ_StoS |
| 1771 | UINT64_C(1598094336), // FCVTZSd |
| 1772 | UINT64_C(1594948608), // FCVTZSh |
| 1773 | UINT64_C(1595997184), // FCVTZSs |
| 1774 | UINT64_C(1593423872), // FCVTZSv1f16 |
| 1775 | UINT64_C(1587656704), // FCVTZSv1i32 |
| 1776 | UINT64_C(1591851008), // FCVTZSv1i64 |
| 1777 | UINT64_C(245479424), // FCVTZSv2f32 |
| 1778 | UINT64_C(1323415552), // FCVTZSv2f64 |
| 1779 | UINT64_C(253819904), // FCVTZSv2i32_shift |
| 1780 | UINT64_C(1329658880), // FCVTZSv2i64_shift |
| 1781 | UINT64_C(251246592), // FCVTZSv4f16 |
| 1782 | UINT64_C(1319221248), // FCVTZSv4f32 |
| 1783 | UINT64_C(252771328), // FCVTZSv4i16_shift |
| 1784 | UINT64_C(1327561728), // FCVTZSv4i32_shift |
| 1785 | UINT64_C(1324988416), // FCVTZSv8f16 |
| 1786 | UINT64_C(1326513152), // FCVTZSv8i16_shift |
| 1787 | UINT64_C(509181952), // FCVTZUSWDri |
| 1788 | UINT64_C(517570560), // FCVTZUSWHri |
| 1789 | UINT64_C(504987648), // FCVTZUSWSri |
| 1790 | UINT64_C(2656632832), // FCVTZUSXDri |
| 1791 | UINT64_C(2665021440), // FCVTZUSXHri |
| 1792 | UINT64_C(2652438528), // FCVTZUSXSri |
| 1793 | UINT64_C(511246336), // FCVTZUUWDr |
| 1794 | UINT64_C(519634944), // FCVTZUUWHr |
| 1795 | UINT64_C(507052032), // FCVTZUUWSr |
| 1796 | UINT64_C(2658729984), // FCVTZUUXDr |
| 1797 | UINT64_C(2667118592), // FCVTZUUXHr |
| 1798 | UINT64_C(2654535680), // FCVTZUUXSr |
| 1799 | UINT64_C(1709154304), // FCVTZU_ZPmZ_DtoD |
| 1800 | UINT64_C(1708761088), // FCVTZU_ZPmZ_DtoS |
| 1801 | UINT64_C(1700765696), // FCVTZU_ZPmZ_HtoD |
| 1802 | UINT64_C(1700503552), // FCVTZU_ZPmZ_HtoH |
| 1803 | UINT64_C(1700634624), // FCVTZU_ZPmZ_HtoS |
| 1804 | UINT64_C(1709023232), // FCVTZU_ZPmZ_StoD |
| 1805 | UINT64_C(1704828928), // FCVTZU_ZPmZ_StoS |
| 1806 | UINT64_C(2134965248), // FCVTZUd |
| 1807 | UINT64_C(2131819520), // FCVTZUh |
| 1808 | UINT64_C(2132868096), // FCVTZUs |
| 1809 | UINT64_C(2130294784), // FCVTZUv1f16 |
| 1810 | UINT64_C(2124527616), // FCVTZUv1i32 |
| 1811 | UINT64_C(2128721920), // FCVTZUv1i64 |
| 1812 | UINT64_C(782350336), // FCVTZUv2f32 |
| 1813 | UINT64_C(1860286464), // FCVTZUv2f64 |
| 1814 | UINT64_C(790690816), // FCVTZUv2i32_shift |
| 1815 | UINT64_C(1866529792), // FCVTZUv2i64_shift |
| 1816 | UINT64_C(788117504), // FCVTZUv4f16 |
| 1817 | UINT64_C(1856092160), // FCVTZUv4f32 |
| 1818 | UINT64_C(789642240), // FCVTZUv4i16_shift |
| 1819 | UINT64_C(1864432640), // FCVTZUv4i32_shift |
| 1820 | UINT64_C(1861859328), // FCVTZUv8f16 |
| 1821 | UINT64_C(1863384064), // FCVTZUv8i16_shift |
| 1822 | UINT64_C(1707646976), // FCVT_ZPmZ_DtoH |
| 1823 | UINT64_C(1707778048), // FCVT_ZPmZ_DtoS |
| 1824 | UINT64_C(1707712512), // FCVT_ZPmZ_HtoD |
| 1825 | UINT64_C(1703518208), // FCVT_ZPmZ_HtoS |
| 1826 | UINT64_C(1707843584), // FCVT_ZPmZ_StoD |
| 1827 | UINT64_C(1703452672), // FCVT_ZPmZ_StoH |
| 1828 | UINT64_C(509614080), // FDIVDrr |
| 1829 | UINT64_C(518002688), // FDIVHrr |
| 1830 | UINT64_C(1707900928), // FDIVR_ZPmZ_D |
| 1831 | UINT64_C(1699512320), // FDIVR_ZPmZ_H |
| 1832 | UINT64_C(1703706624), // FDIVR_ZPmZ_S |
| 1833 | UINT64_C(505419776), // FDIVSrr |
| 1834 | UINT64_C(1707966464), // FDIV_ZPmZ_D |
| 1835 | UINT64_C(1699577856), // FDIV_ZPmZ_H |
| 1836 | UINT64_C(1703772160), // FDIV_ZPmZ_S |
| 1837 | UINT64_C(773913600), // FDIVv2f32 |
| 1838 | UINT64_C(1851849728), // FDIVv2f64 |
| 1839 | UINT64_C(775961600), // FDIVv4f16 |
| 1840 | UINT64_C(1847655424), // FDIVv4f32 |
| 1841 | UINT64_C(1849703424), // FDIVv8f16 |
| 1842 | UINT64_C(637124608), // FDUP_ZI_D |
| 1843 | UINT64_C(628736000), // FDUP_ZI_H |
| 1844 | UINT64_C(632930304), // FDUP_ZI_S |
| 1845 | UINT64_C(81836032), // FEXPA_ZZ_D |
| 1846 | UINT64_C(73447424), // FEXPA_ZZ_H |
| 1847 | UINT64_C(77641728), // FEXPA_ZZ_S |
| 1848 | UINT64_C(511574016), // FJCVTZS |
| 1849 | UINT64_C(1696505856), // FLOGB_ZPmZ_D |
| 1850 | UINT64_C(1696243712), // FLOGB_ZPmZ_H |
| 1851 | UINT64_C(1696374784), // FLOGB_ZPmZ_S |
| 1852 | UINT64_C(524288000), // FMADDDrrr |
| 1853 | UINT64_C(532676608), // FMADDHrrr |
| 1854 | UINT64_C(520093696), // FMADDSrrr |
| 1855 | UINT64_C(1709211648), // FMAD_ZPmZZ_D |
| 1856 | UINT64_C(1700823040), // FMAD_ZPmZZ_H |
| 1857 | UINT64_C(1705017344), // FMAD_ZPmZZ_S |
| 1858 | UINT64_C(509626368), // FMAXDrr |
| 1859 | UINT64_C(518014976), // FMAXHrr |
| 1860 | UINT64_C(509634560), // FMAXNMDrr |
| 1861 | UINT64_C(518023168), // FMAXNMHrr |
| 1862 | UINT64_C(1691648000), // FMAXNMP_ZPmZZ_D |
| 1863 | UINT64_C(1683259392), // FMAXNMP_ZPmZZ_H |
| 1864 | UINT64_C(1687453696), // FMAXNMP_ZPmZZ_S |
| 1865 | UINT64_C(773899264), // FMAXNMPv2f32 |
| 1866 | UINT64_C(1851835392), // FMAXNMPv2f64 |
| 1867 | UINT64_C(1580255232), // FMAXNMPv2i16p |
| 1868 | UINT64_C(2117126144), // FMAXNMPv2i32p |
| 1869 | UINT64_C(2121320448), // FMAXNMPv2i64p |
| 1870 | UINT64_C(775947264), // FMAXNMPv4f16 |
| 1871 | UINT64_C(1847641088), // FMAXNMPv4f32 |
| 1872 | UINT64_C(1849689088), // FMAXNMPv8f16 |
| 1873 | UINT64_C(505440256), // FMAXNMSrr |
| 1874 | UINT64_C(1707352064), // FMAXNMV_VPZ_D |
| 1875 | UINT64_C(1698963456), // FMAXNMV_VPZ_H |
| 1876 | UINT64_C(1703157760), // FMAXNMV_VPZ_S |
| 1877 | UINT64_C(238077952), // FMAXNMVv4i16v |
| 1878 | UINT64_C(1848690688), // FMAXNMVv4i32v |
| 1879 | UINT64_C(1311819776), // FMAXNMVv8i16v |
| 1880 | UINT64_C(1708949504), // FMAXNM_ZPmI_D |
| 1881 | UINT64_C(1700560896), // FMAXNM_ZPmI_H |
| 1882 | UINT64_C(1704755200), // FMAXNM_ZPmI_S |
| 1883 | UINT64_C(1707376640), // FMAXNM_ZPmZ_D |
| 1884 | UINT64_C(1698988032), // FMAXNM_ZPmZ_H |
| 1885 | UINT64_C(1703182336), // FMAXNM_ZPmZ_S |
| 1886 | UINT64_C(237028352), // FMAXNMv2f32 |
| 1887 | UINT64_C(1314964480), // FMAXNMv2f64 |
| 1888 | UINT64_C(239076352), // FMAXNMv4f16 |
| 1889 | UINT64_C(1310770176), // FMAXNMv4f32 |
| 1890 | UINT64_C(1312818176), // FMAXNMv8f16 |
| 1891 | UINT64_C(1691779072), // FMAXP_ZPmZZ_D |
| 1892 | UINT64_C(1683390464), // FMAXP_ZPmZZ_H |
| 1893 | UINT64_C(1687584768), // FMAXP_ZPmZZ_S |
| 1894 | UINT64_C(773911552), // FMAXPv2f32 |
| 1895 | UINT64_C(1851847680), // FMAXPv2f64 |
| 1896 | UINT64_C(1580267520), // FMAXPv2i16p |
| 1897 | UINT64_C(2117138432), // FMAXPv2i32p |
| 1898 | UINT64_C(2121332736), // FMAXPv2i64p |
| 1899 | UINT64_C(775959552), // FMAXPv4f16 |
| 1900 | UINT64_C(1847653376), // FMAXPv4f32 |
| 1901 | UINT64_C(1849701376), // FMAXPv8f16 |
| 1902 | UINT64_C(505432064), // FMAXSrr |
| 1903 | UINT64_C(1707483136), // FMAXV_VPZ_D |
| 1904 | UINT64_C(1699094528), // FMAXV_VPZ_H |
| 1905 | UINT64_C(1703288832), // FMAXV_VPZ_S |
| 1906 | UINT64_C(238090240), // FMAXVv4i16v |
| 1907 | UINT64_C(1848702976), // FMAXVv4i32v |
| 1908 | UINT64_C(1311832064), // FMAXVv8i16v |
| 1909 | UINT64_C(1709080576), // FMAX_ZPmI_D |
| 1910 | UINT64_C(1700691968), // FMAX_ZPmI_H |
| 1911 | UINT64_C(1704886272), // FMAX_ZPmI_S |
| 1912 | UINT64_C(1707507712), // FMAX_ZPmZ_D |
| 1913 | UINT64_C(1699119104), // FMAX_ZPmZ_H |
| 1914 | UINT64_C(1703313408), // FMAX_ZPmZ_S |
| 1915 | UINT64_C(237040640), // FMAXv2f32 |
| 1916 | UINT64_C(1314976768), // FMAXv2f64 |
| 1917 | UINT64_C(239088640), // FMAXv4f16 |
| 1918 | UINT64_C(1310782464), // FMAXv4f32 |
| 1919 | UINT64_C(1312830464), // FMAXv8f16 |
| 1920 | UINT64_C(509630464), // FMINDrr |
| 1921 | UINT64_C(518019072), // FMINHrr |
| 1922 | UINT64_C(509638656), // FMINNMDrr |
| 1923 | UINT64_C(518027264), // FMINNMHrr |
| 1924 | UINT64_C(1691713536), // FMINNMP_ZPmZZ_D |
| 1925 | UINT64_C(1683324928), // FMINNMP_ZPmZZ_H |
| 1926 | UINT64_C(1687519232), // FMINNMP_ZPmZZ_S |
| 1927 | UINT64_C(782287872), // FMINNMPv2f32 |
| 1928 | UINT64_C(1860224000), // FMINNMPv2f64 |
| 1929 | UINT64_C(1588643840), // FMINNMPv2i16p |
| 1930 | UINT64_C(2125514752), // FMINNMPv2i32p |
| 1931 | UINT64_C(2129709056), // FMINNMPv2i64p |
| 1932 | UINT64_C(784335872), // FMINNMPv4f16 |
| 1933 | UINT64_C(1856029696), // FMINNMPv4f32 |
| 1934 | UINT64_C(1858077696), // FMINNMPv8f16 |
| 1935 | UINT64_C(505444352), // FMINNMSrr |
| 1936 | UINT64_C(1707417600), // FMINNMV_VPZ_D |
| 1937 | UINT64_C(1699028992), // FMINNMV_VPZ_H |
| 1938 | UINT64_C(1703223296), // FMINNMV_VPZ_S |
| 1939 | UINT64_C(246466560), // FMINNMVv4i16v |
| 1940 | UINT64_C(1857079296), // FMINNMVv4i32v |
| 1941 | UINT64_C(1320208384), // FMINNMVv8i16v |
| 1942 | UINT64_C(1709015040), // FMINNM_ZPmI_D |
| 1943 | UINT64_C(1700626432), // FMINNM_ZPmI_H |
| 1944 | UINT64_C(1704820736), // FMINNM_ZPmI_S |
| 1945 | UINT64_C(1707442176), // FMINNM_ZPmZ_D |
| 1946 | UINT64_C(1699053568), // FMINNM_ZPmZ_H |
| 1947 | UINT64_C(1703247872), // FMINNM_ZPmZ_S |
| 1948 | UINT64_C(245416960), // FMINNMv2f32 |
| 1949 | UINT64_C(1323353088), // FMINNMv2f64 |
| 1950 | UINT64_C(247464960), // FMINNMv4f16 |
| 1951 | UINT64_C(1319158784), // FMINNMv4f32 |
| 1952 | UINT64_C(1321206784), // FMINNMv8f16 |
| 1953 | UINT64_C(1691844608), // FMINP_ZPmZZ_D |
| 1954 | UINT64_C(1683456000), // FMINP_ZPmZZ_H |
| 1955 | UINT64_C(1687650304), // FMINP_ZPmZZ_S |
| 1956 | UINT64_C(782300160), // FMINPv2f32 |
| 1957 | UINT64_C(1860236288), // FMINPv2f64 |
| 1958 | UINT64_C(1588656128), // FMINPv2i16p |
| 1959 | UINT64_C(2125527040), // FMINPv2i32p |
| 1960 | UINT64_C(2129721344), // FMINPv2i64p |
| 1961 | UINT64_C(784348160), // FMINPv4f16 |
| 1962 | UINT64_C(1856041984), // FMINPv4f32 |
| 1963 | UINT64_C(1858089984), // FMINPv8f16 |
| 1964 | UINT64_C(505436160), // FMINSrr |
| 1965 | UINT64_C(1707548672), // FMINV_VPZ_D |
| 1966 | UINT64_C(1699160064), // FMINV_VPZ_H |
| 1967 | UINT64_C(1703354368), // FMINV_VPZ_S |
| 1968 | UINT64_C(246478848), // FMINVv4i16v |
| 1969 | UINT64_C(1857091584), // FMINVv4i32v |
| 1970 | UINT64_C(1320220672), // FMINVv8i16v |
| 1971 | UINT64_C(1709146112), // FMIN_ZPmI_D |
| 1972 | UINT64_C(1700757504), // FMIN_ZPmI_H |
| 1973 | UINT64_C(1704951808), // FMIN_ZPmI_S |
| 1974 | UINT64_C(1707573248), // FMIN_ZPmZ_D |
| 1975 | UINT64_C(1699184640), // FMIN_ZPmZ_H |
| 1976 | UINT64_C(1703378944), // FMIN_ZPmZ_S |
| 1977 | UINT64_C(245429248), // FMINv2f32 |
| 1978 | UINT64_C(1323365376), // FMINv2f64 |
| 1979 | UINT64_C(247477248), // FMINv4f16 |
| 1980 | UINT64_C(1319171072), // FMINv4f32 |
| 1981 | UINT64_C(1321219072), // FMINv8f16 |
| 1982 | UINT64_C(796950528), // FMLAL2lanev4f16 |
| 1983 | UINT64_C(1870692352), // FMLAL2lanev8f16 |
| 1984 | UINT64_C(773901312), // FMLAL2v4f16 |
| 1985 | UINT64_C(1847643136), // FMLAL2v8f16 |
| 1986 | UINT64_C(1688223744), // FMLALB_ZZZI_SHH |
| 1987 | UINT64_C(1688240128), // FMLALB_ZZZ_SHH |
| 1988 | UINT64_C(1688224768), // FMLALT_ZZZI_SHH |
| 1989 | UINT64_C(1688241152), // FMLALT_ZZZ_SHH |
| 1990 | UINT64_C(260046848), // FMLALlanev4f16 |
| 1991 | UINT64_C(1333788672), // FMLALlanev8f16 |
| 1992 | UINT64_C(237038592), // FMLALv4f16 |
| 1993 | UINT64_C(1310780416), // FMLALv8f16 |
| 1994 | UINT64_C(1709178880), // FMLA_ZPmZZ_D |
| 1995 | UINT64_C(1700790272), // FMLA_ZPmZZ_H |
| 1996 | UINT64_C(1704984576), // FMLA_ZPmZZ_S |
| 1997 | UINT64_C(1692401664), // FMLA_ZZZI_D |
| 1998 | UINT64_C(1679818752), // FMLA_ZZZI_H |
| 1999 | UINT64_C(1688207360), // FMLA_ZZZI_S |
| 2000 | UINT64_C(1593839616), // FMLAv1i16_indexed |
| 2001 | UINT64_C(1602228224), // FMLAv1i32_indexed |
| 2002 | UINT64_C(1606422528), // FMLAv1i64_indexed |
| 2003 | UINT64_C(237030400), // FMLAv2f32 |
| 2004 | UINT64_C(1314966528), // FMLAv2f64 |
| 2005 | UINT64_C(260050944), // FMLAv2i32_indexed |
| 2006 | UINT64_C(1337987072), // FMLAv2i64_indexed |
| 2007 | UINT64_C(239078400), // FMLAv4f16 |
| 2008 | UINT64_C(1310772224), // FMLAv4f32 |
| 2009 | UINT64_C(251662336), // FMLAv4i16_indexed |
| 2010 | UINT64_C(1333792768), // FMLAv4i32_indexed |
| 2011 | UINT64_C(1312820224), // FMLAv8f16 |
| 2012 | UINT64_C(1325404160), // FMLAv8i16_indexed |
| 2013 | UINT64_C(796966912), // FMLSL2lanev4f16 |
| 2014 | UINT64_C(1870708736), // FMLSL2lanev8f16 |
| 2015 | UINT64_C(782289920), // FMLSL2v4f16 |
| 2016 | UINT64_C(1856031744), // FMLSL2v8f16 |
| 2017 | UINT64_C(1688231936), // FMLSLB_ZZZI_SHH |
| 2018 | UINT64_C(1688248320), // FMLSLB_ZZZ_SHH |
| 2019 | UINT64_C(1688232960), // FMLSLT_ZZZI_SHH |
| 2020 | UINT64_C(1688249344), // FMLSLT_ZZZ_SHH |
| 2021 | UINT64_C(260063232), // FMLSLlanev4f16 |
| 2022 | UINT64_C(1333805056), // FMLSLlanev8f16 |
| 2023 | UINT64_C(245427200), // FMLSLv4f16 |
| 2024 | UINT64_C(1319169024), // FMLSLv8f16 |
| 2025 | UINT64_C(1709187072), // FMLS_ZPmZZ_D |
| 2026 | UINT64_C(1700798464), // FMLS_ZPmZZ_H |
| 2027 | UINT64_C(1704992768), // FMLS_ZPmZZ_S |
| 2028 | UINT64_C(1692402688), // FMLS_ZZZI_D |
| 2029 | UINT64_C(1679819776), // FMLS_ZZZI_H |
| 2030 | UINT64_C(1688208384), // FMLS_ZZZI_S |
| 2031 | UINT64_C(1593856000), // FMLSv1i16_indexed |
| 2032 | UINT64_C(1602244608), // FMLSv1i32_indexed |
| 2033 | UINT64_C(1606438912), // FMLSv1i64_indexed |
| 2034 | UINT64_C(245419008), // FMLSv2f32 |
| 2035 | UINT64_C(1323355136), // FMLSv2f64 |
| 2036 | UINT64_C(260067328), // FMLSv2i32_indexed |
| 2037 | UINT64_C(1338003456), // FMLSv2i64_indexed |
| 2038 | UINT64_C(247467008), // FMLSv4f16 |
| 2039 | UINT64_C(1319160832), // FMLSv4f32 |
| 2040 | UINT64_C(251678720), // FMLSv4i16_indexed |
| 2041 | UINT64_C(1333809152), // FMLSv4i32_indexed |
| 2042 | UINT64_C(1321208832), // FMLSv8f16 |
| 2043 | UINT64_C(1325420544), // FMLSv8i16_indexed |
| 2044 | UINT64_C(1692460032), // FMMLA_ZZZ_D |
| 2045 | UINT64_C(1688265728), // FMMLA_ZZZ_S |
| 2046 | UINT64_C(2662203392), // FMOVDXHighr |
| 2047 | UINT64_C(2657484800), // FMOVDXr |
| 2048 | UINT64_C(509612032), // FMOVDi |
| 2049 | UINT64_C(509624320), // FMOVDr |
| 2050 | UINT64_C(518389760), // FMOVHWr |
| 2051 | UINT64_C(2665873408), // FMOVHXr |
| 2052 | UINT64_C(518000640), // FMOVHi |
| 2053 | UINT64_C(518012928), // FMOVHr |
| 2054 | UINT64_C(505806848), // FMOVSWr |
| 2055 | UINT64_C(505417728), // FMOVSi |
| 2056 | UINT64_C(505430016), // FMOVSr |
| 2057 | UINT64_C(518455296), // FMOVWHr |
| 2058 | UINT64_C(505872384), // FMOVWSr |
| 2059 | UINT64_C(2662268928), // FMOVXDHighr |
| 2060 | UINT64_C(2657550336), // FMOVXDr |
| 2061 | UINT64_C(2665938944), // FMOVXHr |
| 2062 | UINT64_C(251720704), // FMOVv2f32_ns |
| 2063 | UINT64_C(1862333440), // FMOVv2f64_ns |
| 2064 | UINT64_C(251722752), // FMOVv4f16_ns |
| 2065 | UINT64_C(1325462528), // FMOVv4f32_ns |
| 2066 | UINT64_C(1325464576), // FMOVv8f16_ns |
| 2067 | UINT64_C(1709219840), // FMSB_ZPmZZ_D |
| 2068 | UINT64_C(1700831232), // FMSB_ZPmZZ_H |
| 2069 | UINT64_C(1705025536), // FMSB_ZPmZZ_S |
| 2070 | UINT64_C(524320768), // FMSUBDrrr |
| 2071 | UINT64_C(532709376), // FMSUBHrrr |
| 2072 | UINT64_C(520126464), // FMSUBSrrr |
| 2073 | UINT64_C(509609984), // FMULDrr |
| 2074 | UINT64_C(517998592), // FMULHrr |
| 2075 | UINT64_C(505415680), // FMULSrr |
| 2076 | UINT64_C(1581259776), // FMULX16 |
| 2077 | UINT64_C(1579211776), // FMULX32 |
| 2078 | UINT64_C(1583406080), // FMULX64 |
| 2079 | UINT64_C(1707769856), // FMULX_ZPmZ_D |
| 2080 | UINT64_C(1699381248), // FMULX_ZPmZ_H |
| 2081 | UINT64_C(1703575552), // FMULX_ZPmZ_S |
| 2082 | UINT64_C(2130743296), // FMULXv1i16_indexed |
| 2083 | UINT64_C(2139131904), // FMULXv1i32_indexed |
| 2084 | UINT64_C(2143326208), // FMULXv1i64_indexed |
| 2085 | UINT64_C(237034496), // FMULXv2f32 |
| 2086 | UINT64_C(1314970624), // FMULXv2f64 |
| 2087 | UINT64_C(796954624), // FMULXv2i32_indexed |
| 2088 | UINT64_C(1874890752), // FMULXv2i64_indexed |
| 2089 | UINT64_C(239082496), // FMULXv4f16 |
| 2090 | UINT64_C(1310776320), // FMULXv4f32 |
| 2091 | UINT64_C(788566016), // FMULXv4i16_indexed |
| 2092 | UINT64_C(1870696448), // FMULXv4i32_indexed |
| 2093 | UINT64_C(1312824320), // FMULXv8f16 |
| 2094 | UINT64_C(1862307840), // FMULXv8i16_indexed |
| 2095 | UINT64_C(1708818432), // FMUL_ZPmI_D |
| 2096 | UINT64_C(1700429824), // FMUL_ZPmI_H |
| 2097 | UINT64_C(1704624128), // FMUL_ZPmI_S |
| 2098 | UINT64_C(1707245568), // FMUL_ZPmZ_D |
| 2099 | UINT64_C(1698856960), // FMUL_ZPmZ_H |
| 2100 | UINT64_C(1703051264), // FMUL_ZPmZ_S |
| 2101 | UINT64_C(1692409856), // FMUL_ZZZI_D |
| 2102 | UINT64_C(1679826944), // FMUL_ZZZI_H |
| 2103 | UINT64_C(1688215552), // FMUL_ZZZI_S |
| 2104 | UINT64_C(1707083776), // FMUL_ZZZ_D |
| 2105 | UINT64_C(1698695168), // FMUL_ZZZ_H |
| 2106 | UINT64_C(1702889472), // FMUL_ZZZ_S |
| 2107 | UINT64_C(1593872384), // FMULv1i16_indexed |
| 2108 | UINT64_C(1602260992), // FMULv1i32_indexed |
| 2109 | UINT64_C(1606455296), // FMULv1i64_indexed |
| 2110 | UINT64_C(773905408), // FMULv2f32 |
| 2111 | UINT64_C(1851841536), // FMULv2f64 |
| 2112 | UINT64_C(260083712), // FMULv2i32_indexed |
| 2113 | UINT64_C(1338019840), // FMULv2i64_indexed |
| 2114 | UINT64_C(775953408), // FMULv4f16 |
| 2115 | UINT64_C(1847647232), // FMULv4f32 |
| 2116 | UINT64_C(251695104), // FMULv4i16_indexed |
| 2117 | UINT64_C(1333825536), // FMULv4i32_indexed |
| 2118 | UINT64_C(1849695232), // FMULv8f16 |
| 2119 | UINT64_C(1325436928), // FMULv8i16_indexed |
| 2120 | UINT64_C(509689856), // FNEGDr |
| 2121 | UINT64_C(518078464), // FNEGHr |
| 2122 | UINT64_C(505495552), // FNEGSr |
| 2123 | UINT64_C(81633280), // FNEG_ZPmZ_D |
| 2124 | UINT64_C(73244672), // FNEG_ZPmZ_H |
| 2125 | UINT64_C(77438976), // FNEG_ZPmZ_S |
| 2126 | UINT64_C(782301184), // FNEGv2f32 |
| 2127 | UINT64_C(1860237312), // FNEGv2f64 |
| 2128 | UINT64_C(788068352), // FNEGv4f16 |
| 2129 | UINT64_C(1856043008), // FNEGv4f32 |
| 2130 | UINT64_C(1861810176), // FNEGv8f16 |
| 2131 | UINT64_C(526385152), // FNMADDDrrr |
| 2132 | UINT64_C(534773760), // FNMADDHrrr |
| 2133 | UINT64_C(522190848), // FNMADDSrrr |
| 2134 | UINT64_C(1709228032), // FNMAD_ZPmZZ_D |
| 2135 | UINT64_C(1700839424), // FNMAD_ZPmZZ_H |
| 2136 | UINT64_C(1705033728), // FNMAD_ZPmZZ_S |
| 2137 | UINT64_C(1709195264), // FNMLA_ZPmZZ_D |
| 2138 | UINT64_C(1700806656), // FNMLA_ZPmZZ_H |
| 2139 | UINT64_C(1705000960), // FNMLA_ZPmZZ_S |
| 2140 | UINT64_C(1709203456), // FNMLS_ZPmZZ_D |
| 2141 | UINT64_C(1700814848), // FNMLS_ZPmZZ_H |
| 2142 | UINT64_C(1705009152), // FNMLS_ZPmZZ_S |
| 2143 | UINT64_C(1709236224), // FNMSB_ZPmZZ_D |
| 2144 | UINT64_C(1700847616), // FNMSB_ZPmZZ_H |
| 2145 | UINT64_C(1705041920), // FNMSB_ZPmZZ_S |
| 2146 | UINT64_C(526417920), // FNMSUBDrrr |
| 2147 | UINT64_C(534806528), // FNMSUBHrrr |
| 2148 | UINT64_C(522223616), // FNMSUBSrrr |
| 2149 | UINT64_C(509642752), // FNMULDrr |
| 2150 | UINT64_C(518031360), // FNMULHrr |
| 2151 | UINT64_C(505448448), // FNMULSrr |
| 2152 | UINT64_C(1708011520), // FRECPE_ZZ_D |
| 2153 | UINT64_C(1699622912), // FRECPE_ZZ_H |
| 2154 | UINT64_C(1703817216), // FRECPE_ZZ_S |
| 2155 | UINT64_C(1593432064), // FRECPEv1f16 |
| 2156 | UINT64_C(1587664896), // FRECPEv1i32 |
| 2157 | UINT64_C(1591859200), // FRECPEv1i64 |
| 2158 | UINT64_C(245487616), // FRECPEv2f32 |
| 2159 | UINT64_C(1323423744), // FRECPEv2f64 |
| 2160 | UINT64_C(251254784), // FRECPEv4f16 |
| 2161 | UINT64_C(1319229440), // FRECPEv4f32 |
| 2162 | UINT64_C(1324996608), // FRECPEv8f16 |
| 2163 | UINT64_C(1581267968), // FRECPS16 |
| 2164 | UINT64_C(1579219968), // FRECPS32 |
| 2165 | UINT64_C(1583414272), // FRECPS64 |
| 2166 | UINT64_C(1707087872), // FRECPS_ZZZ_D |
| 2167 | UINT64_C(1698699264), // FRECPS_ZZZ_H |
| 2168 | UINT64_C(1702893568), // FRECPS_ZZZ_S |
| 2169 | UINT64_C(237042688), // FRECPSv2f32 |
| 2170 | UINT64_C(1314978816), // FRECPSv2f64 |
| 2171 | UINT64_C(239090688), // FRECPSv4f16 |
| 2172 | UINT64_C(1310784512), // FRECPSv4f32 |
| 2173 | UINT64_C(1312832512), // FRECPSv8f16 |
| 2174 | UINT64_C(1707909120), // FRECPX_ZPmZ_D |
| 2175 | UINT64_C(1699520512), // FRECPX_ZPmZ_H |
| 2176 | UINT64_C(1703714816), // FRECPX_ZPmZ_S |
| 2177 | UINT64_C(1593440256), // FRECPXv1f16 |
| 2178 | UINT64_C(1587673088), // FRECPXv1i32 |
| 2179 | UINT64_C(1591867392), // FRECPXv1i64 |
| 2180 | UINT64_C(510181376), // FRINT32XDr |
| 2181 | UINT64_C(505987072), // FRINT32XSr |
| 2182 | UINT64_C(773974016), // FRINT32Xv2f32 |
| 2183 | UINT64_C(1851910144), // FRINT32Xv2f64 |
| 2184 | UINT64_C(1847715840), // FRINT32Xv4f32 |
| 2185 | UINT64_C(510148608), // FRINT32ZDr |
| 2186 | UINT64_C(505954304), // FRINT32ZSr |
| 2187 | UINT64_C(237103104), // FRINT32Zv2f32 |
| 2188 | UINT64_C(1315039232), // FRINT32Zv2f64 |
| 2189 | UINT64_C(1310844928), // FRINT32Zv4f32 |
| 2190 | UINT64_C(510246912), // FRINT64XDr |
| 2191 | UINT64_C(506052608), // FRINT64XSr |
| 2192 | UINT64_C(773978112), // FRINT64Xv2f32 |
| 2193 | UINT64_C(1851914240), // FRINT64Xv2f64 |
| 2194 | UINT64_C(1847719936), // FRINT64Xv4f32 |
| 2195 | UINT64_C(510214144), // FRINT64ZDr |
| 2196 | UINT64_C(506019840), // FRINT64ZSr |
| 2197 | UINT64_C(237107200), // FRINT64Zv2f32 |
| 2198 | UINT64_C(1315043328), // FRINT64Zv2f64 |
| 2199 | UINT64_C(1310849024), // FRINT64Zv4f32 |
| 2200 | UINT64_C(510017536), // FRINTADr |
| 2201 | UINT64_C(518406144), // FRINTAHr |
| 2202 | UINT64_C(505823232), // FRINTASr |
| 2203 | UINT64_C(1707384832), // FRINTA_ZPmZ_D |
| 2204 | UINT64_C(1698996224), // FRINTA_ZPmZ_H |
| 2205 | UINT64_C(1703190528), // FRINTA_ZPmZ_S |
| 2206 | UINT64_C(773949440), // FRINTAv2f32 |
| 2207 | UINT64_C(1851885568), // FRINTAv2f64 |
| 2208 | UINT64_C(779716608), // FRINTAv4f16 |
| 2209 | UINT64_C(1847691264), // FRINTAv4f32 |
| 2210 | UINT64_C(1853458432), // FRINTAv8f16 |
| 2211 | UINT64_C(510115840), // FRINTIDr |
| 2212 | UINT64_C(518504448), // FRINTIHr |
| 2213 | UINT64_C(505921536), // FRINTISr |
| 2214 | UINT64_C(1707581440), // FRINTI_ZPmZ_D |
| 2215 | UINT64_C(1699192832), // FRINTI_ZPmZ_H |
| 2216 | UINT64_C(1703387136), // FRINTI_ZPmZ_S |
| 2217 | UINT64_C(782342144), // FRINTIv2f32 |
| 2218 | UINT64_C(1860278272), // FRINTIv2f64 |
| 2219 | UINT64_C(788109312), // FRINTIv4f16 |
| 2220 | UINT64_C(1856083968), // FRINTIv4f32 |
| 2221 | UINT64_C(1861851136), // FRINTIv8f16 |
| 2222 | UINT64_C(509952000), // FRINTMDr |
| 2223 | UINT64_C(518340608), // FRINTMHr |
| 2224 | UINT64_C(505757696), // FRINTMSr |
| 2225 | UINT64_C(1707253760), // FRINTM_ZPmZ_D |
| 2226 | UINT64_C(1698865152), // FRINTM_ZPmZ_H |
| 2227 | UINT64_C(1703059456), // FRINTM_ZPmZ_S |
| 2228 | UINT64_C(237082624), // FRINTMv2f32 |
| 2229 | UINT64_C(1315018752), // FRINTMv2f64 |
| 2230 | UINT64_C(242849792), // FRINTMv4f16 |
| 2231 | UINT64_C(1310824448), // FRINTMv4f32 |
| 2232 | UINT64_C(1316591616), // FRINTMv8f16 |
| 2233 | UINT64_C(509886464), // FRINTNDr |
| 2234 | UINT64_C(518275072), // FRINTNHr |
| 2235 | UINT64_C(505692160), // FRINTNSr |
| 2236 | UINT64_C(1707122688), // FRINTN_ZPmZ_D |
| 2237 | UINT64_C(1698734080), // FRINTN_ZPmZ_H |
| 2238 | UINT64_C(1702928384), // FRINTN_ZPmZ_S |
| 2239 | UINT64_C(237078528), // FRINTNv2f32 |
| 2240 | UINT64_C(1315014656), // FRINTNv2f64 |
| 2241 | UINT64_C(242845696), // FRINTNv4f16 |
| 2242 | UINT64_C(1310820352), // FRINTNv4f32 |
| 2243 | UINT64_C(1316587520), // FRINTNv8f16 |
| 2244 | UINT64_C(509919232), // FRINTPDr |
| 2245 | UINT64_C(518307840), // FRINTPHr |
| 2246 | UINT64_C(505724928), // FRINTPSr |
| 2247 | UINT64_C(1707188224), // FRINTP_ZPmZ_D |
| 2248 | UINT64_C(1698799616), // FRINTP_ZPmZ_H |
| 2249 | UINT64_C(1702993920), // FRINTP_ZPmZ_S |
| 2250 | UINT64_C(245467136), // FRINTPv2f32 |
| 2251 | UINT64_C(1323403264), // FRINTPv2f64 |
| 2252 | UINT64_C(251234304), // FRINTPv4f16 |
| 2253 | UINT64_C(1319208960), // FRINTPv4f32 |
| 2254 | UINT64_C(1324976128), // FRINTPv8f16 |
| 2255 | UINT64_C(510083072), // FRINTXDr |
| 2256 | UINT64_C(518471680), // FRINTXHr |
| 2257 | UINT64_C(505888768), // FRINTXSr |
| 2258 | UINT64_C(1707515904), // FRINTX_ZPmZ_D |
| 2259 | UINT64_C(1699127296), // FRINTX_ZPmZ_H |
| 2260 | UINT64_C(1703321600), // FRINTX_ZPmZ_S |
| 2261 | UINT64_C(773953536), // FRINTXv2f32 |
| 2262 | UINT64_C(1851889664), // FRINTXv2f64 |
| 2263 | UINT64_C(779720704), // FRINTXv4f16 |
| 2264 | UINT64_C(1847695360), // FRINTXv4f32 |
| 2265 | UINT64_C(1853462528), // FRINTXv8f16 |
| 2266 | UINT64_C(509984768), // FRINTZDr |
| 2267 | UINT64_C(518373376), // FRINTZHr |
| 2268 | UINT64_C(505790464), // FRINTZSr |
| 2269 | UINT64_C(1707319296), // FRINTZ_ZPmZ_D |
| 2270 | UINT64_C(1698930688), // FRINTZ_ZPmZ_H |
| 2271 | UINT64_C(1703124992), // FRINTZ_ZPmZ_S |
| 2272 | UINT64_C(245471232), // FRINTZv2f32 |
| 2273 | UINT64_C(1323407360), // FRINTZv2f64 |
| 2274 | UINT64_C(251238400), // FRINTZv4f16 |
| 2275 | UINT64_C(1319213056), // FRINTZv4f32 |
| 2276 | UINT64_C(1324980224), // FRINTZv8f16 |
| 2277 | UINT64_C(1708077056), // FRSQRTE_ZZ_D |
| 2278 | UINT64_C(1699688448), // FRSQRTE_ZZ_H |
| 2279 | UINT64_C(1703882752), // FRSQRTE_ZZ_S |
| 2280 | UINT64_C(2130302976), // FRSQRTEv1f16 |
| 2281 | UINT64_C(2124535808), // FRSQRTEv1i32 |
| 2282 | UINT64_C(2128730112), // FRSQRTEv1i64 |
| 2283 | UINT64_C(782358528), // FRSQRTEv2f32 |
| 2284 | UINT64_C(1860294656), // FRSQRTEv2f64 |
| 2285 | UINT64_C(788125696), // FRSQRTEv4f16 |
| 2286 | UINT64_C(1856100352), // FRSQRTEv4f32 |
| 2287 | UINT64_C(1861867520), // FRSQRTEv8f16 |
| 2288 | UINT64_C(1589656576), // FRSQRTS16 |
| 2289 | UINT64_C(1587608576), // FRSQRTS32 |
| 2290 | UINT64_C(1591802880), // FRSQRTS64 |
| 2291 | UINT64_C(1707088896), // FRSQRTS_ZZZ_D |
| 2292 | UINT64_C(1698700288), // FRSQRTS_ZZZ_H |
| 2293 | UINT64_C(1702894592), // FRSQRTS_ZZZ_S |
| 2294 | UINT64_C(245431296), // FRSQRTSv2f32 |
| 2295 | UINT64_C(1323367424), // FRSQRTSv2f64 |
| 2296 | UINT64_C(247479296), // FRSQRTSv4f16 |
| 2297 | UINT64_C(1319173120), // FRSQRTSv4f32 |
| 2298 | UINT64_C(1321221120), // FRSQRTSv8f16 |
| 2299 | UINT64_C(1707704320), // FSCALE_ZPmZ_D |
| 2300 | UINT64_C(1699315712), // FSCALE_ZPmZ_H |
| 2301 | UINT64_C(1703510016), // FSCALE_ZPmZ_S |
| 2302 | UINT64_C(509722624), // FSQRTDr |
| 2303 | UINT64_C(518111232), // FSQRTHr |
| 2304 | UINT64_C(505528320), // FSQRTSr |
| 2305 | UINT64_C(1707974656), // FSQRT_ZPmZ_D |
| 2306 | UINT64_C(1699586048), // FSQRT_ZPmZ_H |
| 2307 | UINT64_C(1703780352), // FSQRT_ZPmZ_S |
| 2308 | UINT64_C(782366720), // FSQRTv2f32 |
| 2309 | UINT64_C(1860302848), // FSQRTv2f64 |
| 2310 | UINT64_C(788133888), // FSQRTv4f16 |
| 2311 | UINT64_C(1856108544), // FSQRTv4f32 |
| 2312 | UINT64_C(1861875712), // FSQRTv8f16 |
| 2313 | UINT64_C(509622272), // FSUBDrr |
| 2314 | UINT64_C(518010880), // FSUBHrr |
| 2315 | UINT64_C(1708883968), // FSUBR_ZPmI_D |
| 2316 | UINT64_C(1700495360), // FSUBR_ZPmI_H |
| 2317 | UINT64_C(1704689664), // FSUBR_ZPmI_S |
| 2318 | UINT64_C(1707311104), // FSUBR_ZPmZ_D |
| 2319 | UINT64_C(1698922496), // FSUBR_ZPmZ_H |
| 2320 | UINT64_C(1703116800), // FSUBR_ZPmZ_S |
| 2321 | UINT64_C(505427968), // FSUBSrr |
| 2322 | UINT64_C(1708752896), // FSUB_ZPmI_D |
| 2323 | UINT64_C(1700364288), // FSUB_ZPmI_H |
| 2324 | UINT64_C(1704558592), // FSUB_ZPmI_S |
| 2325 | UINT64_C(1707180032), // FSUB_ZPmZ_D |
| 2326 | UINT64_C(1698791424), // FSUB_ZPmZ_H |
| 2327 | UINT64_C(1702985728), // FSUB_ZPmZ_S |
| 2328 | UINT64_C(1707082752), // FSUB_ZZZ_D |
| 2329 | UINT64_C(1698694144), // FSUB_ZZZ_H |
| 2330 | UINT64_C(1702888448), // FSUB_ZZZ_S |
| 2331 | UINT64_C(245421056), // FSUBv2f32 |
| 2332 | UINT64_C(1323357184), // FSUBv2f64 |
| 2333 | UINT64_C(247469056), // FSUBv4f16 |
| 2334 | UINT64_C(1319162880), // FSUBv4f32 |
| 2335 | UINT64_C(1321210880), // FSUBv8f16 |
| 2336 | UINT64_C(1708163072), // FTMAD_ZZI_D |
| 2337 | UINT64_C(1699774464), // FTMAD_ZZI_H |
| 2338 | UINT64_C(1703968768), // FTMAD_ZZI_S |
| 2339 | UINT64_C(1707084800), // FTSMUL_ZZZ_D |
| 2340 | UINT64_C(1698696192), // FTSMUL_ZZZ_H |
| 2341 | UINT64_C(1702890496), // FTSMUL_ZZZ_S |
| 2342 | UINT64_C(81833984), // FTSSEL_ZZZ_D |
| 2343 | UINT64_C(73445376), // FTSSEL_ZZZ_H |
| 2344 | UINT64_C(77639680), // FTSSEL_ZZZ_S |
| 2345 | UINT64_C(3290480640), // GLD1B_D_IMM_REAL |
| 2346 | UINT64_C(3292577792), // GLD1B_D_REAL |
| 2347 | UINT64_C(3292545024), // GLD1B_D_SXTW_REAL |
| 2348 | UINT64_C(3288350720), // GLD1B_D_UXTW_REAL |
| 2349 | UINT64_C(2216738816), // GLD1B_S_IMM_REAL |
| 2350 | UINT64_C(2218803200), // GLD1B_S_SXTW_REAL |
| 2351 | UINT64_C(2214608896), // GLD1B_S_UXTW_REAL |
| 2352 | UINT64_C(3315646464), // GLD1D_IMM_REAL |
| 2353 | UINT64_C(3317743616), // GLD1D_REAL |
| 2354 | UINT64_C(3319840768), // GLD1D_SCALED_REAL |
| 2355 | UINT64_C(3317710848), // GLD1D_SXTW_REAL |
| 2356 | UINT64_C(3319808000), // GLD1D_SXTW_SCALED_REAL |
| 2357 | UINT64_C(3313516544), // GLD1D_UXTW_REAL |
| 2358 | UINT64_C(3315613696), // GLD1D_UXTW_SCALED_REAL |
| 2359 | UINT64_C(3298869248), // GLD1H_D_IMM_REAL |
| 2360 | UINT64_C(3300966400), // GLD1H_D_REAL |
| 2361 | UINT64_C(3303063552), // GLD1H_D_SCALED_REAL |
| 2362 | UINT64_C(3300933632), // GLD1H_D_SXTW_REAL |
| 2363 | UINT64_C(3303030784), // GLD1H_D_SXTW_SCALED_REAL |
| 2364 | UINT64_C(3296739328), // GLD1H_D_UXTW_REAL |
| 2365 | UINT64_C(3298836480), // GLD1H_D_UXTW_SCALED_REAL |
| 2366 | UINT64_C(2225127424), // GLD1H_S_IMM_REAL |
| 2367 | UINT64_C(2227191808), // GLD1H_S_SXTW_REAL |
| 2368 | UINT64_C(2229288960), // GLD1H_S_SXTW_SCALED_REAL |
| 2369 | UINT64_C(2222997504), // GLD1H_S_UXTW_REAL |
| 2370 | UINT64_C(2225094656), // GLD1H_S_UXTW_SCALED_REAL |
| 2371 | UINT64_C(3290464256), // GLD1SB_D_IMM_REAL |
| 2372 | UINT64_C(3292561408), // GLD1SB_D_REAL |
| 2373 | UINT64_C(3292528640), // GLD1SB_D_SXTW_REAL |
| 2374 | UINT64_C(3288334336), // GLD1SB_D_UXTW_REAL |
| 2375 | UINT64_C(2216722432), // GLD1SB_S_IMM_REAL |
| 2376 | UINT64_C(2218786816), // GLD1SB_S_SXTW_REAL |
| 2377 | UINT64_C(2214592512), // GLD1SB_S_UXTW_REAL |
| 2378 | UINT64_C(3298852864), // GLD1SH_D_IMM_REAL |
| 2379 | UINT64_C(3300950016), // GLD1SH_D_REAL |
| 2380 | UINT64_C(3303047168), // GLD1SH_D_SCALED_REAL |
| 2381 | UINT64_C(3300917248), // GLD1SH_D_SXTW_REAL |
| 2382 | UINT64_C(3303014400), // GLD1SH_D_SXTW_SCALED_REAL |
| 2383 | UINT64_C(3296722944), // GLD1SH_D_UXTW_REAL |
| 2384 | UINT64_C(3298820096), // GLD1SH_D_UXTW_SCALED_REAL |
| 2385 | UINT64_C(2225111040), // GLD1SH_S_IMM_REAL |
| 2386 | UINT64_C(2227175424), // GLD1SH_S_SXTW_REAL |
| 2387 | UINT64_C(2229272576), // GLD1SH_S_SXTW_SCALED_REAL |
| 2388 | UINT64_C(2222981120), // GLD1SH_S_UXTW_REAL |
| 2389 | UINT64_C(2225078272), // GLD1SH_S_UXTW_SCALED_REAL |
| 2390 | UINT64_C(3307241472), // GLD1SW_D_IMM_REAL |
| 2391 | UINT64_C(3309338624), // GLD1SW_D_REAL |
| 2392 | UINT64_C(3311435776), // GLD1SW_D_SCALED_REAL |
| 2393 | UINT64_C(3309305856), // GLD1SW_D_SXTW_REAL |
| 2394 | UINT64_C(3311403008), // GLD1SW_D_SXTW_SCALED_REAL |
| 2395 | UINT64_C(3305111552), // GLD1SW_D_UXTW_REAL |
| 2396 | UINT64_C(3307208704), // GLD1SW_D_UXTW_SCALED_REAL |
| 2397 | UINT64_C(3307257856), // GLD1W_D_IMM_REAL |
| 2398 | UINT64_C(3309355008), // GLD1W_D_REAL |
| 2399 | UINT64_C(3311452160), // GLD1W_D_SCALED_REAL |
| 2400 | UINT64_C(3309322240), // GLD1W_D_SXTW_REAL |
| 2401 | UINT64_C(3311419392), // GLD1W_D_SXTW_SCALED_REAL |
| 2402 | UINT64_C(3305127936), // GLD1W_D_UXTW_REAL |
| 2403 | UINT64_C(3307225088), // GLD1W_D_UXTW_SCALED_REAL |
| 2404 | UINT64_C(2233516032), // GLD1W_IMM_REAL |
| 2405 | UINT64_C(2235580416), // GLD1W_SXTW_REAL |
| 2406 | UINT64_C(2237677568), // GLD1W_SXTW_SCALED_REAL |
| 2407 | UINT64_C(2231386112), // GLD1W_UXTW_REAL |
| 2408 | UINT64_C(2233483264), // GLD1W_UXTW_SCALED_REAL |
| 2409 | UINT64_C(3290488832), // GLDFF1B_D_IMM_REAL |
| 2410 | UINT64_C(3292585984), // GLDFF1B_D_REAL |
| 2411 | UINT64_C(3292553216), // GLDFF1B_D_SXTW_REAL |
| 2412 | UINT64_C(3288358912), // GLDFF1B_D_UXTW_REAL |
| 2413 | UINT64_C(2216747008), // GLDFF1B_S_IMM_REAL |
| 2414 | UINT64_C(2218811392), // GLDFF1B_S_SXTW_REAL |
| 2415 | UINT64_C(2214617088), // GLDFF1B_S_UXTW_REAL |
| 2416 | UINT64_C(3315654656), // GLDFF1D_IMM_REAL |
| 2417 | UINT64_C(3317751808), // GLDFF1D_REAL |
| 2418 | UINT64_C(3319848960), // GLDFF1D_SCALED_REAL |
| 2419 | UINT64_C(3317719040), // GLDFF1D_SXTW_REAL |
| 2420 | UINT64_C(3319816192), // GLDFF1D_SXTW_SCALED_REAL |
| 2421 | UINT64_C(3313524736), // GLDFF1D_UXTW_REAL |
| 2422 | UINT64_C(3315621888), // GLDFF1D_UXTW_SCALED_REAL |
| 2423 | UINT64_C(3298877440), // GLDFF1H_D_IMM_REAL |
| 2424 | UINT64_C(3300974592), // GLDFF1H_D_REAL |
| 2425 | UINT64_C(3303071744), // GLDFF1H_D_SCALED_REAL |
| 2426 | UINT64_C(3300941824), // GLDFF1H_D_SXTW_REAL |
| 2427 | UINT64_C(3303038976), // GLDFF1H_D_SXTW_SCALED_REAL |
| 2428 | UINT64_C(3296747520), // GLDFF1H_D_UXTW_REAL |
| 2429 | UINT64_C(3298844672), // GLDFF1H_D_UXTW_SCALED_REAL |
| 2430 | UINT64_C(2225135616), // GLDFF1H_S_IMM_REAL |
| 2431 | UINT64_C(2227200000), // GLDFF1H_S_SXTW_REAL |
| 2432 | UINT64_C(2229297152), // GLDFF1H_S_SXTW_SCALED_REAL |
| 2433 | UINT64_C(2223005696), // GLDFF1H_S_UXTW_REAL |
| 2434 | UINT64_C(2225102848), // GLDFF1H_S_UXTW_SCALED_REAL |
| 2435 | UINT64_C(3290472448), // GLDFF1SB_D_IMM_REAL |
| 2436 | UINT64_C(3292569600), // GLDFF1SB_D_REAL |
| 2437 | UINT64_C(3292536832), // GLDFF1SB_D_SXTW_REAL |
| 2438 | UINT64_C(3288342528), // GLDFF1SB_D_UXTW_REAL |
| 2439 | UINT64_C(2216730624), // GLDFF1SB_S_IMM_REAL |
| 2440 | UINT64_C(2218795008), // GLDFF1SB_S_SXTW_REAL |
| 2441 | UINT64_C(2214600704), // GLDFF1SB_S_UXTW_REAL |
| 2442 | UINT64_C(3298861056), // GLDFF1SH_D_IMM_REAL |
| 2443 | UINT64_C(3300958208), // GLDFF1SH_D_REAL |
| 2444 | UINT64_C(3303055360), // GLDFF1SH_D_SCALED_REAL |
| 2445 | UINT64_C(3300925440), // GLDFF1SH_D_SXTW_REAL |
| 2446 | UINT64_C(3303022592), // GLDFF1SH_D_SXTW_SCALED_REAL |
| 2447 | UINT64_C(3296731136), // GLDFF1SH_D_UXTW_REAL |
| 2448 | UINT64_C(3298828288), // GLDFF1SH_D_UXTW_SCALED_REAL |
| 2449 | UINT64_C(2225119232), // GLDFF1SH_S_IMM_REAL |
| 2450 | UINT64_C(2227183616), // GLDFF1SH_S_SXTW_REAL |
| 2451 | UINT64_C(2229280768), // GLDFF1SH_S_SXTW_SCALED_REAL |
| 2452 | UINT64_C(2222989312), // GLDFF1SH_S_UXTW_REAL |
| 2453 | UINT64_C(2225086464), // GLDFF1SH_S_UXTW_SCALED_REAL |
| 2454 | UINT64_C(3307249664), // GLDFF1SW_D_IMM_REAL |
| 2455 | UINT64_C(3309346816), // GLDFF1SW_D_REAL |
| 2456 | UINT64_C(3311443968), // GLDFF1SW_D_SCALED_REAL |
| 2457 | UINT64_C(3309314048), // GLDFF1SW_D_SXTW_REAL |
| 2458 | UINT64_C(3311411200), // GLDFF1SW_D_SXTW_SCALED_REAL |
| 2459 | UINT64_C(3305119744), // GLDFF1SW_D_UXTW_REAL |
| 2460 | UINT64_C(3307216896), // GLDFF1SW_D_UXTW_SCALED_REAL |
| 2461 | UINT64_C(3307266048), // GLDFF1W_D_IMM_REAL |
| 2462 | UINT64_C(3309363200), // GLDFF1W_D_REAL |
| 2463 | UINT64_C(3311460352), // GLDFF1W_D_SCALED_REAL |
| 2464 | UINT64_C(3309330432), // GLDFF1W_D_SXTW_REAL |
| 2465 | UINT64_C(3311427584), // GLDFF1W_D_SXTW_SCALED_REAL |
| 2466 | UINT64_C(3305136128), // GLDFF1W_D_UXTW_REAL |
| 2467 | UINT64_C(3307233280), // GLDFF1W_D_UXTW_SCALED_REAL |
| 2468 | UINT64_C(2233524224), // GLDFF1W_IMM_REAL |
| 2469 | UINT64_C(2235588608), // GLDFF1W_SXTW_REAL |
| 2470 | UINT64_C(2237685760), // GLDFF1W_SXTW_SCALED_REAL |
| 2471 | UINT64_C(2231394304), // GLDFF1W_UXTW_REAL |
| 2472 | UINT64_C(2233491456), // GLDFF1W_UXTW_SCALED_REAL |
| 2473 | UINT64_C(2596279296), // GMI |
| 2474 | UINT64_C(3573751839), // HINT |
| 2475 | UINT64_C(1172357120), // HISTCNT_ZPzZZ_D |
| 2476 | UINT64_C(1168162816), // HISTCNT_ZPzZZ_S |
| 2477 | UINT64_C(1159766016), // HISTSEG_ZZZ |
| 2478 | UINT64_C(3560964096), // HLT |
| 2479 | UINT64_C(3556769794), // HVC |
| 2480 | UINT64_C(70311936), // INCB_XPiI |
| 2481 | UINT64_C(82894848), // INCD_XPiI |
| 2482 | UINT64_C(82886656), // INCD_ZPiI |
| 2483 | UINT64_C(74506240), // INCH_XPiI |
| 2484 | UINT64_C(74498048), // INCH_ZPiI |
| 2485 | UINT64_C(623675392), // INCP_XP_B |
| 2486 | UINT64_C(636258304), // INCP_XP_D |
| 2487 | UINT64_C(627869696), // INCP_XP_H |
| 2488 | UINT64_C(632064000), // INCP_XP_S |
| 2489 | UINT64_C(636256256), // INCP_ZP_D |
| 2490 | UINT64_C(627867648), // INCP_ZP_H |
| 2491 | UINT64_C(632061952), // INCP_ZP_S |
| 2492 | UINT64_C(78700544), // INCW_XPiI |
| 2493 | UINT64_C(78692352), // INCW_ZPiI |
| 2494 | UINT64_C(69222400), // INDEX_II_B |
| 2495 | UINT64_C(81805312), // INDEX_II_D |
| 2496 | UINT64_C(73416704), // INDEX_II_H |
| 2497 | UINT64_C(77611008), // INDEX_II_S |
| 2498 | UINT64_C(69224448), // INDEX_IR_B |
| 2499 | UINT64_C(81807360), // INDEX_IR_D |
| 2500 | UINT64_C(73418752), // INDEX_IR_H |
| 2501 | UINT64_C(77613056), // INDEX_IR_S |
| 2502 | UINT64_C(69223424), // INDEX_RI_B |
| 2503 | UINT64_C(81806336), // INDEX_RI_D |
| 2504 | UINT64_C(73417728), // INDEX_RI_H |
| 2505 | UINT64_C(77612032), // INDEX_RI_S |
| 2506 | UINT64_C(69225472), // INDEX_RR_B |
| 2507 | UINT64_C(81808384), // INDEX_RR_D |
| 2508 | UINT64_C(73419776), // INDEX_RR_H |
| 2509 | UINT64_C(77614080), // INDEX_RR_S |
| 2510 | UINT64_C(86259712), // INSR_ZR_B |
| 2511 | UINT64_C(98842624), // INSR_ZR_D |
| 2512 | UINT64_C(90454016), // INSR_ZR_H |
| 2513 | UINT64_C(94648320), // INSR_ZR_S |
| 2514 | UINT64_C(87308288), // INSR_ZV_B |
| 2515 | UINT64_C(99891200), // INSR_ZV_D |
| 2516 | UINT64_C(91502592), // INSR_ZV_H |
| 2517 | UINT64_C(95696896), // INSR_ZV_S |
| 2518 | UINT64_C(1308761088), // INSvi16gpr |
| 2519 | UINT64_C(1845625856), // INSvi16lane |
| 2520 | UINT64_C(1308892160), // INSvi32gpr |
| 2521 | UINT64_C(1845756928), // INSvi32lane |
| 2522 | UINT64_C(1309154304), // INSvi64gpr |
| 2523 | UINT64_C(1846019072), // INSvi64lane |
| 2524 | UINT64_C(1308695552), // INSvi8gpr |
| 2525 | UINT64_C(1845560320), // INSvi8lane |
| 2526 | UINT64_C(2596278272), // IRG |
| 2527 | UINT64_C(3573756127), // ISB |
| 2528 | UINT64_C(86024192), // LASTA_RPZ_B |
| 2529 | UINT64_C(98607104), // LASTA_RPZ_D |
| 2530 | UINT64_C(90218496), // LASTA_RPZ_H |
| 2531 | UINT64_C(94412800), // LASTA_RPZ_S |
| 2532 | UINT64_C(86147072), // LASTA_VPZ_B |
| 2533 | UINT64_C(98729984), // LASTA_VPZ_D |
| 2534 | UINT64_C(90341376), // LASTA_VPZ_H |
| 2535 | UINT64_C(94535680), // LASTA_VPZ_S |
| 2536 | UINT64_C(86089728), // LASTB_RPZ_B |
| 2537 | UINT64_C(98672640), // LASTB_RPZ_D |
| 2538 | UINT64_C(90284032), // LASTB_RPZ_H |
| 2539 | UINT64_C(94478336), // LASTB_RPZ_S |
| 2540 | UINT64_C(86212608), // LASTB_VPZ_B |
| 2541 | UINT64_C(98795520), // LASTB_VPZ_D |
| 2542 | UINT64_C(90406912), // LASTB_VPZ_H |
| 2543 | UINT64_C(94601216), // LASTB_VPZ_S |
| 2544 | UINT64_C(2751479808), // LD1B |
| 2545 | UINT64_C(2757771264), // LD1B_D |
| 2546 | UINT64_C(2757795840), // LD1B_D_IMM_REAL |
| 2547 | UINT64_C(2753576960), // LD1B_H |
| 2548 | UINT64_C(2753601536), // LD1B_H_IMM_REAL |
| 2549 | UINT64_C(2751504384), // LD1B_IMM_REAL |
| 2550 | UINT64_C(2755674112), // LD1B_S |
| 2551 | UINT64_C(2755698688), // LD1B_S_IMM_REAL |
| 2552 | UINT64_C(2782937088), // LD1D |
| 2553 | UINT64_C(2782961664), // LD1D_IMM_REAL |
| 2554 | UINT64_C(1279270912), // LD1Fourv16b |
| 2555 | UINT64_C(1287659520), // LD1Fourv16b_POST |
| 2556 | UINT64_C(205532160), // LD1Fourv1d |
| 2557 | UINT64_C(213920768), // LD1Fourv1d_POST |
| 2558 | UINT64_C(1279273984), // LD1Fourv2d |
| 2559 | UINT64_C(1287662592), // LD1Fourv2d_POST |
| 2560 | UINT64_C(205531136), // LD1Fourv2s |
| 2561 | UINT64_C(213919744), // LD1Fourv2s_POST |
| 2562 | UINT64_C(205530112), // LD1Fourv4h |
| 2563 | UINT64_C(213918720), // LD1Fourv4h_POST |
| 2564 | UINT64_C(1279272960), // LD1Fourv4s |
| 2565 | UINT64_C(1287661568), // LD1Fourv4s_POST |
| 2566 | UINT64_C(205529088), // LD1Fourv8b |
| 2567 | UINT64_C(213917696), // LD1Fourv8b_POST |
| 2568 | UINT64_C(1279271936), // LD1Fourv8h |
| 2569 | UINT64_C(1287660544), // LD1Fourv8h_POST |
| 2570 | UINT64_C(2761965568), // LD1H |
| 2571 | UINT64_C(2766159872), // LD1H_D |
| 2572 | UINT64_C(2766184448), // LD1H_D_IMM_REAL |
| 2573 | UINT64_C(2761990144), // LD1H_IMM_REAL |
| 2574 | UINT64_C(2764062720), // LD1H_S |
| 2575 | UINT64_C(2764087296), // LD1H_S_IMM_REAL |
| 2576 | UINT64_C(1279291392), // LD1Onev16b |
| 2577 | UINT64_C(1287680000), // LD1Onev16b_POST |
| 2578 | UINT64_C(205552640), // LD1Onev1d |
| 2579 | UINT64_C(213941248), // LD1Onev1d_POST |
| 2580 | UINT64_C(1279294464), // LD1Onev2d |
| 2581 | UINT64_C(1287683072), // LD1Onev2d_POST |
| 2582 | UINT64_C(205551616), // LD1Onev2s |
| 2583 | UINT64_C(213940224), // LD1Onev2s_POST |
| 2584 | UINT64_C(205550592), // LD1Onev4h |
| 2585 | UINT64_C(213939200), // LD1Onev4h_POST |
| 2586 | UINT64_C(1279293440), // LD1Onev4s |
| 2587 | UINT64_C(1287682048), // LD1Onev4s_POST |
| 2588 | UINT64_C(205549568), // LD1Onev8b |
| 2589 | UINT64_C(213938176), // LD1Onev8b_POST |
| 2590 | UINT64_C(1279292416), // LD1Onev8h |
| 2591 | UINT64_C(1287681024), // LD1Onev8h_POST |
| 2592 | UINT64_C(2218844160), // LD1RB_D_IMM |
| 2593 | UINT64_C(2218827776), // LD1RB_H_IMM |
| 2594 | UINT64_C(2218819584), // LD1RB_IMM |
| 2595 | UINT64_C(2218835968), // LD1RB_S_IMM |
| 2596 | UINT64_C(2244009984), // LD1RD_IMM |
| 2597 | UINT64_C(2227232768), // LD1RH_D_IMM |
| 2598 | UINT64_C(2227216384), // LD1RH_IMM |
| 2599 | UINT64_C(2227224576), // LD1RH_S_IMM |
| 2600 | UINT64_C(2753560576), // LD1RO_B |
| 2601 | UINT64_C(2753568768), // LD1RO_B_IMM |
| 2602 | UINT64_C(2778726400), // LD1RO_D |
| 2603 | UINT64_C(2778734592), // LD1RO_D_IMM |
| 2604 | UINT64_C(2761949184), // LD1RO_H |
| 2605 | UINT64_C(2761957376), // LD1RO_H_IMM |
| 2606 | UINT64_C(2770337792), // LD1RO_W |
| 2607 | UINT64_C(2770345984), // LD1RO_W_IMM |
| 2608 | UINT64_C(2751463424), // LD1RQ_B |
| 2609 | UINT64_C(2751471616), // LD1RQ_B_IMM |
| 2610 | UINT64_C(2776629248), // LD1RQ_D |
| 2611 | UINT64_C(2776637440), // LD1RQ_D_IMM |
| 2612 | UINT64_C(2759852032), // LD1RQ_H |
| 2613 | UINT64_C(2759860224), // LD1RQ_H_IMM |
| 2614 | UINT64_C(2768240640), // LD1RQ_W |
| 2615 | UINT64_C(2768248832), // LD1RQ_W_IMM |
| 2616 | UINT64_C(2243985408), // LD1RSB_D_IMM |
| 2617 | UINT64_C(2244001792), // LD1RSB_H_IMM |
| 2618 | UINT64_C(2243993600), // LD1RSB_S_IMM |
| 2619 | UINT64_C(2235596800), // LD1RSH_D_IMM |
| 2620 | UINT64_C(2235604992), // LD1RSH_S_IMM |
| 2621 | UINT64_C(2227208192), // LD1RSW_IMM |
| 2622 | UINT64_C(2235621376), // LD1RW_D_IMM |
| 2623 | UINT64_C(2235613184), // LD1RW_IMM |
| 2624 | UINT64_C(1296089088), // LD1Rv16b |
| 2625 | UINT64_C(1304477696), // LD1Rv16b_POST |
| 2626 | UINT64_C(222350336), // LD1Rv1d |
| 2627 | UINT64_C(230738944), // LD1Rv1d_POST |
| 2628 | UINT64_C(1296092160), // LD1Rv2d |
| 2629 | UINT64_C(1304480768), // LD1Rv2d_POST |
| 2630 | UINT64_C(222349312), // LD1Rv2s |
| 2631 | UINT64_C(230737920), // LD1Rv2s_POST |
| 2632 | UINT64_C(222348288), // LD1Rv4h |
| 2633 | UINT64_C(230736896), // LD1Rv4h_POST |
| 2634 | UINT64_C(1296091136), // LD1Rv4s |
| 2635 | UINT64_C(1304479744), // LD1Rv4s_POST |
| 2636 | UINT64_C(222347264), // LD1Rv8b |
| 2637 | UINT64_C(230735872), // LD1Rv8b_POST |
| 2638 | UINT64_C(1296090112), // LD1Rv8h |
| 2639 | UINT64_C(1304478720), // LD1Rv8h_POST |
| 2640 | UINT64_C(2776645632), // LD1SB_D |
| 2641 | UINT64_C(2776670208), // LD1SB_D_IMM_REAL |
| 2642 | UINT64_C(2780839936), // LD1SB_H |
| 2643 | UINT64_C(2780864512), // LD1SB_H_IMM_REAL |
| 2644 | UINT64_C(2778742784), // LD1SB_S |
| 2645 | UINT64_C(2778767360), // LD1SB_S_IMM_REAL |
| 2646 | UINT64_C(2768257024), // LD1SH_D |
| 2647 | UINT64_C(2768281600), // LD1SH_D_IMM_REAL |
| 2648 | UINT64_C(2770354176), // LD1SH_S |
| 2649 | UINT64_C(2770378752), // LD1SH_S_IMM_REAL |
| 2650 | UINT64_C(2759868416), // LD1SW_D |
| 2651 | UINT64_C(2759892992), // LD1SW_D_IMM_REAL |
| 2652 | UINT64_C(1279287296), // LD1Threev16b |
| 2653 | UINT64_C(1287675904), // LD1Threev16b_POST |
| 2654 | UINT64_C(205548544), // LD1Threev1d |
| 2655 | UINT64_C(213937152), // LD1Threev1d_POST |
| 2656 | UINT64_C(1279290368), // LD1Threev2d |
| 2657 | UINT64_C(1287678976), // LD1Threev2d_POST |
| 2658 | UINT64_C(205547520), // LD1Threev2s |
| 2659 | UINT64_C(213936128), // LD1Threev2s_POST |
| 2660 | UINT64_C(205546496), // LD1Threev4h |
| 2661 | UINT64_C(213935104), // LD1Threev4h_POST |
| 2662 | UINT64_C(1279289344), // LD1Threev4s |
| 2663 | UINT64_C(1287677952), // LD1Threev4s_POST |
| 2664 | UINT64_C(205545472), // LD1Threev8b |
| 2665 | UINT64_C(213934080), // LD1Threev8b_POST |
| 2666 | UINT64_C(1279288320), // LD1Threev8h |
| 2667 | UINT64_C(1287676928), // LD1Threev8h_POST |
| 2668 | UINT64_C(1279303680), // LD1Twov16b |
| 2669 | UINT64_C(1287692288), // LD1Twov16b_POST |
| 2670 | UINT64_C(205564928), // LD1Twov1d |
| 2671 | UINT64_C(213953536), // LD1Twov1d_POST |
| 2672 | UINT64_C(1279306752), // LD1Twov2d |
| 2673 | UINT64_C(1287695360), // LD1Twov2d_POST |
| 2674 | UINT64_C(205563904), // LD1Twov2s |
| 2675 | UINT64_C(213952512), // LD1Twov2s_POST |
| 2676 | UINT64_C(205562880), // LD1Twov4h |
| 2677 | UINT64_C(213951488), // LD1Twov4h_POST |
| 2678 | UINT64_C(1279305728), // LD1Twov4s |
| 2679 | UINT64_C(1287694336), // LD1Twov4s_POST |
| 2680 | UINT64_C(205561856), // LD1Twov8b |
| 2681 | UINT64_C(213950464), // LD1Twov8b_POST |
| 2682 | UINT64_C(1279304704), // LD1Twov8h |
| 2683 | UINT64_C(1287693312), // LD1Twov8h_POST |
| 2684 | UINT64_C(2772451328), // LD1W |
| 2685 | UINT64_C(2774548480), // LD1W_D |
| 2686 | UINT64_C(2774573056), // LD1W_D_IMM_REAL |
| 2687 | UINT64_C(2772475904), // LD1W_IMM_REAL |
| 2688 | UINT64_C(222314496), // LD1i16 |
| 2689 | UINT64_C(230703104), // LD1i16_POST |
| 2690 | UINT64_C(222330880), // LD1i32 |
| 2691 | UINT64_C(230719488), // LD1i32_POST |
| 2692 | UINT64_C(222331904), // LD1i64 |
| 2693 | UINT64_C(230720512), // LD1i64_POST |
| 2694 | UINT64_C(222298112), // LD1i8 |
| 2695 | UINT64_C(230686720), // LD1i8_POST |
| 2696 | UINT64_C(2753609728), // LD2B |
| 2697 | UINT64_C(2753617920), // LD2B_IMM |
| 2698 | UINT64_C(2778775552), // LD2D |
| 2699 | UINT64_C(2778783744), // LD2D_IMM |
| 2700 | UINT64_C(2761998336), // LD2H |
| 2701 | UINT64_C(2762006528), // LD2H_IMM |
| 2702 | UINT64_C(1298186240), // LD2Rv16b |
| 2703 | UINT64_C(1306574848), // LD2Rv16b_POST |
| 2704 | UINT64_C(224447488), // LD2Rv1d |
| 2705 | UINT64_C(232836096), // LD2Rv1d_POST |
| 2706 | UINT64_C(1298189312), // LD2Rv2d |
| 2707 | UINT64_C(1306577920), // LD2Rv2d_POST |
| 2708 | UINT64_C(224446464), // LD2Rv2s |
| 2709 | UINT64_C(232835072), // LD2Rv2s_POST |
| 2710 | UINT64_C(224445440), // LD2Rv4h |
| 2711 | UINT64_C(232834048), // LD2Rv4h_POST |
| 2712 | UINT64_C(1298188288), // LD2Rv4s |
| 2713 | UINT64_C(1306576896), // LD2Rv4s_POST |
| 2714 | UINT64_C(224444416), // LD2Rv8b |
| 2715 | UINT64_C(232833024), // LD2Rv8b_POST |
| 2716 | UINT64_C(1298187264), // LD2Rv8h |
| 2717 | UINT64_C(1306575872), // LD2Rv8h_POST |
| 2718 | UINT64_C(1279295488), // LD2Twov16b |
| 2719 | UINT64_C(1287684096), // LD2Twov16b_POST |
| 2720 | UINT64_C(1279298560), // LD2Twov2d |
| 2721 | UINT64_C(1287687168), // LD2Twov2d_POST |
| 2722 | UINT64_C(205555712), // LD2Twov2s |
| 2723 | UINT64_C(213944320), // LD2Twov2s_POST |
| 2724 | UINT64_C(205554688), // LD2Twov4h |
| 2725 | UINT64_C(213943296), // LD2Twov4h_POST |
| 2726 | UINT64_C(1279297536), // LD2Twov4s |
| 2727 | UINT64_C(1287686144), // LD2Twov4s_POST |
| 2728 | UINT64_C(205553664), // LD2Twov8b |
| 2729 | UINT64_C(213942272), // LD2Twov8b_POST |
| 2730 | UINT64_C(1279296512), // LD2Twov8h |
| 2731 | UINT64_C(1287685120), // LD2Twov8h_POST |
| 2732 | UINT64_C(2770386944), // LD2W |
| 2733 | UINT64_C(2770395136), // LD2W_IMM |
| 2734 | UINT64_C(224411648), // LD2i16 |
| 2735 | UINT64_C(232800256), // LD2i16_POST |
| 2736 | UINT64_C(224428032), // LD2i32 |
| 2737 | UINT64_C(232816640), // LD2i32_POST |
| 2738 | UINT64_C(224429056), // LD2i64 |
| 2739 | UINT64_C(232817664), // LD2i64_POST |
| 2740 | UINT64_C(224395264), // LD2i8 |
| 2741 | UINT64_C(232783872), // LD2i8_POST |
| 2742 | UINT64_C(2755706880), // LD3B |
| 2743 | UINT64_C(2755715072), // LD3B_IMM |
| 2744 | UINT64_C(2780872704), // LD3D |
| 2745 | UINT64_C(2780880896), // LD3D_IMM |
| 2746 | UINT64_C(2764095488), // LD3H |
| 2747 | UINT64_C(2764103680), // LD3H_IMM |
| 2748 | UINT64_C(1296097280), // LD3Rv16b |
| 2749 | UINT64_C(1304485888), // LD3Rv16b_POST |
| 2750 | UINT64_C(222358528), // LD3Rv1d |
| 2751 | UINT64_C(230747136), // LD3Rv1d_POST |
| 2752 | UINT64_C(1296100352), // LD3Rv2d |
| 2753 | UINT64_C(1304488960), // LD3Rv2d_POST |
| 2754 | UINT64_C(222357504), // LD3Rv2s |
| 2755 | UINT64_C(230746112), // LD3Rv2s_POST |
| 2756 | UINT64_C(222356480), // LD3Rv4h |
| 2757 | UINT64_C(230745088), // LD3Rv4h_POST |
| 2758 | UINT64_C(1296099328), // LD3Rv4s |
| 2759 | UINT64_C(1304487936), // LD3Rv4s_POST |
| 2760 | UINT64_C(222355456), // LD3Rv8b |
| 2761 | UINT64_C(230744064), // LD3Rv8b_POST |
| 2762 | UINT64_C(1296098304), // LD3Rv8h |
| 2763 | UINT64_C(1304486912), // LD3Rv8h_POST |
| 2764 | UINT64_C(1279279104), // LD3Threev16b |
| 2765 | UINT64_C(1287667712), // LD3Threev16b_POST |
| 2766 | UINT64_C(1279282176), // LD3Threev2d |
| 2767 | UINT64_C(1287670784), // LD3Threev2d_POST |
| 2768 | UINT64_C(205539328), // LD3Threev2s |
| 2769 | UINT64_C(213927936), // LD3Threev2s_POST |
| 2770 | UINT64_C(205538304), // LD3Threev4h |
| 2771 | UINT64_C(213926912), // LD3Threev4h_POST |
| 2772 | UINT64_C(1279281152), // LD3Threev4s |
| 2773 | UINT64_C(1287669760), // LD3Threev4s_POST |
| 2774 | UINT64_C(205537280), // LD3Threev8b |
| 2775 | UINT64_C(213925888), // LD3Threev8b_POST |
| 2776 | UINT64_C(1279280128), // LD3Threev8h |
| 2777 | UINT64_C(1287668736), // LD3Threev8h_POST |
| 2778 | UINT64_C(2772484096), // LD3W |
| 2779 | UINT64_C(2772492288), // LD3W_IMM |
| 2780 | UINT64_C(222322688), // LD3i16 |
| 2781 | UINT64_C(230711296), // LD3i16_POST |
| 2782 | UINT64_C(222339072), // LD3i32 |
| 2783 | UINT64_C(230727680), // LD3i32_POST |
| 2784 | UINT64_C(222340096), // LD3i64 |
| 2785 | UINT64_C(230728704), // LD3i64_POST |
| 2786 | UINT64_C(222306304), // LD3i8 |
| 2787 | UINT64_C(230694912), // LD3i8_POST |
| 2788 | UINT64_C(2757804032), // LD4B |
| 2789 | UINT64_C(2757812224), // LD4B_IMM |
| 2790 | UINT64_C(2782969856), // LD4D |
| 2791 | UINT64_C(2782978048), // LD4D_IMM |
| 2792 | UINT64_C(1279262720), // LD4Fourv16b |
| 2793 | UINT64_C(1287651328), // LD4Fourv16b_POST |
| 2794 | UINT64_C(1279265792), // LD4Fourv2d |
| 2795 | UINT64_C(1287654400), // LD4Fourv2d_POST |
| 2796 | UINT64_C(205522944), // LD4Fourv2s |
| 2797 | UINT64_C(213911552), // LD4Fourv2s_POST |
| 2798 | UINT64_C(205521920), // LD4Fourv4h |
| 2799 | UINT64_C(213910528), // LD4Fourv4h_POST |
| 2800 | UINT64_C(1279264768), // LD4Fourv4s |
| 2801 | UINT64_C(1287653376), // LD4Fourv4s_POST |
| 2802 | UINT64_C(205520896), // LD4Fourv8b |
| 2803 | UINT64_C(213909504), // LD4Fourv8b_POST |
| 2804 | UINT64_C(1279263744), // LD4Fourv8h |
| 2805 | UINT64_C(1287652352), // LD4Fourv8h_POST |
| 2806 | UINT64_C(2766192640), // LD4H |
| 2807 | UINT64_C(2766200832), // LD4H_IMM |
| 2808 | UINT64_C(1298194432), // LD4Rv16b |
| 2809 | UINT64_C(1306583040), // LD4Rv16b_POST |
| 2810 | UINT64_C(224455680), // LD4Rv1d |
| 2811 | UINT64_C(232844288), // LD4Rv1d_POST |
| 2812 | UINT64_C(1298197504), // LD4Rv2d |
| 2813 | UINT64_C(1306586112), // LD4Rv2d_POST |
| 2814 | UINT64_C(224454656), // LD4Rv2s |
| 2815 | UINT64_C(232843264), // LD4Rv2s_POST |
| 2816 | UINT64_C(224453632), // LD4Rv4h |
| 2817 | UINT64_C(232842240), // LD4Rv4h_POST |
| 2818 | UINT64_C(1298196480), // LD4Rv4s |
| 2819 | UINT64_C(1306585088), // LD4Rv4s_POST |
| 2820 | UINT64_C(224452608), // LD4Rv8b |
| 2821 | UINT64_C(232841216), // LD4Rv8b_POST |
| 2822 | UINT64_C(1298195456), // LD4Rv8h |
| 2823 | UINT64_C(1306584064), // LD4Rv8h_POST |
| 2824 | UINT64_C(2774581248), // LD4W |
| 2825 | UINT64_C(2774589440), // LD4W_IMM |
| 2826 | UINT64_C(224419840), // LD4i16 |
| 2827 | UINT64_C(232808448), // LD4i16_POST |
| 2828 | UINT64_C(224436224), // LD4i32 |
| 2829 | UINT64_C(232824832), // LD4i32_POST |
| 2830 | UINT64_C(224437248), // LD4i64 |
| 2831 | UINT64_C(232825856), // LD4i64_POST |
| 2832 | UINT64_C(224403456), // LD4i8 |
| 2833 | UINT64_C(232792064), // LD4i8_POST |
| 2834 | UINT64_C(4164931584), // LD64B |
| 2835 | UINT64_C(950009856), // LDADDAB |
| 2836 | UINT64_C(2023751680), // LDADDAH |
| 2837 | UINT64_C(954204160), // LDADDALB |
| 2838 | UINT64_C(2027945984), // LDADDALH |
| 2839 | UINT64_C(3101687808), // LDADDALW |
| 2840 | UINT64_C(4175429632), // LDADDALX |
| 2841 | UINT64_C(3097493504), // LDADDAW |
| 2842 | UINT64_C(4171235328), // LDADDAX |
| 2843 | UINT64_C(941621248), // LDADDB |
| 2844 | UINT64_C(2015363072), // LDADDH |
| 2845 | UINT64_C(945815552), // LDADDLB |
| 2846 | UINT64_C(2019557376), // LDADDLH |
| 2847 | UINT64_C(3093299200), // LDADDLW |
| 2848 | UINT64_C(4167041024), // LDADDLX |
| 2849 | UINT64_C(3089104896), // LDADDW |
| 2850 | UINT64_C(4162846720), // LDADDX |
| 2851 | UINT64_C(952090624), // LDAPRB |
| 2852 | UINT64_C(2025832448), // LDAPRH |
| 2853 | UINT64_C(3099574272), // LDAPRW |
| 2854 | UINT64_C(4173316096), // LDAPRX |
| 2855 | UINT64_C(423624704), // LDAPURBi |
| 2856 | UINT64_C(1497366528), // LDAPURHi |
| 2857 | UINT64_C(432013312), // LDAPURSBWi |
| 2858 | UINT64_C(427819008), // LDAPURSBXi |
| 2859 | UINT64_C(1505755136), // LDAPURSHWi |
| 2860 | UINT64_C(1501560832), // LDAPURSHXi |
| 2861 | UINT64_C(2575302656), // LDAPURSWi |
| 2862 | UINT64_C(3644850176), // LDAPURXi |
| 2863 | UINT64_C(2571108352), // LDAPURi |
| 2864 | UINT64_C(148896768), // LDARB |
| 2865 | UINT64_C(1222638592), // LDARH |
| 2866 | UINT64_C(2296380416), // LDARW |
| 2867 | UINT64_C(3370122240), // LDARX |
| 2868 | UINT64_C(2288025600), // LDAXPW |
| 2869 | UINT64_C(3361767424), // LDAXPX |
| 2870 | UINT64_C(140508160), // LDAXRB |
| 2871 | UINT64_C(1214249984), // LDAXRH |
| 2872 | UINT64_C(2287991808), // LDAXRW |
| 2873 | UINT64_C(3361733632), // LDAXRX |
| 2874 | UINT64_C(950013952), // LDCLRAB |
| 2875 | UINT64_C(2023755776), // LDCLRAH |
| 2876 | UINT64_C(954208256), // LDCLRALB |
| 2877 | UINT64_C(2027950080), // LDCLRALH |
| 2878 | UINT64_C(3101691904), // LDCLRALW |
| 2879 | UINT64_C(4175433728), // LDCLRALX |
| 2880 | UINT64_C(3097497600), // LDCLRAW |
| 2881 | UINT64_C(4171239424), // LDCLRAX |
| 2882 | UINT64_C(941625344), // LDCLRB |
| 2883 | UINT64_C(2015367168), // LDCLRH |
| 2884 | UINT64_C(945819648), // LDCLRLB |
| 2885 | UINT64_C(2019561472), // LDCLRLH |
| 2886 | UINT64_C(3093303296), // LDCLRLW |
| 2887 | UINT64_C(4167045120), // LDCLRLX |
| 2888 | UINT64_C(3089108992), // LDCLRW |
| 2889 | UINT64_C(4162850816), // LDCLRX |
| 2890 | UINT64_C(950018048), // LDEORAB |
| 2891 | UINT64_C(2023759872), // LDEORAH |
| 2892 | UINT64_C(954212352), // LDEORALB |
| 2893 | UINT64_C(2027954176), // LDEORALH |
| 2894 | UINT64_C(3101696000), // LDEORALW |
| 2895 | UINT64_C(4175437824), // LDEORALX |
| 2896 | UINT64_C(3097501696), // LDEORAW |
| 2897 | UINT64_C(4171243520), // LDEORAX |
| 2898 | UINT64_C(941629440), // LDEORB |
| 2899 | UINT64_C(2015371264), // LDEORH |
| 2900 | UINT64_C(945823744), // LDEORLB |
| 2901 | UINT64_C(2019565568), // LDEORLH |
| 2902 | UINT64_C(3093307392), // LDEORLW |
| 2903 | UINT64_C(4167049216), // LDEORLX |
| 2904 | UINT64_C(3089113088), // LDEORW |
| 2905 | UINT64_C(4162854912), // LDEORX |
| 2906 | UINT64_C(2757779456), // LDFF1B_D_REAL |
| 2907 | UINT64_C(2753585152), // LDFF1B_H_REAL |
| 2908 | UINT64_C(2751488000), // LDFF1B_REAL |
| 2909 | UINT64_C(2755682304), // LDFF1B_S_REAL |
| 2910 | UINT64_C(2782945280), // LDFF1D_REAL |
| 2911 | UINT64_C(2766168064), // LDFF1H_D_REAL |
| 2912 | UINT64_C(2761973760), // LDFF1H_REAL |
| 2913 | UINT64_C(2764070912), // LDFF1H_S_REAL |
| 2914 | UINT64_C(2776653824), // LDFF1SB_D_REAL |
| 2915 | UINT64_C(2780848128), // LDFF1SB_H_REAL |
| 2916 | UINT64_C(2778750976), // LDFF1SB_S_REAL |
| 2917 | UINT64_C(2768265216), // LDFF1SH_D_REAL |
| 2918 | UINT64_C(2770362368), // LDFF1SH_S_REAL |
| 2919 | UINT64_C(2759876608), // LDFF1SW_D_REAL |
| 2920 | UINT64_C(2774556672), // LDFF1W_D_REAL |
| 2921 | UINT64_C(2772459520), // LDFF1W_REAL |
| 2922 | UINT64_C(3646947328), // LDG |
| 2923 | UINT64_C(3655335936), // LDGM |
| 2924 | UINT64_C(148864000), // LDLARB |
| 2925 | UINT64_C(1222605824), // LDLARH |
| 2926 | UINT64_C(2296347648), // LDLARW |
| 2927 | UINT64_C(3370089472), // LDLARX |
| 2928 | UINT64_C(2758844416), // LDNF1B_D_IMM_REAL |
| 2929 | UINT64_C(2754650112), // LDNF1B_H_IMM_REAL |
| 2930 | UINT64_C(2752552960), // LDNF1B_IMM_REAL |
| 2931 | UINT64_C(2756747264), // LDNF1B_S_IMM_REAL |
| 2932 | UINT64_C(2784010240), // LDNF1D_IMM_REAL |
| 2933 | UINT64_C(2767233024), // LDNF1H_D_IMM_REAL |
| 2934 | UINT64_C(2763038720), // LDNF1H_IMM_REAL |
| 2935 | UINT64_C(2765135872), // LDNF1H_S_IMM_REAL |
| 2936 | UINT64_C(2777718784), // LDNF1SB_D_IMM_REAL |
| 2937 | UINT64_C(2781913088), // LDNF1SB_H_IMM_REAL |
| 2938 | UINT64_C(2779815936), // LDNF1SB_S_IMM_REAL |
| 2939 | UINT64_C(2769330176), // LDNF1SH_D_IMM_REAL |
| 2940 | UINT64_C(2771427328), // LDNF1SH_S_IMM_REAL |
| 2941 | UINT64_C(2760941568), // LDNF1SW_D_IMM_REAL |
| 2942 | UINT64_C(2775621632), // LDNF1W_D_IMM_REAL |
| 2943 | UINT64_C(2773524480), // LDNF1W_IMM_REAL |
| 2944 | UINT64_C(1816133632), // LDNPDi |
| 2945 | UINT64_C(2889875456), // LDNPQi |
| 2946 | UINT64_C(742391808), // LDNPSi |
| 2947 | UINT64_C(675282944), // LDNPWi |
| 2948 | UINT64_C(2822766592), // LDNPXi |
| 2949 | UINT64_C(2751520768), // LDNT1B_ZRI |
| 2950 | UINT64_C(2751512576), // LDNT1B_ZRR |
| 2951 | UINT64_C(3288383488), // LDNT1B_ZZR_D_REAL |
| 2952 | UINT64_C(2214633472), // LDNT1B_ZZR_S_REAL |
| 2953 | UINT64_C(2776686592), // LDNT1D_ZRI |
| 2954 | UINT64_C(2776678400), // LDNT1D_ZRR |
| 2955 | UINT64_C(3313549312), // LDNT1D_ZZR_D_REAL |
| 2956 | UINT64_C(2759909376), // LDNT1H_ZRI |
| 2957 | UINT64_C(2759901184), // LDNT1H_ZRR |
| 2958 | UINT64_C(3296772096), // LDNT1H_ZZR_D_REAL |
| 2959 | UINT64_C(2223022080), // LDNT1H_ZZR_S_REAL |
| 2960 | UINT64_C(3288367104), // LDNT1SB_ZZR_D_REAL |
| 2961 | UINT64_C(2214625280), // LDNT1SB_ZZR_S_REAL |
| 2962 | UINT64_C(3296755712), // LDNT1SH_ZZR_D_REAL |
| 2963 | UINT64_C(2223013888), // LDNT1SH_ZZR_S_REAL |
| 2964 | UINT64_C(3305144320), // LDNT1SW_ZZR_D_REAL |
| 2965 | UINT64_C(2768297984), // LDNT1W_ZRI |
| 2966 | UINT64_C(2768289792), // LDNT1W_ZRR |
| 2967 | UINT64_C(3305160704), // LDNT1W_ZZR_D_REAL |
| 2968 | UINT64_C(2231410688), // LDNT1W_ZZR_S_REAL |
| 2969 | UINT64_C(1832910848), // LDPDi |
| 2970 | UINT64_C(1824522240), // LDPDpost |
| 2971 | UINT64_C(1841299456), // LDPDpre |
| 2972 | UINT64_C(2906652672), // LDPQi |
| 2973 | UINT64_C(2898264064), // LDPQpost |
| 2974 | UINT64_C(2915041280), // LDPQpre |
| 2975 | UINT64_C(1765801984), // LDPSWi |
| 2976 | UINT64_C(1757413376), // LDPSWpost |
| 2977 | UINT64_C(1774190592), // LDPSWpre |
| 2978 | UINT64_C(759169024), // LDPSi |
| 2979 | UINT64_C(750780416), // LDPSpost |
| 2980 | UINT64_C(767557632), // LDPSpre |
| 2981 | UINT64_C(692060160), // LDPWi |
| 2982 | UINT64_C(683671552), // LDPWpost |
| 2983 | UINT64_C(700448768), // LDPWpre |
| 2984 | UINT64_C(2839543808), // LDPXi |
| 2985 | UINT64_C(2831155200), // LDPXpost |
| 2986 | UINT64_C(2847932416), // LDPXpre |
| 2987 | UINT64_C(4162847744), // LDRAAindexed |
| 2988 | UINT64_C(4162849792), // LDRAAwriteback |
| 2989 | UINT64_C(4171236352), // LDRABindexed |
| 2990 | UINT64_C(4171238400), // LDRABwriteback |
| 2991 | UINT64_C(943719424), // LDRBBpost |
| 2992 | UINT64_C(943721472), // LDRBBpre |
| 2993 | UINT64_C(945833984), // LDRBBroW |
| 2994 | UINT64_C(945842176), // LDRBBroX |
| 2995 | UINT64_C(960495616), // LDRBBui |
| 2996 | UINT64_C(1010828288), // LDRBpost |
| 2997 | UINT64_C(1010830336), // LDRBpre |
| 2998 | UINT64_C(1012942848), // LDRBroW |
| 2999 | UINT64_C(1012951040), // LDRBroX |
| 3000 | UINT64_C(1027604480), // LDRBui |
| 3001 | UINT64_C(1543503872), // LDRDl |
| 3002 | UINT64_C(4232053760), // LDRDpost |
| 3003 | UINT64_C(4232055808), // LDRDpre |
| 3004 | UINT64_C(4234168320), // LDRDroW |
| 3005 | UINT64_C(4234176512), // LDRDroX |
| 3006 | UINT64_C(4248829952), // LDRDui |
| 3007 | UINT64_C(2017461248), // LDRHHpost |
| 3008 | UINT64_C(2017463296), // LDRHHpre |
| 3009 | UINT64_C(2019575808), // LDRHHroW |
| 3010 | UINT64_C(2019584000), // LDRHHroX |
| 3011 | UINT64_C(2034237440), // LDRHHui |
| 3012 | UINT64_C(2084570112), // LDRHpost |
| 3013 | UINT64_C(2084572160), // LDRHpre |
| 3014 | UINT64_C(2086684672), // LDRHroW |
| 3015 | UINT64_C(2086692864), // LDRHroX |
| 3016 | UINT64_C(2101346304), // LDRHui |
| 3017 | UINT64_C(2617245696), // LDRQl |
| 3018 | UINT64_C(1019216896), // LDRQpost |
| 3019 | UINT64_C(1019218944), // LDRQpre |
| 3020 | UINT64_C(1021331456), // LDRQroW |
| 3021 | UINT64_C(1021339648), // LDRQroX |
| 3022 | UINT64_C(1035993088), // LDRQui |
| 3023 | UINT64_C(952108032), // LDRSBWpost |
| 3024 | UINT64_C(952110080), // LDRSBWpre |
| 3025 | UINT64_C(954222592), // LDRSBWroW |
| 3026 | UINT64_C(954230784), // LDRSBWroX |
| 3027 | UINT64_C(968884224), // LDRSBWui |
| 3028 | UINT64_C(947913728), // LDRSBXpost |
| 3029 | UINT64_C(947915776), // LDRSBXpre |
| 3030 | UINT64_C(950028288), // LDRSBXroW |
| 3031 | UINT64_C(950036480), // LDRSBXroX |
| 3032 | UINT64_C(964689920), // LDRSBXui |
| 3033 | UINT64_C(2025849856), // LDRSHWpost |
| 3034 | UINT64_C(2025851904), // LDRSHWpre |
| 3035 | UINT64_C(2027964416), // LDRSHWroW |
| 3036 | UINT64_C(2027972608), // LDRSHWroX |
| 3037 | UINT64_C(2042626048), // LDRSHWui |
| 3038 | UINT64_C(2021655552), // LDRSHXpost |
| 3039 | UINT64_C(2021657600), // LDRSHXpre |
| 3040 | UINT64_C(2023770112), // LDRSHXroW |
| 3041 | UINT64_C(2023778304), // LDRSHXroX |
| 3042 | UINT64_C(2038431744), // LDRSHXui |
| 3043 | UINT64_C(2550136832), // LDRSWl |
| 3044 | UINT64_C(3095397376), // LDRSWpost |
| 3045 | UINT64_C(3095399424), // LDRSWpre |
| 3046 | UINT64_C(3097511936), // LDRSWroW |
| 3047 | UINT64_C(3097520128), // LDRSWroX |
| 3048 | UINT64_C(3112173568), // LDRSWui |
| 3049 | UINT64_C(469762048), // LDRSl |
| 3050 | UINT64_C(3158311936), // LDRSpost |
| 3051 | UINT64_C(3158313984), // LDRSpre |
| 3052 | UINT64_C(3160426496), // LDRSroW |
| 3053 | UINT64_C(3160434688), // LDRSroX |
| 3054 | UINT64_C(3175088128), // LDRSui |
| 3055 | UINT64_C(402653184), // LDRWl |
| 3056 | UINT64_C(3091203072), // LDRWpost |
| 3057 | UINT64_C(3091205120), // LDRWpre |
| 3058 | UINT64_C(3093317632), // LDRWroW |
| 3059 | UINT64_C(3093325824), // LDRWroX |
| 3060 | UINT64_C(3107979264), // LDRWui |
| 3061 | UINT64_C(1476395008), // LDRXl |
| 3062 | UINT64_C(4164944896), // LDRXpost |
| 3063 | UINT64_C(4164946944), // LDRXpre |
| 3064 | UINT64_C(4167059456), // LDRXroW |
| 3065 | UINT64_C(4167067648), // LDRXroX |
| 3066 | UINT64_C(4181721088), // LDRXui |
| 3067 | UINT64_C(2239758336), // LDR_PXI |
| 3068 | UINT64_C(2239774720), // LDR_ZXI |
| 3069 | UINT64_C(950022144), // LDSETAB |
| 3070 | UINT64_C(2023763968), // LDSETAH |
| 3071 | UINT64_C(954216448), // LDSETALB |
| 3072 | UINT64_C(2027958272), // LDSETALH |
| 3073 | UINT64_C(3101700096), // LDSETALW |
| 3074 | UINT64_C(4175441920), // LDSETALX |
| 3075 | UINT64_C(3097505792), // LDSETAW |
| 3076 | UINT64_C(4171247616), // LDSETAX |
| 3077 | UINT64_C(941633536), // LDSETB |
| 3078 | UINT64_C(2015375360), // LDSETH |
| 3079 | UINT64_C(945827840), // LDSETLB |
| 3080 | UINT64_C(2019569664), // LDSETLH |
| 3081 | UINT64_C(3093311488), // LDSETLW |
| 3082 | UINT64_C(4167053312), // LDSETLX |
| 3083 | UINT64_C(3089117184), // LDSETW |
| 3084 | UINT64_C(4162859008), // LDSETX |
| 3085 | UINT64_C(950026240), // LDSMAXAB |
| 3086 | UINT64_C(2023768064), // LDSMAXAH |
| 3087 | UINT64_C(954220544), // LDSMAXALB |
| 3088 | UINT64_C(2027962368), // LDSMAXALH |
| 3089 | UINT64_C(3101704192), // LDSMAXALW |
| 3090 | UINT64_C(4175446016), // LDSMAXALX |
| 3091 | UINT64_C(3097509888), // LDSMAXAW |
| 3092 | UINT64_C(4171251712), // LDSMAXAX |
| 3093 | UINT64_C(941637632), // LDSMAXB |
| 3094 | UINT64_C(2015379456), // LDSMAXH |
| 3095 | UINT64_C(945831936), // LDSMAXLB |
| 3096 | UINT64_C(2019573760), // LDSMAXLH |
| 3097 | UINT64_C(3093315584), // LDSMAXLW |
| 3098 | UINT64_C(4167057408), // LDSMAXLX |
| 3099 | UINT64_C(3089121280), // LDSMAXW |
| 3100 | UINT64_C(4162863104), // LDSMAXX |
| 3101 | UINT64_C(950030336), // LDSMINAB |
| 3102 | UINT64_C(2023772160), // LDSMINAH |
| 3103 | UINT64_C(954224640), // LDSMINALB |
| 3104 | UINT64_C(2027966464), // LDSMINALH |
| 3105 | UINT64_C(3101708288), // LDSMINALW |
| 3106 | UINT64_C(4175450112), // LDSMINALX |
| 3107 | UINT64_C(3097513984), // LDSMINAW |
| 3108 | UINT64_C(4171255808), // LDSMINAX |
| 3109 | UINT64_C(941641728), // LDSMINB |
| 3110 | UINT64_C(2015383552), // LDSMINH |
| 3111 | UINT64_C(945836032), // LDSMINLB |
| 3112 | UINT64_C(2019577856), // LDSMINLH |
| 3113 | UINT64_C(3093319680), // LDSMINLW |
| 3114 | UINT64_C(4167061504), // LDSMINLX |
| 3115 | UINT64_C(3089125376), // LDSMINW |
| 3116 | UINT64_C(4162867200), // LDSMINX |
| 3117 | UINT64_C(943720448), // LDTRBi |
| 3118 | UINT64_C(2017462272), // LDTRHi |
| 3119 | UINT64_C(952109056), // LDTRSBWi |
| 3120 | UINT64_C(947914752), // LDTRSBXi |
| 3121 | UINT64_C(2025850880), // LDTRSHWi |
| 3122 | UINT64_C(2021656576), // LDTRSHXi |
| 3123 | UINT64_C(3095398400), // LDTRSWi |
| 3124 | UINT64_C(3091204096), // LDTRWi |
| 3125 | UINT64_C(4164945920), // LDTRXi |
| 3126 | UINT64_C(950034432), // LDUMAXAB |
| 3127 | UINT64_C(2023776256), // LDUMAXAH |
| 3128 | UINT64_C(954228736), // LDUMAXALB |
| 3129 | UINT64_C(2027970560), // LDUMAXALH |
| 3130 | UINT64_C(3101712384), // LDUMAXALW |
| 3131 | UINT64_C(4175454208), // LDUMAXALX |
| 3132 | UINT64_C(3097518080), // LDUMAXAW |
| 3133 | UINT64_C(4171259904), // LDUMAXAX |
| 3134 | UINT64_C(941645824), // LDUMAXB |
| 3135 | UINT64_C(2015387648), // LDUMAXH |
| 3136 | UINT64_C(945840128), // LDUMAXLB |
| 3137 | UINT64_C(2019581952), // LDUMAXLH |
| 3138 | UINT64_C(3093323776), // LDUMAXLW |
| 3139 | UINT64_C(4167065600), // LDUMAXLX |
| 3140 | UINT64_C(3089129472), // LDUMAXW |
| 3141 | UINT64_C(4162871296), // LDUMAXX |
| 3142 | UINT64_C(950038528), // LDUMINAB |
| 3143 | UINT64_C(2023780352), // LDUMINAH |
| 3144 | UINT64_C(954232832), // LDUMINALB |
| 3145 | UINT64_C(2027974656), // LDUMINALH |
| 3146 | UINT64_C(3101716480), // LDUMINALW |
| 3147 | UINT64_C(4175458304), // LDUMINALX |
| 3148 | UINT64_C(3097522176), // LDUMINAW |
| 3149 | UINT64_C(4171264000), // LDUMINAX |
| 3150 | UINT64_C(941649920), // LDUMINB |
| 3151 | UINT64_C(2015391744), // LDUMINH |
| 3152 | UINT64_C(945844224), // LDUMINLB |
| 3153 | UINT64_C(2019586048), // LDUMINLH |
| 3154 | UINT64_C(3093327872), // LDUMINLW |
| 3155 | UINT64_C(4167069696), // LDUMINLX |
| 3156 | UINT64_C(3089133568), // LDUMINW |
| 3157 | UINT64_C(4162875392), // LDUMINX |
| 3158 | UINT64_C(943718400), // LDURBBi |
| 3159 | UINT64_C(1010827264), // LDURBi |
| 3160 | UINT64_C(4232052736), // LDURDi |
| 3161 | UINT64_C(2017460224), // LDURHHi |
| 3162 | UINT64_C(2084569088), // LDURHi |
| 3163 | UINT64_C(1019215872), // LDURQi |
| 3164 | UINT64_C(952107008), // LDURSBWi |
| 3165 | UINT64_C(947912704), // LDURSBXi |
| 3166 | UINT64_C(2025848832), // LDURSHWi |
| 3167 | UINT64_C(2021654528), // LDURSHXi |
| 3168 | UINT64_C(3095396352), // LDURSWi |
| 3169 | UINT64_C(3158310912), // LDURSi |
| 3170 | UINT64_C(3091202048), // LDURWi |
| 3171 | UINT64_C(4164943872), // LDURXi |
| 3172 | UINT64_C(2287992832), // LDXPW |
| 3173 | UINT64_C(3361734656), // LDXPX |
| 3174 | UINT64_C(140475392), // LDXRB |
| 3175 | UINT64_C(1214217216), // LDXRH |
| 3176 | UINT64_C(2287959040), // LDXRW |
| 3177 | UINT64_C(3361700864), // LDXRX |
| 3178 | UINT64_C(68648960), // LSLR_ZPmZ_B |
| 3179 | UINT64_C(81231872), // LSLR_ZPmZ_D |
| 3180 | UINT64_C(72843264), // LSLR_ZPmZ_H |
| 3181 | UINT64_C(77037568), // LSLR_ZPmZ_S |
| 3182 | UINT64_C(448798720), // LSLVWr |
| 3183 | UINT64_C(2596282368), // LSLVXr |
| 3184 | UINT64_C(68911104), // LSL_WIDE_ZPmZ_B |
| 3185 | UINT64_C(73105408), // LSL_WIDE_ZPmZ_H |
| 3186 | UINT64_C(77299712), // LSL_WIDE_ZPmZ_S |
| 3187 | UINT64_C(69241856), // LSL_WIDE_ZZZ_B |
| 3188 | UINT64_C(73436160), // LSL_WIDE_ZZZ_H |
| 3189 | UINT64_C(77630464), // LSL_WIDE_ZZZ_S |
| 3190 | UINT64_C(67338496), // LSL_ZPmI_B |
| 3191 | UINT64_C(75726848), // LSL_ZPmI_D |
| 3192 | UINT64_C(67338752), // LSL_ZPmI_H |
| 3193 | UINT64_C(71532544), // LSL_ZPmI_S |
| 3194 | UINT64_C(68386816), // LSL_ZPmZ_B |
| 3195 | UINT64_C(80969728), // LSL_ZPmZ_D |
| 3196 | UINT64_C(72581120), // LSL_ZPmZ_H |
| 3197 | UINT64_C(76775424), // LSL_ZPmZ_S |
| 3198 | UINT64_C(69770240), // LSL_ZZI_B |
| 3199 | UINT64_C(77634560), // LSL_ZZI_D |
| 3200 | UINT64_C(70294528), // LSL_ZZI_H |
| 3201 | UINT64_C(73440256), // LSL_ZZI_S |
| 3202 | UINT64_C(68517888), // LSRR_ZPmZ_B |
| 3203 | UINT64_C(81100800), // LSRR_ZPmZ_D |
| 3204 | UINT64_C(72712192), // LSRR_ZPmZ_H |
| 3205 | UINT64_C(76906496), // LSRR_ZPmZ_S |
| 3206 | UINT64_C(448799744), // LSRVWr |
| 3207 | UINT64_C(2596283392), // LSRVXr |
| 3208 | UINT64_C(68780032), // LSR_WIDE_ZPmZ_B |
| 3209 | UINT64_C(72974336), // LSR_WIDE_ZPmZ_H |
| 3210 | UINT64_C(77168640), // LSR_WIDE_ZPmZ_S |
| 3211 | UINT64_C(69239808), // LSR_WIDE_ZZZ_B |
| 3212 | UINT64_C(73434112), // LSR_WIDE_ZZZ_H |
| 3213 | UINT64_C(77628416), // LSR_WIDE_ZZZ_S |
| 3214 | UINT64_C(67207424), // LSR_ZPmI_B |
| 3215 | UINT64_C(75595776), // LSR_ZPmI_D |
| 3216 | UINT64_C(67207680), // LSR_ZPmI_H |
| 3217 | UINT64_C(71401472), // LSR_ZPmI_S |
| 3218 | UINT64_C(68255744), // LSR_ZPmZ_B |
| 3219 | UINT64_C(80838656), // LSR_ZPmZ_D |
| 3220 | UINT64_C(72450048), // LSR_ZPmZ_H |
| 3221 | UINT64_C(76644352), // LSR_ZPmZ_S |
| 3222 | UINT64_C(69768192), // LSR_ZZI_B |
| 3223 | UINT64_C(77632512), // LSR_ZZI_D |
| 3224 | UINT64_C(70292480), // LSR_ZZI_H |
| 3225 | UINT64_C(73438208), // LSR_ZZI_S |
| 3226 | UINT64_C(452984832), // MADDWrrr |
| 3227 | UINT64_C(2600468480), // MADDXrrr |
| 3228 | UINT64_C(67158016), // MAD_ZPmZZ_B |
| 3229 | UINT64_C(79740928), // MAD_ZPmZZ_D |
| 3230 | UINT64_C(71352320), // MAD_ZPmZZ_H |
| 3231 | UINT64_C(75546624), // MAD_ZPmZZ_S |
| 3232 | UINT64_C(1159757824), // MATCH_PPzZZ_B |
| 3233 | UINT64_C(1163952128), // MATCH_PPzZZ_H |
| 3234 | UINT64_C(67125248), // MLA_ZPmZZ_B |
| 3235 | UINT64_C(79708160), // MLA_ZPmZZ_D |
| 3236 | UINT64_C(71319552), // MLA_ZPmZZ_H |
| 3237 | UINT64_C(75513856), // MLA_ZPmZZ_S |
| 3238 | UINT64_C(1155532800), // MLA_ZZZI_D |
| 3239 | UINT64_C(1142949888), // MLA_ZZZI_H |
| 3240 | UINT64_C(1151338496), // MLA_ZZZI_S |
| 3241 | UINT64_C(1310757888), // MLAv16i8 |
| 3242 | UINT64_C(245404672), // MLAv2i32 |
| 3243 | UINT64_C(796917760), // MLAv2i32_indexed |
| 3244 | UINT64_C(241210368), // MLAv4i16 |
| 3245 | UINT64_C(792723456), // MLAv4i16_indexed |
| 3246 | UINT64_C(1319146496), // MLAv4i32 |
| 3247 | UINT64_C(1870659584), // MLAv4i32_indexed |
| 3248 | UINT64_C(1314952192), // MLAv8i16 |
| 3249 | UINT64_C(1866465280), // MLAv8i16_indexed |
| 3250 | UINT64_C(237016064), // MLAv8i8 |
| 3251 | UINT64_C(67133440), // MLS_ZPmZZ_B |
| 3252 | UINT64_C(79716352), // MLS_ZPmZZ_D |
| 3253 | UINT64_C(71327744), // MLS_ZPmZZ_H |
| 3254 | UINT64_C(75522048), // MLS_ZPmZZ_S |
| 3255 | UINT64_C(1155533824), // MLS_ZZZI_D |
| 3256 | UINT64_C(1142950912), // MLS_ZZZI_H |
| 3257 | UINT64_C(1151339520), // MLS_ZZZI_S |
| 3258 | UINT64_C(1847628800), // MLSv16i8 |
| 3259 | UINT64_C(782275584), // MLSv2i32 |
| 3260 | UINT64_C(796934144), // MLSv2i32_indexed |
| 3261 | UINT64_C(778081280), // MLSv4i16 |
| 3262 | UINT64_C(792739840), // MLSv4i16_indexed |
| 3263 | UINT64_C(1856017408), // MLSv4i32 |
| 3264 | UINT64_C(1870675968), // MLSv4i32_indexed |
| 3265 | UINT64_C(1851823104), // MLSv8i16 |
| 3266 | UINT64_C(1866481664), // MLSv8i16_indexed |
| 3267 | UINT64_C(773886976), // MLSv8i8 |
| 3268 | UINT64_C(788587520), // MOVID |
| 3269 | UINT64_C(1325458432), // MOVIv16b_ns |
| 3270 | UINT64_C(1862329344), // MOVIv2d_ns |
| 3271 | UINT64_C(251659264), // MOVIv2i32 |
| 3272 | UINT64_C(251708416), // MOVIv2s_msl |
| 3273 | UINT64_C(251692032), // MOVIv4i16 |
| 3274 | UINT64_C(1325401088), // MOVIv4i32 |
| 3275 | UINT64_C(1325450240), // MOVIv4s_msl |
| 3276 | UINT64_C(251716608), // MOVIv8b_ns |
| 3277 | UINT64_C(1325433856), // MOVIv8i16 |
| 3278 | UINT64_C(1920991232), // MOVKWi |
| 3279 | UINT64_C(4068474880), // MOVKXi |
| 3280 | UINT64_C(310378496), // MOVNWi |
| 3281 | UINT64_C(2457862144), // MOVNXi |
| 3282 | UINT64_C(68231168), // MOVPRFX_ZPmZ_B |
| 3283 | UINT64_C(80814080), // MOVPRFX_ZPmZ_D |
| 3284 | UINT64_C(72425472), // MOVPRFX_ZPmZ_H |
| 3285 | UINT64_C(76619776), // MOVPRFX_ZPmZ_S |
| 3286 | UINT64_C(68165632), // MOVPRFX_ZPzZ_B |
| 3287 | UINT64_C(80748544), // MOVPRFX_ZPzZ_D |
| 3288 | UINT64_C(72359936), // MOVPRFX_ZPzZ_H |
| 3289 | UINT64_C(76554240), // MOVPRFX_ZPzZ_S |
| 3290 | UINT64_C(69254144), // MOVPRFX_ZZ |
| 3291 | UINT64_C(1384120320), // MOVZWi |
| 3292 | UINT64_C(3531603968), // MOVZXi |
| 3293 | UINT64_C(3575644160), // MRS |
| 3294 | UINT64_C(67166208), // MSB_ZPmZZ_B |
| 3295 | UINT64_C(79749120), // MSB_ZPmZZ_D |
| 3296 | UINT64_C(71360512), // MSB_ZPmZZ_H |
| 3297 | UINT64_C(75554816), // MSB_ZPmZZ_S |
| 3298 | UINT64_C(3573547008), // MSR |
| 3299 | UINT64_C(3573563423), // MSRpstateImm1 |
| 3300 | UINT64_C(3573563423), // MSRpstateImm4 |
| 3301 | UINT64_C(453017600), // MSUBWrrr |
| 3302 | UINT64_C(2600501248), // MSUBXrrr |
| 3303 | UINT64_C(623951872), // MUL_ZI_B |
| 3304 | UINT64_C(636534784), // MUL_ZI_D |
| 3305 | UINT64_C(628146176), // MUL_ZI_H |
| 3306 | UINT64_C(632340480), // MUL_ZI_S |
| 3307 | UINT64_C(68157440), // MUL_ZPmZ_B |
| 3308 | UINT64_C(80740352), // MUL_ZPmZ_D |
| 3309 | UINT64_C(72351744), // MUL_ZPmZ_H |
| 3310 | UINT64_C(76546048), // MUL_ZPmZ_S |
| 3311 | UINT64_C(1155594240), // MUL_ZZZI_D |
| 3312 | UINT64_C(1143011328), // MUL_ZZZI_H |
| 3313 | UINT64_C(1151399936), // MUL_ZZZI_S |
| 3314 | UINT64_C(69230592), // MUL_ZZZ_B |
| 3315 | UINT64_C(81813504), // MUL_ZZZ_D |
| 3316 | UINT64_C(73424896), // MUL_ZZZ_H |
| 3317 | UINT64_C(77619200), // MUL_ZZZ_S |
| 3318 | UINT64_C(1310759936), // MULv16i8 |
| 3319 | UINT64_C(245406720), // MULv2i32 |
| 3320 | UINT64_C(260079616), // MULv2i32_indexed |
| 3321 | UINT64_C(241212416), // MULv4i16 |
| 3322 | UINT64_C(255885312), // MULv4i16_indexed |
| 3323 | UINT64_C(1319148544), // MULv4i32 |
| 3324 | UINT64_C(1333821440), // MULv4i32_indexed |
| 3325 | UINT64_C(1314954240), // MULv8i16 |
| 3326 | UINT64_C(1329627136), // MULv8i16_indexed |
| 3327 | UINT64_C(237018112), // MULv8i8 |
| 3328 | UINT64_C(788530176), // MVNIv2i32 |
| 3329 | UINT64_C(788579328), // MVNIv2s_msl |
| 3330 | UINT64_C(788562944), // MVNIv4i16 |
| 3331 | UINT64_C(1862272000), // MVNIv4i32 |
| 3332 | UINT64_C(1862321152), // MVNIv4s_msl |
| 3333 | UINT64_C(1862304768), // MVNIv8i16 |
| 3334 | UINT64_C(633356816), // NANDS_PPzPP |
| 3335 | UINT64_C(629162512), // NAND_PPzPP |
| 3336 | UINT64_C(81804288), // NBSL_ZZZZ |
| 3337 | UINT64_C(68657152), // NEG_ZPmZ_B |
| 3338 | UINT64_C(81240064), // NEG_ZPmZ_D |
| 3339 | UINT64_C(72851456), // NEG_ZPmZ_H |
| 3340 | UINT64_C(77045760), // NEG_ZPmZ_S |
| 3341 | UINT64_C(1847638016), // NEGv16i8 |
| 3342 | UINT64_C(2128656384), // NEGv1i64 |
| 3343 | UINT64_C(782284800), // NEGv2i32 |
| 3344 | UINT64_C(1860220928), // NEGv2i64 |
| 3345 | UINT64_C(778090496), // NEGv4i16 |
| 3346 | UINT64_C(1856026624), // NEGv4i32 |
| 3347 | UINT64_C(1851832320), // NEGv8i16 |
| 3348 | UINT64_C(773896192), // NEGv8i8 |
| 3349 | UINT64_C(1159757840), // NMATCH_PPzZZ_B |
| 3350 | UINT64_C(1163952144), // NMATCH_PPzZZ_H |
| 3351 | UINT64_C(633356800), // NORS_PPzPP |
| 3352 | UINT64_C(629162496), // NOR_PPzPP |
| 3353 | UINT64_C(69115904), // NOT_ZPmZ_B |
| 3354 | UINT64_C(81698816), // NOT_ZPmZ_D |
| 3355 | UINT64_C(73310208), // NOT_ZPmZ_H |
| 3356 | UINT64_C(77504512), // NOT_ZPmZ_S |
| 3357 | UINT64_C(1847613440), // NOTv16i8 |
| 3358 | UINT64_C(773871616), // NOTv8i8 |
| 3359 | UINT64_C(633356304), // ORNS_PPzPP |
| 3360 | UINT64_C(706740224), // ORNWrs |
| 3361 | UINT64_C(2854223872), // ORNXrs |
| 3362 | UINT64_C(629162000), // ORN_PPzPP |
| 3363 | UINT64_C(1323310080), // ORNv16i8 |
| 3364 | UINT64_C(249568256), // ORNv8i8 |
| 3365 | UINT64_C(633356288), // ORRS_PPzPP |
| 3366 | UINT64_C(838860800), // ORRWri |
| 3367 | UINT64_C(704643072), // ORRWrs |
| 3368 | UINT64_C(2986344448), // ORRXri |
| 3369 | UINT64_C(2852126720), // ORRXrs |
| 3370 | UINT64_C(629161984), // ORR_PPzPP |
| 3371 | UINT64_C(83886080), // ORR_ZI |
| 3372 | UINT64_C(68681728), // ORR_ZPmZ_B |
| 3373 | UINT64_C(81264640), // ORR_ZPmZ_D |
| 3374 | UINT64_C(72876032), // ORR_ZPmZ_H |
| 3375 | UINT64_C(77070336), // ORR_ZPmZ_S |
| 3376 | UINT64_C(73412608), // ORR_ZZZ |
| 3377 | UINT64_C(1319115776), // ORRv16i8 |
| 3378 | UINT64_C(251663360), // ORRv2i32 |
| 3379 | UINT64_C(251696128), // ORRv4i16 |
| 3380 | UINT64_C(1325405184), // ORRv4i32 |
| 3381 | UINT64_C(1325437952), // ORRv8i16 |
| 3382 | UINT64_C(245373952), // ORRv8i8 |
| 3383 | UINT64_C(68689920), // ORV_VPZ_B |
| 3384 | UINT64_C(81272832), // ORV_VPZ_D |
| 3385 | UINT64_C(72884224), // ORV_VPZ_H |
| 3386 | UINT64_C(77078528), // ORV_VPZ_S |
| 3387 | UINT64_C(3670083584), // PACDA |
| 3388 | UINT64_C(3670084608), // PACDB |
| 3389 | UINT64_C(3670092768), // PACDZA |
| 3390 | UINT64_C(3670093792), // PACDZB |
| 3391 | UINT64_C(2596286464), // PACGA |
| 3392 | UINT64_C(3670081536), // PACIA |
| 3393 | UINT64_C(3573752095), // PACIA1716 |
| 3394 | UINT64_C(3573752639), // PACIASP |
| 3395 | UINT64_C(3573752607), // PACIAZ |
| 3396 | UINT64_C(3670082560), // PACIB |
| 3397 | UINT64_C(3573752159), // PACIB1716 |
| 3398 | UINT64_C(3573752703), // PACIBSP |
| 3399 | UINT64_C(3573752671), // PACIBZ |
| 3400 | UINT64_C(3670090720), // PACIZA |
| 3401 | UINT64_C(3670091744), // PACIZB |
| 3402 | UINT64_C(622388224), // PFALSE |
| 3403 | UINT64_C(626573312), // PFIRST_B |
| 3404 | UINT64_C(1170237440), // PMULLB_ZZZ_D |
| 3405 | UINT64_C(1161848832), // PMULLB_ZZZ_H |
| 3406 | UINT64_C(1157654528), // PMULLB_ZZZ_Q |
| 3407 | UINT64_C(1170238464), // PMULLT_ZZZ_D |
| 3408 | UINT64_C(1161849856), // PMULLT_ZZZ_H |
| 3409 | UINT64_C(1157655552), // PMULLT_ZZZ_Q |
| 3410 | UINT64_C(1310777344), // PMULLv16i8 |
| 3411 | UINT64_C(249618432), // PMULLv1i64 |
| 3412 | UINT64_C(1323360256), // PMULLv2i64 |
| 3413 | UINT64_C(237035520), // PMULLv8i8 |
| 3414 | UINT64_C(69231616), // PMUL_ZZZ_B |
| 3415 | UINT64_C(1847630848), // PMULv16i8 |
| 3416 | UINT64_C(773889024), // PMULv8i8 |
| 3417 | UINT64_C(622445568), // PNEXT_B |
| 3418 | UINT64_C(635028480), // PNEXT_D |
| 3419 | UINT64_C(626639872), // PNEXT_H |
| 3420 | UINT64_C(630834176), // PNEXT_S |
| 3421 | UINT64_C(3288391680), // PRFB_D_PZI |
| 3422 | UINT64_C(3294658560), // PRFB_D_SCALED |
| 3423 | UINT64_C(3294625792), // PRFB_D_SXTW_SCALED |
| 3424 | UINT64_C(3290431488), // PRFB_D_UXTW_SCALED |
| 3425 | UINT64_C(2243952640), // PRFB_PRI |
| 3426 | UINT64_C(2214641664), // PRFB_PRR |
| 3427 | UINT64_C(2214649856), // PRFB_S_PZI |
| 3428 | UINT64_C(2220883968), // PRFB_S_SXTW_SCALED |
| 3429 | UINT64_C(2216689664), // PRFB_S_UXTW_SCALED |
| 3430 | UINT64_C(3313557504), // PRFD_D_PZI |
| 3431 | UINT64_C(3294683136), // PRFD_D_SCALED |
| 3432 | UINT64_C(3294650368), // PRFD_D_SXTW_SCALED |
| 3433 | UINT64_C(3290456064), // PRFD_D_UXTW_SCALED |
| 3434 | UINT64_C(2243977216), // PRFD_PRI |
| 3435 | UINT64_C(2239807488), // PRFD_PRR |
| 3436 | UINT64_C(2239815680), // PRFD_S_PZI |
| 3437 | UINT64_C(2220908544), // PRFD_S_SXTW_SCALED |
| 3438 | UINT64_C(2216714240), // PRFD_S_UXTW_SCALED |
| 3439 | UINT64_C(3296780288), // PRFH_D_PZI |
| 3440 | UINT64_C(3294666752), // PRFH_D_SCALED |
| 3441 | UINT64_C(3294633984), // PRFH_D_SXTW_SCALED |
| 3442 | UINT64_C(3290439680), // PRFH_D_UXTW_SCALED |
| 3443 | UINT64_C(2243960832), // PRFH_PRI |
| 3444 | UINT64_C(2223030272), // PRFH_PRR |
| 3445 | UINT64_C(2223038464), // PRFH_S_PZI |
| 3446 | UINT64_C(2220892160), // PRFH_S_SXTW_SCALED |
| 3447 | UINT64_C(2216697856), // PRFH_S_UXTW_SCALED |
| 3448 | UINT64_C(3623878656), // PRFMl |
| 3449 | UINT64_C(4171253760), // PRFMroW |
| 3450 | UINT64_C(4171261952), // PRFMroX |
| 3451 | UINT64_C(4185915392), // PRFMui |
| 3452 | UINT64_C(2231418880), // PRFS_PRR |
| 3453 | UINT64_C(4169138176), // PRFUMi |
| 3454 | UINT64_C(3305168896), // PRFW_D_PZI |
| 3455 | UINT64_C(3294674944), // PRFW_D_SCALED |
| 3456 | UINT64_C(3294642176), // PRFW_D_SXTW_SCALED |
| 3457 | UINT64_C(3290447872), // PRFW_D_UXTW_SCALED |
| 3458 | UINT64_C(2243969024), // PRFW_PRI |
| 3459 | UINT64_C(2231427072), // PRFW_S_PZI |
| 3460 | UINT64_C(2220900352), // PRFW_S_SXTW_SCALED |
| 3461 | UINT64_C(2216706048), // PRFW_S_UXTW_SCALED |
| 3462 | UINT64_C(626049024), // PTEST_PP |
| 3463 | UINT64_C(622452736), // PTRUES_B |
| 3464 | UINT64_C(635035648), // PTRUES_D |
| 3465 | UINT64_C(626647040), // PTRUES_H |
| 3466 | UINT64_C(630841344), // PTRUES_S |
| 3467 | UINT64_C(622387200), // PTRUE_B |
| 3468 | UINT64_C(634970112), // PTRUE_D |
| 3469 | UINT64_C(626581504), // PTRUE_H |
| 3470 | UINT64_C(630775808), // PTRUE_S |
| 3471 | UINT64_C(87113728), // PUNPKHI_PP |
| 3472 | UINT64_C(87048192), // PUNPKLO_PP |
| 3473 | UINT64_C(1163945984), // RADDHNB_ZZZ_B |
| 3474 | UINT64_C(1168140288), // RADDHNB_ZZZ_H |
| 3475 | UINT64_C(1172334592), // RADDHNB_ZZZ_S |
| 3476 | UINT64_C(1163947008), // RADDHNT_ZZZ_B |
| 3477 | UINT64_C(1168141312), // RADDHNT_ZZZ_H |
| 3478 | UINT64_C(1172335616), // RADDHNT_ZZZ_S |
| 3479 | UINT64_C(782254080), // RADDHNv2i64_v2i32 |
| 3480 | UINT64_C(1855995904), // RADDHNv2i64_v4i32 |
| 3481 | UINT64_C(778059776), // RADDHNv4i32_v4i16 |
| 3482 | UINT64_C(1851801600), // RADDHNv4i32_v8i16 |
| 3483 | UINT64_C(1847607296), // RADDHNv8i16_v16i8 |
| 3484 | UINT64_C(773865472), // RADDHNv8i16_v8i8 |
| 3485 | UINT64_C(3462433792), // RAX1 |
| 3486 | UINT64_C(1159787520), // RAX1_ZZZ_D |
| 3487 | UINT64_C(1522532352), // RBITWr |
| 3488 | UINT64_C(3670016000), // RBITXr |
| 3489 | UINT64_C(86474752), // RBIT_ZPmZ_B |
| 3490 | UINT64_C(99057664), // RBIT_ZPmZ_D |
| 3491 | UINT64_C(90669056), // RBIT_ZPmZ_H |
| 3492 | UINT64_C(94863360), // RBIT_ZPmZ_S |
| 3493 | UINT64_C(1851807744), // RBITv16i8 |
| 3494 | UINT64_C(778065920), // RBITv8i8 |
| 3495 | UINT64_C(626585600), // RDFFRS_PPz |
| 3496 | UINT64_C(622391296), // RDFFR_PPz_REAL |
| 3497 | UINT64_C(622456832), // RDFFR_P_REAL |
| 3498 | UINT64_C(79646720), // RDVLI_XI |
| 3499 | UINT64_C(3596550144), // RET |
| 3500 | UINT64_C(3596553215), // RETAA |
| 3501 | UINT64_C(3596554239), // RETAB |
| 3502 | UINT64_C(1522533376), // REV16Wr |
| 3503 | UINT64_C(3670017024), // REV16Xr |
| 3504 | UINT64_C(1310726144), // REV16v16i8 |
| 3505 | UINT64_C(236984320), // REV16v8i8 |
| 3506 | UINT64_C(3670018048), // REV32Xr |
| 3507 | UINT64_C(1847592960), // REV32v16i8 |
| 3508 | UINT64_C(778045440), // REV32v4i16 |
| 3509 | UINT64_C(1851787264), // REV32v8i16 |
| 3510 | UINT64_C(773851136), // REV32v8i8 |
| 3511 | UINT64_C(1310722048), // REV64v16i8 |
| 3512 | UINT64_C(245368832), // REV64v2i32 |
| 3513 | UINT64_C(241174528), // REV64v4i16 |
| 3514 | UINT64_C(1319110656), // REV64v4i32 |
| 3515 | UINT64_C(1314916352), // REV64v8i16 |
| 3516 | UINT64_C(236980224), // REV64v8i8 |
| 3517 | UINT64_C(98861056), // REVB_ZPmZ_D |
| 3518 | UINT64_C(90472448), // REVB_ZPmZ_H |
| 3519 | UINT64_C(94666752), // REVB_ZPmZ_S |
| 3520 | UINT64_C(98926592), // REVH_ZPmZ_D |
| 3521 | UINT64_C(94732288), // REVH_ZPmZ_S |
| 3522 | UINT64_C(98992128), // REVW_ZPmZ_D |
| 3523 | UINT64_C(1522534400), // REVWr |
| 3524 | UINT64_C(3670019072), // REVXr |
| 3525 | UINT64_C(87310336), // REV_PP_B |
| 3526 | UINT64_C(99893248), // REV_PP_D |
| 3527 | UINT64_C(91504640), // REV_PP_H |
| 3528 | UINT64_C(95698944), // REV_PP_S |
| 3529 | UINT64_C(87570432), // REV_ZZ_B |
| 3530 | UINT64_C(100153344), // REV_ZZ_D |
| 3531 | UINT64_C(91764736), // REV_ZZ_H |
| 3532 | UINT64_C(95959040), // REV_ZZ_S |
| 3533 | UINT64_C(3120563200), // RMIF |
| 3534 | UINT64_C(448801792), // RORVWr |
| 3535 | UINT64_C(2596285440), // RORVXr |
| 3536 | UINT64_C(1160255488), // RSHRNB_ZZI_B |
| 3537 | UINT64_C(1160779776), // RSHRNB_ZZI_H |
| 3538 | UINT64_C(1163925504), // RSHRNB_ZZI_S |
| 3539 | UINT64_C(1160256512), // RSHRNT_ZZI_B |
| 3540 | UINT64_C(1160780800), // RSHRNT_ZZI_H |
| 3541 | UINT64_C(1163926528), // RSHRNT_ZZI_S |
| 3542 | UINT64_C(1325960192), // RSHRNv16i8_shift |
| 3543 | UINT64_C(253791232), // RSHRNv2i32_shift |
| 3544 | UINT64_C(252742656), // RSHRNv4i16_shift |
| 3545 | UINT64_C(1327533056), // RSHRNv4i32_shift |
| 3546 | UINT64_C(1326484480), // RSHRNv8i16_shift |
| 3547 | UINT64_C(252218368), // RSHRNv8i8_shift |
| 3548 | UINT64_C(1163950080), // RSUBHNB_ZZZ_B |
| 3549 | UINT64_C(1168144384), // RSUBHNB_ZZZ_H |
| 3550 | UINT64_C(1172338688), // RSUBHNB_ZZZ_S |
| 3551 | UINT64_C(1163951104), // RSUBHNT_ZZZ_B |
| 3552 | UINT64_C(1168145408), // RSUBHNT_ZZZ_H |
| 3553 | UINT64_C(1172339712), // RSUBHNT_ZZZ_S |
| 3554 | UINT64_C(782262272), // RSUBHNv2i64_v2i32 |
| 3555 | UINT64_C(1856004096), // RSUBHNv2i64_v4i32 |
| 3556 | UINT64_C(778067968), // RSUBHNv4i32_v4i16 |
| 3557 | UINT64_C(1851809792), // RSUBHNv4i32_v8i16 |
| 3558 | UINT64_C(1847615488), // RSUBHNv8i16_v16i8 |
| 3559 | UINT64_C(773873664), // RSUBHNv8i16_v8i8 |
| 3560 | UINT64_C(1170259968), // SABALB_ZZZ_D |
| 3561 | UINT64_C(1161871360), // SABALB_ZZZ_H |
| 3562 | UINT64_C(1166065664), // SABALB_ZZZ_S |
| 3563 | UINT64_C(1170260992), // SABALT_ZZZ_D |
| 3564 | UINT64_C(1161872384), // SABALT_ZZZ_H |
| 3565 | UINT64_C(1166066688), // SABALT_ZZZ_S |
| 3566 | UINT64_C(1310740480), // SABALv16i8_v8i16 |
| 3567 | UINT64_C(245387264), // SABALv2i32_v2i64 |
| 3568 | UINT64_C(241192960), // SABALv4i16_v4i32 |
| 3569 | UINT64_C(1319129088), // SABALv4i32_v2i64 |
| 3570 | UINT64_C(1314934784), // SABALv8i16_v4i32 |
| 3571 | UINT64_C(236998656), // SABALv8i8_v8i16 |
| 3572 | UINT64_C(1157691392), // SABA_ZZZ_B |
| 3573 | UINT64_C(1170274304), // SABA_ZZZ_D |
| 3574 | UINT64_C(1161885696), // SABA_ZZZ_H |
| 3575 | UINT64_C(1166080000), // SABA_ZZZ_S |
| 3576 | UINT64_C(1310751744), // SABAv16i8 |
| 3577 | UINT64_C(245398528), // SABAv2i32 |
| 3578 | UINT64_C(241204224), // SABAv4i16 |
| 3579 | UINT64_C(1319140352), // SABAv4i32 |
| 3580 | UINT64_C(1314946048), // SABAv8i16 |
| 3581 | UINT64_C(237009920), // SABAv8i8 |
| 3582 | UINT64_C(1170223104), // SABDLB_ZZZ_D |
| 3583 | UINT64_C(1161834496), // SABDLB_ZZZ_H |
| 3584 | UINT64_C(1166028800), // SABDLB_ZZZ_S |
| 3585 | UINT64_C(1170224128), // SABDLT_ZZZ_D |
| 3586 | UINT64_C(1161835520), // SABDLT_ZZZ_H |
| 3587 | UINT64_C(1166029824), // SABDLT_ZZZ_S |
| 3588 | UINT64_C(1310748672), // SABDLv16i8_v8i16 |
| 3589 | UINT64_C(245395456), // SABDLv2i32_v2i64 |
| 3590 | UINT64_C(241201152), // SABDLv4i16_v4i32 |
| 3591 | UINT64_C(1319137280), // SABDLv4i32_v2i64 |
| 3592 | UINT64_C(1314942976), // SABDLv8i16_v4i32 |
| 3593 | UINT64_C(237006848), // SABDLv8i8_v8i16 |
| 3594 | UINT64_C(67895296), // SABD_ZPmZ_B |
| 3595 | UINT64_C(80478208), // SABD_ZPmZ_D |
| 3596 | UINT64_C(72089600), // SABD_ZPmZ_H |
| 3597 | UINT64_C(76283904), // SABD_ZPmZ_S |
| 3598 | UINT64_C(1310749696), // SABDv16i8 |
| 3599 | UINT64_C(245396480), // SABDv2i32 |
| 3600 | UINT64_C(241202176), // SABDv4i16 |
| 3601 | UINT64_C(1319138304), // SABDv4i32 |
| 3602 | UINT64_C(1314944000), // SABDv8i16 |
| 3603 | UINT64_C(237007872), // SABDv8i8 |
| 3604 | UINT64_C(1153736704), // SADALP_ZPmZ_D |
| 3605 | UINT64_C(1145348096), // SADALP_ZPmZ_H |
| 3606 | UINT64_C(1149542400), // SADALP_ZPmZ_S |
| 3607 | UINT64_C(1310746624), // SADALPv16i8_v8i16 |
| 3608 | UINT64_C(245393408), // SADALPv2i32_v1i64 |
| 3609 | UINT64_C(241199104), // SADALPv4i16_v2i32 |
| 3610 | UINT64_C(1319135232), // SADALPv4i32_v2i64 |
| 3611 | UINT64_C(1314940928), // SADALPv8i16_v4i32 |
| 3612 | UINT64_C(237004800), // SADALPv8i8_v4i16 |
| 3613 | UINT64_C(1170243584), // SADDLBT_ZZZ_D |
| 3614 | UINT64_C(1161854976), // SADDLBT_ZZZ_H |
| 3615 | UINT64_C(1166049280), // SADDLBT_ZZZ_S |
| 3616 | UINT64_C(1170210816), // SADDLB_ZZZ_D |
| 3617 | UINT64_C(1161822208), // SADDLB_ZZZ_H |
| 3618 | UINT64_C(1166016512), // SADDLB_ZZZ_S |
| 3619 | UINT64_C(1310730240), // SADDLPv16i8_v8i16 |
| 3620 | UINT64_C(245377024), // SADDLPv2i32_v1i64 |
| 3621 | UINT64_C(241182720), // SADDLPv4i16_v2i32 |
| 3622 | UINT64_C(1319118848), // SADDLPv4i32_v2i64 |
| 3623 | UINT64_C(1314924544), // SADDLPv8i16_v4i32 |
| 3624 | UINT64_C(236988416), // SADDLPv8i8_v4i16 |
| 3625 | UINT64_C(1170211840), // SADDLT_ZZZ_D |
| 3626 | UINT64_C(1161823232), // SADDLT_ZZZ_H |
| 3627 | UINT64_C(1166017536), // SADDLT_ZZZ_S |
| 3628 | UINT64_C(1311782912), // SADDLVv16i8v |
| 3629 | UINT64_C(242235392), // SADDLVv4i16v |
| 3630 | UINT64_C(1320171520), // SADDLVv4i32v |
| 3631 | UINT64_C(1315977216), // SADDLVv8i16v |
| 3632 | UINT64_C(238041088), // SADDLVv8i8v |
| 3633 | UINT64_C(1310720000), // SADDLv16i8_v8i16 |
| 3634 | UINT64_C(245366784), // SADDLv2i32_v2i64 |
| 3635 | UINT64_C(241172480), // SADDLv4i16_v4i32 |
| 3636 | UINT64_C(1319108608), // SADDLv4i32_v2i64 |
| 3637 | UINT64_C(1314914304), // SADDLv8i16_v4i32 |
| 3638 | UINT64_C(236978176), // SADDLv8i8_v8i16 |
| 3639 | UINT64_C(67117056), // SADDV_VPZ_B |
| 3640 | UINT64_C(71311360), // SADDV_VPZ_H |
| 3641 | UINT64_C(75505664), // SADDV_VPZ_S |
| 3642 | UINT64_C(1170227200), // SADDWB_ZZZ_D |
| 3643 | UINT64_C(1161838592), // SADDWB_ZZZ_H |
| 3644 | UINT64_C(1166032896), // SADDWB_ZZZ_S |
| 3645 | UINT64_C(1170228224), // SADDWT_ZZZ_D |
| 3646 | UINT64_C(1161839616), // SADDWT_ZZZ_H |
| 3647 | UINT64_C(1166033920), // SADDWT_ZZZ_S |
| 3648 | UINT64_C(1310724096), // SADDWv16i8_v8i16 |
| 3649 | UINT64_C(245370880), // SADDWv2i32_v2i64 |
| 3650 | UINT64_C(241176576), // SADDWv4i16_v4i32 |
| 3651 | UINT64_C(1319112704), // SADDWv4i32_v2i64 |
| 3652 | UINT64_C(1314918400), // SADDWv8i16_v4i32 |
| 3653 | UINT64_C(236982272), // SADDWv8i8_v8i16 |
| 3654 | UINT64_C(3573756159), // SB |
| 3655 | UINT64_C(1170264064), // SBCLB_ZZZ_D |
| 3656 | UINT64_C(1166069760), // SBCLB_ZZZ_S |
| 3657 | UINT64_C(1170265088), // SBCLT_ZZZ_D |
| 3658 | UINT64_C(1166070784), // SBCLT_ZZZ_S |
| 3659 | UINT64_C(2046820352), // SBCSWr |
| 3660 | UINT64_C(4194304000), // SBCSXr |
| 3661 | UINT64_C(1509949440), // SBCWr |
| 3662 | UINT64_C(3657433088), // SBCXr |
| 3663 | UINT64_C(318767104), // SBFMWri |
| 3664 | UINT64_C(2470445056), // SBFMXri |
| 3665 | UINT64_C(507674624), // SCVTFSWDri |
| 3666 | UINT64_C(516063232), // SCVTFSWHri |
| 3667 | UINT64_C(503480320), // SCVTFSWSri |
| 3668 | UINT64_C(2655125504), // SCVTFSXDri |
| 3669 | UINT64_C(2663514112), // SCVTFSXHri |
| 3670 | UINT64_C(2650931200), // SCVTFSXSri |
| 3671 | UINT64_C(509739008), // SCVTFUWDri |
| 3672 | UINT64_C(518127616), // SCVTFUWHri |
| 3673 | UINT64_C(505544704), // SCVTFUWSri |
| 3674 | UINT64_C(2657222656), // SCVTFUXDri |
| 3675 | UINT64_C(2665611264), // SCVTFUXHri |
| 3676 | UINT64_C(2653028352), // SCVTFUXSri |
| 3677 | UINT64_C(1708564480), // SCVTF_ZPmZ_DtoD |
| 3678 | UINT64_C(1700175872), // SCVTF_ZPmZ_DtoH |
| 3679 | UINT64_C(1708433408), // SCVTF_ZPmZ_DtoS |
| 3680 | UINT64_C(1699913728), // SCVTF_ZPmZ_HtoH |
| 3681 | UINT64_C(1708171264), // SCVTF_ZPmZ_StoD |
| 3682 | UINT64_C(1700044800), // SCVTF_ZPmZ_StoH |
| 3683 | UINT64_C(1704239104), // SCVTF_ZPmZ_StoS |
| 3684 | UINT64_C(1598088192), // SCVTFd |
| 3685 | UINT64_C(1594942464), // SCVTFh |
| 3686 | UINT64_C(1595991040), // SCVTFs |
| 3687 | UINT64_C(1585043456), // SCVTFv1i16 |
| 3688 | UINT64_C(1579276288), // SCVTFv1i32 |
| 3689 | UINT64_C(1583470592), // SCVTFv1i64 |
| 3690 | UINT64_C(237099008), // SCVTFv2f32 |
| 3691 | UINT64_C(1315035136), // SCVTFv2f64 |
| 3692 | UINT64_C(253813760), // SCVTFv2i32_shift |
| 3693 | UINT64_C(1329652736), // SCVTFv2i64_shift |
| 3694 | UINT64_C(242866176), // SCVTFv4f16 |
| 3695 | UINT64_C(1310840832), // SCVTFv4f32 |
| 3696 | UINT64_C(252765184), // SCVTFv4i16_shift |
| 3697 | UINT64_C(1327555584), // SCVTFv4i32_shift |
| 3698 | UINT64_C(1316608000), // SCVTFv8f16 |
| 3699 | UINT64_C(1326507008), // SCVTFv8i16_shift |
| 3700 | UINT64_C(81133568), // SDIVR_ZPmZ_D |
| 3701 | UINT64_C(76939264), // SDIVR_ZPmZ_S |
| 3702 | UINT64_C(448793600), // SDIVWr |
| 3703 | UINT64_C(2596277248), // SDIVXr |
| 3704 | UINT64_C(81002496), // SDIV_ZPmZ_D |
| 3705 | UINT64_C(76808192), // SDIV_ZPmZ_S |
| 3706 | UINT64_C(1155530752), // SDOT_ZZZI_D |
| 3707 | UINT64_C(1151336448), // SDOT_ZZZI_S |
| 3708 | UINT64_C(1153433600), // SDOT_ZZZ_D |
| 3709 | UINT64_C(1149239296), // SDOT_ZZZ_S |
| 3710 | UINT64_C(1333846016), // SDOTlanev16i8 |
| 3711 | UINT64_C(260104192), // SDOTlanev8i8 |
| 3712 | UINT64_C(1317049344), // SDOTv16i8 |
| 3713 | UINT64_C(243307520), // SDOTv8i8 |
| 3714 | UINT64_C(620773904), // SEL_PPPP |
| 3715 | UINT64_C(86032384), // SEL_ZPZZ_B |
| 3716 | UINT64_C(98615296), // SEL_ZPZZ_D |
| 3717 | UINT64_C(90226688), // SEL_ZPZZ_H |
| 3718 | UINT64_C(94420992), // SEL_ZPZZ_S |
| 3719 | UINT64_C(973096973), // SETF16 |
| 3720 | UINT64_C(973080589), // SETF8 |
| 3721 | UINT64_C(623677440), // SETFFR |
| 3722 | UINT64_C(1577058304), // SHA1Crrr |
| 3723 | UINT64_C(1579681792), // SHA1Hrr |
| 3724 | UINT64_C(1577066496), // SHA1Mrrr |
| 3725 | UINT64_C(1577062400), // SHA1Prrr |
| 3726 | UINT64_C(1577070592), // SHA1SU0rrr |
| 3727 | UINT64_C(1579685888), // SHA1SU1rr |
| 3728 | UINT64_C(1577078784), // SHA256H2rrr |
| 3729 | UINT64_C(1577074688), // SHA256Hrrr |
| 3730 | UINT64_C(1579689984), // SHA256SU0rr |
| 3731 | UINT64_C(1577082880), // SHA256SU1rrr |
| 3732 | UINT64_C(3462430720), // SHA512H |
| 3733 | UINT64_C(3462431744), // SHA512H2 |
| 3734 | UINT64_C(3468722176), // SHA512SU0 |
| 3735 | UINT64_C(3462432768), // SHA512SU1 |
| 3736 | UINT64_C(1141932032), // SHADD_ZPmZ_B |
| 3737 | UINT64_C(1154514944), // SHADD_ZPmZ_D |
| 3738 | UINT64_C(1146126336), // SHADD_ZPmZ_H |
| 3739 | UINT64_C(1150320640), // SHADD_ZPmZ_S |
| 3740 | UINT64_C(1310721024), // SHADDv16i8 |
| 3741 | UINT64_C(245367808), // SHADDv2i32 |
| 3742 | UINT64_C(241173504), // SHADDv4i16 |
| 3743 | UINT64_C(1319109632), // SHADDv4i32 |
| 3744 | UINT64_C(1314915328), // SHADDv8i16 |
| 3745 | UINT64_C(236979200), // SHADDv8i8 |
| 3746 | UINT64_C(1847670784), // SHLLv16i8 |
| 3747 | UINT64_C(782317568), // SHLLv2i32 |
| 3748 | UINT64_C(778123264), // SHLLv4i16 |
| 3749 | UINT64_C(1856059392), // SHLLv4i32 |
| 3750 | UINT64_C(1851865088), // SHLLv8i16 |
| 3751 | UINT64_C(773928960), // SHLLv8i8 |
| 3752 | UINT64_C(1598051328), // SHLd |
| 3753 | UINT64_C(1325945856), // SHLv16i8_shift |
| 3754 | UINT64_C(253776896), // SHLv2i32_shift |
| 3755 | UINT64_C(1329615872), // SHLv2i64_shift |
| 3756 | UINT64_C(252728320), // SHLv4i16_shift |
| 3757 | UINT64_C(1327518720), // SHLv4i32_shift |
| 3758 | UINT64_C(1326470144), // SHLv8i16_shift |
| 3759 | UINT64_C(252204032), // SHLv8i8_shift |
| 3760 | UINT64_C(1160253440), // SHRNB_ZZI_B |
| 3761 | UINT64_C(1160777728), // SHRNB_ZZI_H |
| 3762 | UINT64_C(1163923456), // SHRNB_ZZI_S |
| 3763 | UINT64_C(1160254464), // SHRNT_ZZI_B |
| 3764 | UINT64_C(1160778752), // SHRNT_ZZI_H |
| 3765 | UINT64_C(1163924480), // SHRNT_ZZI_S |
| 3766 | UINT64_C(1325958144), // SHRNv16i8_shift |
| 3767 | UINT64_C(253789184), // SHRNv2i32_shift |
| 3768 | UINT64_C(252740608), // SHRNv4i16_shift |
| 3769 | UINT64_C(1327531008), // SHRNv4i32_shift |
| 3770 | UINT64_C(1326482432), // SHRNv8i16_shift |
| 3771 | UINT64_C(252216320), // SHRNv8i8_shift |
| 3772 | UINT64_C(1142325248), // SHSUBR_ZPmZ_B |
| 3773 | UINT64_C(1154908160), // SHSUBR_ZPmZ_D |
| 3774 | UINT64_C(1146519552), // SHSUBR_ZPmZ_H |
| 3775 | UINT64_C(1150713856), // SHSUBR_ZPmZ_S |
| 3776 | UINT64_C(1142063104), // SHSUB_ZPmZ_B |
| 3777 | UINT64_C(1154646016), // SHSUB_ZPmZ_D |
| 3778 | UINT64_C(1146257408), // SHSUB_ZPmZ_H |
| 3779 | UINT64_C(1150451712), // SHSUB_ZPmZ_S |
| 3780 | UINT64_C(1310729216), // SHSUBv16i8 |
| 3781 | UINT64_C(245376000), // SHSUBv2i32 |
| 3782 | UINT64_C(241181696), // SHSUBv4i16 |
| 3783 | UINT64_C(1319117824), // SHSUBv4i32 |
| 3784 | UINT64_C(1314923520), // SHSUBv8i16 |
| 3785 | UINT64_C(236987392), // SHSUBv8i8 |
| 3786 | UINT64_C(1158214656), // SLI_ZZI_B |
| 3787 | UINT64_C(1166078976), // SLI_ZZI_D |
| 3788 | UINT64_C(1158738944), // SLI_ZZI_H |
| 3789 | UINT64_C(1161884672), // SLI_ZZI_S |
| 3790 | UINT64_C(2134922240), // SLId |
| 3791 | UINT64_C(1862816768), // SLIv16i8_shift |
| 3792 | UINT64_C(790647808), // SLIv2i32_shift |
| 3793 | UINT64_C(1866486784), // SLIv2i64_shift |
| 3794 | UINT64_C(789599232), // SLIv4i16_shift |
| 3795 | UINT64_C(1864389632), // SLIv4i32_shift |
| 3796 | UINT64_C(1863341056), // SLIv8i16_shift |
| 3797 | UINT64_C(789074944), // SLIv8i8_shift |
| 3798 | UINT64_C(3462447104), // SM3PARTW1 |
| 3799 | UINT64_C(3462448128), // SM3PARTW2 |
| 3800 | UINT64_C(3460300800), // SM3SS1 |
| 3801 | UINT64_C(3460333568), // SM3TT1A |
| 3802 | UINT64_C(3460334592), // SM3TT1B |
| 3803 | UINT64_C(3460335616), // SM3TT2A |
| 3804 | UINT64_C(3460336640), // SM3TT2B |
| 3805 | UINT64_C(3468723200), // SM4E |
| 3806 | UINT64_C(1159786496), // SM4EKEY_ZZZ_S |
| 3807 | UINT64_C(3462449152), // SM4ENCKEY |
| 3808 | UINT64_C(1159979008), // SM4E_ZZZ_S |
| 3809 | UINT64_C(2602565632), // SMADDLrrr |
| 3810 | UINT64_C(1142202368), // SMAXP_ZPmZ_B |
| 3811 | UINT64_C(1154785280), // SMAXP_ZPmZ_D |
| 3812 | UINT64_C(1146396672), // SMAXP_ZPmZ_H |
| 3813 | UINT64_C(1150590976), // SMAXP_ZPmZ_S |
| 3814 | UINT64_C(1310761984), // SMAXPv16i8 |
| 3815 | UINT64_C(245408768), // SMAXPv2i32 |
| 3816 | UINT64_C(241214464), // SMAXPv4i16 |
| 3817 | UINT64_C(1319150592), // SMAXPv4i32 |
| 3818 | UINT64_C(1314956288), // SMAXPv8i16 |
| 3819 | UINT64_C(237020160), // SMAXPv8i8 |
| 3820 | UINT64_C(67641344), // SMAXV_VPZ_B |
| 3821 | UINT64_C(80224256), // SMAXV_VPZ_D |
| 3822 | UINT64_C(71835648), // SMAXV_VPZ_H |
| 3823 | UINT64_C(76029952), // SMAXV_VPZ_S |
| 3824 | UINT64_C(1311811584), // SMAXVv16i8v |
| 3825 | UINT64_C(242264064), // SMAXVv4i16v |
| 3826 | UINT64_C(1320200192), // SMAXVv4i32v |
| 3827 | UINT64_C(1316005888), // SMAXVv8i16v |
| 3828 | UINT64_C(238069760), // SMAXVv8i8v |
| 3829 | UINT64_C(623427584), // SMAX_ZI_B |
| 3830 | UINT64_C(636010496), // SMAX_ZI_D |
| 3831 | UINT64_C(627621888), // SMAX_ZI_H |
| 3832 | UINT64_C(631816192), // SMAX_ZI_S |
| 3833 | UINT64_C(67633152), // SMAX_ZPmZ_B |
| 3834 | UINT64_C(80216064), // SMAX_ZPmZ_D |
| 3835 | UINT64_C(71827456), // SMAX_ZPmZ_H |
| 3836 | UINT64_C(76021760), // SMAX_ZPmZ_S |
| 3837 | UINT64_C(1310745600), // SMAXv16i8 |
| 3838 | UINT64_C(245392384), // SMAXv2i32 |
| 3839 | UINT64_C(241198080), // SMAXv4i16 |
| 3840 | UINT64_C(1319134208), // SMAXv4i32 |
| 3841 | UINT64_C(1314939904), // SMAXv8i16 |
| 3842 | UINT64_C(237003776), // SMAXv8i8 |
| 3843 | UINT64_C(3556769795), // SMC |
| 3844 | UINT64_C(1142333440), // SMINP_ZPmZ_B |
| 3845 | UINT64_C(1154916352), // SMINP_ZPmZ_D |
| 3846 | UINT64_C(1146527744), // SMINP_ZPmZ_H |
| 3847 | UINT64_C(1150722048), // SMINP_ZPmZ_S |
| 3848 | UINT64_C(1310764032), // SMINPv16i8 |
| 3849 | UINT64_C(245410816), // SMINPv2i32 |
| 3850 | UINT64_C(241216512), // SMINPv4i16 |
| 3851 | UINT64_C(1319152640), // SMINPv4i32 |
| 3852 | UINT64_C(1314958336), // SMINPv8i16 |
| 3853 | UINT64_C(237022208), // SMINPv8i8 |
| 3854 | UINT64_C(67772416), // SMINV_VPZ_B |
| 3855 | UINT64_C(80355328), // SMINV_VPZ_D |
| 3856 | UINT64_C(71966720), // SMINV_VPZ_H |
| 3857 | UINT64_C(76161024), // SMINV_VPZ_S |
| 3858 | UINT64_C(1311877120), // SMINVv16i8v |
| 3859 | UINT64_C(242329600), // SMINVv4i16v |
| 3860 | UINT64_C(1320265728), // SMINVv4i32v |
| 3861 | UINT64_C(1316071424), // SMINVv8i16v |
| 3862 | UINT64_C(238135296), // SMINVv8i8v |
| 3863 | UINT64_C(623558656), // SMIN_ZI_B |
| 3864 | UINT64_C(636141568), // SMIN_ZI_D |
| 3865 | UINT64_C(627752960), // SMIN_ZI_H |
| 3866 | UINT64_C(631947264), // SMIN_ZI_S |
| 3867 | UINT64_C(67764224), // SMIN_ZPmZ_B |
| 3868 | UINT64_C(80347136), // SMIN_ZPmZ_D |
| 3869 | UINT64_C(71958528), // SMIN_ZPmZ_H |
| 3870 | UINT64_C(76152832), // SMIN_ZPmZ_S |
| 3871 | UINT64_C(1310747648), // SMINv16i8 |
| 3872 | UINT64_C(245394432), // SMINv2i32 |
| 3873 | UINT64_C(241200128), // SMINv4i16 |
| 3874 | UINT64_C(1319136256), // SMINv4i32 |
| 3875 | UINT64_C(1314941952), // SMINv8i16 |
| 3876 | UINT64_C(237005824), // SMINv8i8 |
| 3877 | UINT64_C(1155563520), // SMLALB_ZZZI_D |
| 3878 | UINT64_C(1151369216), // SMLALB_ZZZI_S |
| 3879 | UINT64_C(1153449984), // SMLALB_ZZZ_D |
| 3880 | UINT64_C(1145061376), // SMLALB_ZZZ_H |
| 3881 | UINT64_C(1149255680), // SMLALB_ZZZ_S |
| 3882 | UINT64_C(1155564544), // SMLALT_ZZZI_D |
| 3883 | UINT64_C(1151370240), // SMLALT_ZZZI_S |
| 3884 | UINT64_C(1153451008), // SMLALT_ZZZ_D |
| 3885 | UINT64_C(1145062400), // SMLALT_ZZZ_H |
| 3886 | UINT64_C(1149256704), // SMLALT_ZZZ_S |
| 3887 | UINT64_C(1310752768), // SMLALv16i8_v8i16 |
| 3888 | UINT64_C(260055040), // SMLALv2i32_indexed |
| 3889 | UINT64_C(245399552), // SMLALv2i32_v2i64 |
| 3890 | UINT64_C(255860736), // SMLALv4i16_indexed |
| 3891 | UINT64_C(241205248), // SMLALv4i16_v4i32 |
| 3892 | UINT64_C(1333796864), // SMLALv4i32_indexed |
| 3893 | UINT64_C(1319141376), // SMLALv4i32_v2i64 |
| 3894 | UINT64_C(1329602560), // SMLALv8i16_indexed |
| 3895 | UINT64_C(1314947072), // SMLALv8i16_v4i32 |
| 3896 | UINT64_C(237010944), // SMLALv8i8_v8i16 |
| 3897 | UINT64_C(1155571712), // SMLSLB_ZZZI_D |
| 3898 | UINT64_C(1151377408), // SMLSLB_ZZZI_S |
| 3899 | UINT64_C(1153454080), // SMLSLB_ZZZ_D |
| 3900 | UINT64_C(1145065472), // SMLSLB_ZZZ_H |
| 3901 | UINT64_C(1149259776), // SMLSLB_ZZZ_S |
| 3902 | UINT64_C(1155572736), // SMLSLT_ZZZI_D |
| 3903 | UINT64_C(1151378432), // SMLSLT_ZZZI_S |
| 3904 | UINT64_C(1153455104), // SMLSLT_ZZZ_D |
| 3905 | UINT64_C(1145066496), // SMLSLT_ZZZ_H |
| 3906 | UINT64_C(1149260800), // SMLSLT_ZZZ_S |
| 3907 | UINT64_C(1310760960), // SMLSLv16i8_v8i16 |
| 3908 | UINT64_C(260071424), // SMLSLv2i32_indexed |
| 3909 | UINT64_C(245407744), // SMLSLv2i32_v2i64 |
| 3910 | UINT64_C(255877120), // SMLSLv4i16_indexed |
| 3911 | UINT64_C(241213440), // SMLSLv4i16_v4i32 |
| 3912 | UINT64_C(1333813248), // SMLSLv4i32_indexed |
| 3913 | UINT64_C(1319149568), // SMLSLv4i32_v2i64 |
| 3914 | UINT64_C(1329618944), // SMLSLv8i16_indexed |
| 3915 | UINT64_C(1314955264), // SMLSLv8i16_v4i32 |
| 3916 | UINT64_C(237019136), // SMLSLv8i8_v8i16 |
| 3917 | UINT64_C(1317053440), // SMMLA |
| 3918 | UINT64_C(1157666816), // SMMLA_ZZZ |
| 3919 | UINT64_C(235023360), // SMOVvi16to32 |
| 3920 | UINT64_C(1308765184), // SMOVvi16to64 |
| 3921 | UINT64_C(1308896256), // SMOVvi32to64 |
| 3922 | UINT64_C(234957824), // SMOVvi8to32 |
| 3923 | UINT64_C(1308699648), // SMOVvi8to64 |
| 3924 | UINT64_C(2602598400), // SMSUBLrrr |
| 3925 | UINT64_C(68288512), // SMULH_ZPmZ_B |
| 3926 | UINT64_C(80871424), // SMULH_ZPmZ_D |
| 3927 | UINT64_C(72482816), // SMULH_ZPmZ_H |
| 3928 | UINT64_C(76677120), // SMULH_ZPmZ_S |
| 3929 | UINT64_C(69232640), // SMULH_ZZZ_B |
| 3930 | UINT64_C(81815552), // SMULH_ZZZ_D |
| 3931 | UINT64_C(73426944), // SMULH_ZZZ_H |
| 3932 | UINT64_C(77621248), // SMULH_ZZZ_S |
| 3933 | UINT64_C(2604662784), // SMULHrr |
| 3934 | UINT64_C(1155579904), // SMULLB_ZZZI_D |
| 3935 | UINT64_C(1151385600), // SMULLB_ZZZI_S |
| 3936 | UINT64_C(1170239488), // SMULLB_ZZZ_D |
| 3937 | UINT64_C(1161850880), // SMULLB_ZZZ_H |
| 3938 | UINT64_C(1166045184), // SMULLB_ZZZ_S |
| 3939 | UINT64_C(1155580928), // SMULLT_ZZZI_D |
| 3940 | UINT64_C(1151386624), // SMULLT_ZZZI_S |
| 3941 | UINT64_C(1170240512), // SMULLT_ZZZ_D |
| 3942 | UINT64_C(1161851904), // SMULLT_ZZZ_H |
| 3943 | UINT64_C(1166046208), // SMULLT_ZZZ_S |
| 3944 | UINT64_C(1310769152), // SMULLv16i8_v8i16 |
| 3945 | UINT64_C(260087808), // SMULLv2i32_indexed |
| 3946 | UINT64_C(245415936), // SMULLv2i32_v2i64 |
| 3947 | UINT64_C(255893504), // SMULLv4i16_indexed |
| 3948 | UINT64_C(241221632), // SMULLv4i16_v4i32 |
| 3949 | UINT64_C(1333829632), // SMULLv4i32_indexed |
| 3950 | UINT64_C(1319157760), // SMULLv4i32_v2i64 |
| 3951 | UINT64_C(1329635328), // SMULLv8i16_indexed |
| 3952 | UINT64_C(1314963456), // SMULLv8i16_v4i32 |
| 3953 | UINT64_C(237027328), // SMULLv8i8_v8i16 |
| 3954 | UINT64_C(86867968), // SPLICE_ZPZZ_B |
| 3955 | UINT64_C(99450880), // SPLICE_ZPZZ_D |
| 3956 | UINT64_C(91062272), // SPLICE_ZPZZ_H |
| 3957 | UINT64_C(95256576), // SPLICE_ZPZZ_S |
| 3958 | UINT64_C(86802432), // SPLICE_ZPZ_B |
| 3959 | UINT64_C(99385344), // SPLICE_ZPZ_D |
| 3960 | UINT64_C(90996736), // SPLICE_ZPZ_H |
| 3961 | UINT64_C(95191040), // SPLICE_ZPZ_S |
| 3962 | UINT64_C(1141415936), // SQABS_ZPmZ_B |
| 3963 | UINT64_C(1153998848), // SQABS_ZPmZ_D |
| 3964 | UINT64_C(1145610240), // SQABS_ZPmZ_H |
| 3965 | UINT64_C(1149804544), // SQABS_ZPmZ_S |
| 3966 | UINT64_C(1310750720), // SQABSv16i8 |
| 3967 | UINT64_C(1583380480), // SQABSv1i16 |
| 3968 | UINT64_C(1587574784), // SQABSv1i32 |
| 3969 | UINT64_C(1591769088), // SQABSv1i64 |
| 3970 | UINT64_C(1579186176), // SQABSv1i8 |
| 3971 | UINT64_C(245397504), // SQABSv2i32 |
| 3972 | UINT64_C(1323333632), // SQABSv2i64 |
| 3973 | UINT64_C(241203200), // SQABSv4i16 |
| 3974 | UINT64_C(1319139328), // SQABSv4i32 |
| 3975 | UINT64_C(1314945024), // SQABSv8i16 |
| 3976 | UINT64_C(237008896), // SQABSv8i8 |
| 3977 | UINT64_C(623165440), // SQADD_ZI_B |
| 3978 | UINT64_C(635748352), // SQADD_ZI_D |
| 3979 | UINT64_C(627359744), // SQADD_ZI_H |
| 3980 | UINT64_C(631554048), // SQADD_ZI_S |
| 3981 | UINT64_C(1142456320), // SQADD_ZPmZ_B |
| 3982 | UINT64_C(1155039232), // SQADD_ZPmZ_D |
| 3983 | UINT64_C(1146650624), // SQADD_ZPmZ_H |
| 3984 | UINT64_C(1150844928), // SQADD_ZPmZ_S |
| 3985 | UINT64_C(69210112), // SQADD_ZZZ_B |
| 3986 | UINT64_C(81793024), // SQADD_ZZZ_D |
| 3987 | UINT64_C(73404416), // SQADD_ZZZ_H |
| 3988 | UINT64_C(77598720), // SQADD_ZZZ_S |
| 3989 | UINT64_C(1310723072), // SQADDv16i8 |
| 3990 | UINT64_C(1583352832), // SQADDv1i16 |
| 3991 | UINT64_C(1587547136), // SQADDv1i32 |
| 3992 | UINT64_C(1591741440), // SQADDv1i64 |
| 3993 | UINT64_C(1579158528), // SQADDv1i8 |
| 3994 | UINT64_C(245369856), // SQADDv2i32 |
| 3995 | UINT64_C(1323305984), // SQADDv2i64 |
| 3996 | UINT64_C(241175552), // SQADDv4i16 |
| 3997 | UINT64_C(1319111680), // SQADDv4i32 |
| 3998 | UINT64_C(1314917376), // SQADDv8i16 |
| 3999 | UINT64_C(236981248), // SQADDv8i8 |
| 4000 | UINT64_C(1157748736), // SQCADD_ZZI_B |
| 4001 | UINT64_C(1170331648), // SQCADD_ZZI_D |
| 4002 | UINT64_C(1161943040), // SQCADD_ZZI_H |
| 4003 | UINT64_C(1166137344), // SQCADD_ZZI_S |
| 4004 | UINT64_C(70318080), // SQDECB_XPiI |
| 4005 | UINT64_C(69269504), // SQDECB_XPiWdI |
| 4006 | UINT64_C(82900992), // SQDECD_XPiI |
| 4007 | UINT64_C(81852416), // SQDECD_XPiWdI |
| 4008 | UINT64_C(81840128), // SQDECD_ZPiI |
| 4009 | UINT64_C(74512384), // SQDECH_XPiI |
| 4010 | UINT64_C(73463808), // SQDECH_XPiWdI |
| 4011 | UINT64_C(73451520), // SQDECH_ZPiI |
| 4012 | UINT64_C(623544320), // SQDECP_XPWd_B |
| 4013 | UINT64_C(636127232), // SQDECP_XPWd_D |
| 4014 | UINT64_C(627738624), // SQDECP_XPWd_H |
| 4015 | UINT64_C(631932928), // SQDECP_XPWd_S |
| 4016 | UINT64_C(623545344), // SQDECP_XP_B |
| 4017 | UINT64_C(636128256), // SQDECP_XP_D |
| 4018 | UINT64_C(627739648), // SQDECP_XP_H |
| 4019 | UINT64_C(631933952), // SQDECP_XP_S |
| 4020 | UINT64_C(636125184), // SQDECP_ZP_D |
| 4021 | UINT64_C(627736576), // SQDECP_ZP_H |
| 4022 | UINT64_C(631930880), // SQDECP_ZP_S |
| 4023 | UINT64_C(78706688), // SQDECW_XPiI |
| 4024 | UINT64_C(77658112), // SQDECW_XPiWdI |
| 4025 | UINT64_C(77645824), // SQDECW_ZPiI |
| 4026 | UINT64_C(1153435648), // SQDMLALBT_ZZZ_D |
| 4027 | UINT64_C(1145047040), // SQDMLALBT_ZZZ_H |
| 4028 | UINT64_C(1149241344), // SQDMLALBT_ZZZ_S |
| 4029 | UINT64_C(1155538944), // SQDMLALB_ZZZI_D |
| 4030 | UINT64_C(1151344640), // SQDMLALB_ZZZI_S |
| 4031 | UINT64_C(1153458176), // SQDMLALB_ZZZ_D |
| 4032 | UINT64_C(1145069568), // SQDMLALB_ZZZ_H |
| 4033 | UINT64_C(1149263872), // SQDMLALB_ZZZ_S |
| 4034 | UINT64_C(1155539968), // SQDMLALT_ZZZI_D |
| 4035 | UINT64_C(1151345664), // SQDMLALT_ZZZI_S |
| 4036 | UINT64_C(1153459200), // SQDMLALT_ZZZ_D |
| 4037 | UINT64_C(1145070592), // SQDMLALT_ZZZ_H |
| 4038 | UINT64_C(1149264896), // SQDMLALT_ZZZ_S |
| 4039 | UINT64_C(1583386624), // SQDMLALi16 |
| 4040 | UINT64_C(1587580928), // SQDMLALi32 |
| 4041 | UINT64_C(1598042112), // SQDMLALv1i32_indexed |
| 4042 | UINT64_C(1602236416), // SQDMLALv1i64_indexed |
| 4043 | UINT64_C(260059136), // SQDMLALv2i32_indexed |
| 4044 | UINT64_C(245403648), // SQDMLALv2i32_v2i64 |
| 4045 | UINT64_C(255864832), // SQDMLALv4i16_indexed |
| 4046 | UINT64_C(241209344), // SQDMLALv4i16_v4i32 |
| 4047 | UINT64_C(1333800960), // SQDMLALv4i32_indexed |
| 4048 | UINT64_C(1319145472), // SQDMLALv4i32_v2i64 |
| 4049 | UINT64_C(1329606656), // SQDMLALv8i16_indexed |
| 4050 | UINT64_C(1314951168), // SQDMLALv8i16_v4i32 |
| 4051 | UINT64_C(1153436672), // SQDMLSLBT_ZZZ_D |
| 4052 | UINT64_C(1145048064), // SQDMLSLBT_ZZZ_H |
| 4053 | UINT64_C(1149242368), // SQDMLSLBT_ZZZ_S |
| 4054 | UINT64_C(1155543040), // SQDMLSLB_ZZZI_D |
| 4055 | UINT64_C(1151348736), // SQDMLSLB_ZZZI_S |
| 4056 | UINT64_C(1153460224), // SQDMLSLB_ZZZ_D |
| 4057 | UINT64_C(1145071616), // SQDMLSLB_ZZZ_H |
| 4058 | UINT64_C(1149265920), // SQDMLSLB_ZZZ_S |
| 4059 | UINT64_C(1155544064), // SQDMLSLT_ZZZI_D |
| 4060 | UINT64_C(1151349760), // SQDMLSLT_ZZZI_S |
| 4061 | UINT64_C(1153461248), // SQDMLSLT_ZZZ_D |
| 4062 | UINT64_C(1145072640), // SQDMLSLT_ZZZ_H |
| 4063 | UINT64_C(1149266944), // SQDMLSLT_ZZZ_S |
| 4064 | UINT64_C(1583394816), // SQDMLSLi16 |
| 4065 | UINT64_C(1587589120), // SQDMLSLi32 |
| 4066 | UINT64_C(1598058496), // SQDMLSLv1i32_indexed |
| 4067 | UINT64_C(1602252800), // SQDMLSLv1i64_indexed |
| 4068 | UINT64_C(260075520), // SQDMLSLv2i32_indexed |
| 4069 | UINT64_C(245411840), // SQDMLSLv2i32_v2i64 |
| 4070 | UINT64_C(255881216), // SQDMLSLv4i16_indexed |
| 4071 | UINT64_C(241217536), // SQDMLSLv4i16_v4i32 |
| 4072 | UINT64_C(1333817344), // SQDMLSLv4i32_indexed |
| 4073 | UINT64_C(1319153664), // SQDMLSLv4i32_v2i64 |
| 4074 | UINT64_C(1329623040), // SQDMLSLv8i16_indexed |
| 4075 | UINT64_C(1314959360), // SQDMLSLv8i16_v4i32 |
| 4076 | UINT64_C(1155592192), // SQDMULH_ZZZI_D |
| 4077 | UINT64_C(1143009280), // SQDMULH_ZZZI_H |
| 4078 | UINT64_C(1151397888), // SQDMULH_ZZZI_S |
| 4079 | UINT64_C(69234688), // SQDMULH_ZZZ_B |
| 4080 | UINT64_C(81817600), // SQDMULH_ZZZ_D |
| 4081 | UINT64_C(73428992), // SQDMULH_ZZZ_H |
| 4082 | UINT64_C(77623296), // SQDMULH_ZZZ_S |
| 4083 | UINT64_C(1583395840), // SQDMULHv1i16 |
| 4084 | UINT64_C(1598078976), // SQDMULHv1i16_indexed |
| 4085 | UINT64_C(1587590144), // SQDMULHv1i32 |
| 4086 | UINT64_C(1602273280), // SQDMULHv1i32_indexed |
| 4087 | UINT64_C(245412864), // SQDMULHv2i32 |
| 4088 | UINT64_C(260096000), // SQDMULHv2i32_indexed |
| 4089 | UINT64_C(241218560), // SQDMULHv4i16 |
| 4090 | UINT64_C(255901696), // SQDMULHv4i16_indexed |
| 4091 | UINT64_C(1319154688), // SQDMULHv4i32 |
| 4092 | UINT64_C(1333837824), // SQDMULHv4i32_indexed |
| 4093 | UINT64_C(1314960384), // SQDMULHv8i16 |
| 4094 | UINT64_C(1329643520), // SQDMULHv8i16_indexed |
| 4095 | UINT64_C(1155588096), // SQDMULLB_ZZZI_D |
| 4096 | UINT64_C(1151393792), // SQDMULLB_ZZZI_S |
| 4097 | UINT64_C(1170235392), // SQDMULLB_ZZZ_D |
| 4098 | UINT64_C(1161846784), // SQDMULLB_ZZZ_H |
| 4099 | UINT64_C(1166041088), // SQDMULLB_ZZZ_S |
| 4100 | UINT64_C(1155589120), // SQDMULLT_ZZZI_D |
| 4101 | UINT64_C(1151394816), // SQDMULLT_ZZZI_S |
| 4102 | UINT64_C(1170236416), // SQDMULLT_ZZZ_D |
| 4103 | UINT64_C(1161847808), // SQDMULLT_ZZZ_H |
| 4104 | UINT64_C(1166042112), // SQDMULLT_ZZZ_S |
| 4105 | UINT64_C(1583403008), // SQDMULLi16 |
| 4106 | UINT64_C(1587597312), // SQDMULLi32 |
| 4107 | UINT64_C(1598074880), // SQDMULLv1i32_indexed |
| 4108 | UINT64_C(1602269184), // SQDMULLv1i64_indexed |
| 4109 | UINT64_C(260091904), // SQDMULLv2i32_indexed |
| 4110 | UINT64_C(245420032), // SQDMULLv2i32_v2i64 |
| 4111 | UINT64_C(255897600), // SQDMULLv4i16_indexed |
| 4112 | UINT64_C(241225728), // SQDMULLv4i16_v4i32 |
| 4113 | UINT64_C(1333833728), // SQDMULLv4i32_indexed |
| 4114 | UINT64_C(1319161856), // SQDMULLv4i32_v2i64 |
| 4115 | UINT64_C(1329639424), // SQDMULLv8i16_indexed |
| 4116 | UINT64_C(1314967552), // SQDMULLv8i16_v4i32 |
| 4117 | UINT64_C(70316032), // SQINCB_XPiI |
| 4118 | UINT64_C(69267456), // SQINCB_XPiWdI |
| 4119 | UINT64_C(82898944), // SQINCD_XPiI |
| 4120 | UINT64_C(81850368), // SQINCD_XPiWdI |
| 4121 | UINT64_C(81838080), // SQINCD_ZPiI |
| 4122 | UINT64_C(74510336), // SQINCH_XPiI |
| 4123 | UINT64_C(73461760), // SQINCH_XPiWdI |
| 4124 | UINT64_C(73449472), // SQINCH_ZPiI |
| 4125 | UINT64_C(623413248), // SQINCP_XPWd_B |
| 4126 | UINT64_C(635996160), // SQINCP_XPWd_D |
| 4127 | UINT64_C(627607552), // SQINCP_XPWd_H |
| 4128 | UINT64_C(631801856), // SQINCP_XPWd_S |
| 4129 | UINT64_C(623414272), // SQINCP_XP_B |
| 4130 | UINT64_C(635997184), // SQINCP_XP_D |
| 4131 | UINT64_C(627608576), // SQINCP_XP_H |
| 4132 | UINT64_C(631802880), // SQINCP_XP_S |
| 4133 | UINT64_C(635994112), // SQINCP_ZP_D |
| 4134 | UINT64_C(627605504), // SQINCP_ZP_H |
| 4135 | UINT64_C(631799808), // SQINCP_ZP_S |
| 4136 | UINT64_C(78704640), // SQINCW_XPiI |
| 4137 | UINT64_C(77656064), // SQINCW_XPiWdI |
| 4138 | UINT64_C(77643776), // SQINCW_ZPiI |
| 4139 | UINT64_C(1141481472), // SQNEG_ZPmZ_B |
| 4140 | UINT64_C(1154064384), // SQNEG_ZPmZ_D |
| 4141 | UINT64_C(1145675776), // SQNEG_ZPmZ_H |
| 4142 | UINT64_C(1149870080), // SQNEG_ZPmZ_S |
| 4143 | UINT64_C(1847621632), // SQNEGv16i8 |
| 4144 | UINT64_C(2120251392), // SQNEGv1i16 |
| 4145 | UINT64_C(2124445696), // SQNEGv1i32 |
| 4146 | UINT64_C(2128640000), // SQNEGv1i64 |
| 4147 | UINT64_C(2116057088), // SQNEGv1i8 |
| 4148 | UINT64_C(782268416), // SQNEGv2i32 |
| 4149 | UINT64_C(1860204544), // SQNEGv2i64 |
| 4150 | UINT64_C(778074112), // SQNEGv4i16 |
| 4151 | UINT64_C(1856010240), // SQNEGv4i32 |
| 4152 | UINT64_C(1851815936), // SQNEGv8i16 |
| 4153 | UINT64_C(773879808), // SQNEGv8i8 |
| 4154 | UINT64_C(1151365120), // SQRDCMLAH_ZZZI_H |
| 4155 | UINT64_C(1155559424), // SQRDCMLAH_ZZZI_S |
| 4156 | UINT64_C(1140862976), // SQRDCMLAH_ZZZ_B |
| 4157 | UINT64_C(1153445888), // SQRDCMLAH_ZZZ_D |
| 4158 | UINT64_C(1145057280), // SQRDCMLAH_ZZZ_H |
| 4159 | UINT64_C(1149251584), // SQRDCMLAH_ZZZ_S |
| 4160 | UINT64_C(1155534848), // SQRDMLAH_ZZZI_D |
| 4161 | UINT64_C(1142951936), // SQRDMLAH_ZZZI_H |
| 4162 | UINT64_C(1151340544), // SQRDMLAH_ZZZI_S |
| 4163 | UINT64_C(1140879360), // SQRDMLAH_ZZZ_B |
| 4164 | UINT64_C(1153462272), // SQRDMLAH_ZZZ_D |
| 4165 | UINT64_C(1145073664), // SQRDMLAH_ZZZ_H |
| 4166 | UINT64_C(1149267968), // SQRDMLAH_ZZZ_S |
| 4167 | UINT64_C(2134953984), // SQRDMLAHi16_indexed |
| 4168 | UINT64_C(2139148288), // SQRDMLAHi32_indexed |
| 4169 | UINT64_C(2118157312), // SQRDMLAHv1i16 |
| 4170 | UINT64_C(2122351616), // SQRDMLAHv1i32 |
| 4171 | UINT64_C(780174336), // SQRDMLAHv2i32 |
| 4172 | UINT64_C(796971008), // SQRDMLAHv2i32_indexed |
| 4173 | UINT64_C(775980032), // SQRDMLAHv4i16 |
| 4174 | UINT64_C(792776704), // SQRDMLAHv4i16_indexed |
| 4175 | UINT64_C(1853916160), // SQRDMLAHv4i32 |
| 4176 | UINT64_C(1870712832), // SQRDMLAHv4i32_indexed |
| 4177 | UINT64_C(1849721856), // SQRDMLAHv8i16 |
| 4178 | UINT64_C(1866518528), // SQRDMLAHv8i16_indexed |
| 4179 | UINT64_C(1155535872), // SQRDMLSH_ZZZI_D |
| 4180 | UINT64_C(1142952960), // SQRDMLSH_ZZZI_H |
| 4181 | UINT64_C(1151341568), // SQRDMLSH_ZZZI_S |
| 4182 | UINT64_C(1140880384), // SQRDMLSH_ZZZ_B |
| 4183 | UINT64_C(1153463296), // SQRDMLSH_ZZZ_D |
| 4184 | UINT64_C(1145074688), // SQRDMLSH_ZZZ_H |
| 4185 | UINT64_C(1149268992), // SQRDMLSH_ZZZ_S |
| 4186 | UINT64_C(2134962176), // SQRDMLSHi16_indexed |
| 4187 | UINT64_C(2139156480), // SQRDMLSHi32_indexed |
| 4188 | UINT64_C(2118159360), // SQRDMLSHv1i16 |
| 4189 | UINT64_C(2122353664), // SQRDMLSHv1i32 |
| 4190 | UINT64_C(780176384), // SQRDMLSHv2i32 |
| 4191 | UINT64_C(796979200), // SQRDMLSHv2i32_indexed |
| 4192 | UINT64_C(775982080), // SQRDMLSHv4i16 |
| 4193 | UINT64_C(792784896), // SQRDMLSHv4i16_indexed |
| 4194 | UINT64_C(1853918208), // SQRDMLSHv4i32 |
| 4195 | UINT64_C(1870721024), // SQRDMLSHv4i32_indexed |
| 4196 | UINT64_C(1849723904), // SQRDMLSHv8i16 |
| 4197 | UINT64_C(1866526720), // SQRDMLSHv8i16_indexed |
| 4198 | UINT64_C(1155593216), // SQRDMULH_ZZZI_D |
| 4199 | UINT64_C(1143010304), // SQRDMULH_ZZZI_H |
| 4200 | UINT64_C(1151398912), // SQRDMULH_ZZZI_S |
| 4201 | UINT64_C(69235712), // SQRDMULH_ZZZ_B |
| 4202 | UINT64_C(81818624), // SQRDMULH_ZZZ_D |
| 4203 | UINT64_C(73430016), // SQRDMULH_ZZZ_H |
| 4204 | UINT64_C(77624320), // SQRDMULH_ZZZ_S |
| 4205 | UINT64_C(2120266752), // SQRDMULHv1i16 |
| 4206 | UINT64_C(1598083072), // SQRDMULHv1i16_indexed |
| 4207 | UINT64_C(2124461056), // SQRDMULHv1i32 |
| 4208 | UINT64_C(1602277376), // SQRDMULHv1i32_indexed |
| 4209 | UINT64_C(782283776), // SQRDMULHv2i32 |
| 4210 | UINT64_C(260100096), // SQRDMULHv2i32_indexed |
| 4211 | UINT64_C(778089472), // SQRDMULHv4i16 |
| 4212 | UINT64_C(255905792), // SQRDMULHv4i16_indexed |
| 4213 | UINT64_C(1856025600), // SQRDMULHv4i32 |
| 4214 | UINT64_C(1333841920), // SQRDMULHv4i32_indexed |
| 4215 | UINT64_C(1851831296), // SQRDMULHv8i16 |
| 4216 | UINT64_C(1329647616), // SQRDMULHv8i16_indexed |
| 4217 | UINT64_C(1141800960), // SQRSHLR_ZPmZ_B |
| 4218 | UINT64_C(1154383872), // SQRSHLR_ZPmZ_D |
| 4219 | UINT64_C(1145995264), // SQRSHLR_ZPmZ_H |
| 4220 | UINT64_C(1150189568), // SQRSHLR_ZPmZ_S |
| 4221 | UINT64_C(1141538816), // SQRSHL_ZPmZ_B |
| 4222 | UINT64_C(1154121728), // SQRSHL_ZPmZ_D |
| 4223 | UINT64_C(1145733120), // SQRSHL_ZPmZ_H |
| 4224 | UINT64_C(1149927424), // SQRSHL_ZPmZ_S |
| 4225 | UINT64_C(1310743552), // SQRSHLv16i8 |
| 4226 | UINT64_C(1583373312), // SQRSHLv1i16 |
| 4227 | UINT64_C(1587567616), // SQRSHLv1i32 |
| 4228 | UINT64_C(1591761920), // SQRSHLv1i64 |
| 4229 | UINT64_C(1579179008), // SQRSHLv1i8 |
| 4230 | UINT64_C(245390336), // SQRSHLv2i32 |
| 4231 | UINT64_C(1323326464), // SQRSHLv2i64 |
| 4232 | UINT64_C(241196032), // SQRSHLv4i16 |
| 4233 | UINT64_C(1319132160), // SQRSHLv4i32 |
| 4234 | UINT64_C(1314937856), // SQRSHLv8i16 |
| 4235 | UINT64_C(237001728), // SQRSHLv8i8 |
| 4236 | UINT64_C(1160259584), // SQRSHRNB_ZZI_B |
| 4237 | UINT64_C(1160783872), // SQRSHRNB_ZZI_H |
| 4238 | UINT64_C(1163929600), // SQRSHRNB_ZZI_S |
| 4239 | UINT64_C(1160260608), // SQRSHRNT_ZZI_B |
| 4240 | UINT64_C(1160784896), // SQRSHRNT_ZZI_H |
| 4241 | UINT64_C(1163930624), // SQRSHRNT_ZZI_S |
| 4242 | UINT64_C(1594399744), // SQRSHRNb |
| 4243 | UINT64_C(1594924032), // SQRSHRNh |
| 4244 | UINT64_C(1595972608), // SQRSHRNs |
| 4245 | UINT64_C(1325964288), // SQRSHRNv16i8_shift |
| 4246 | UINT64_C(253795328), // SQRSHRNv2i32_shift |
| 4247 | UINT64_C(252746752), // SQRSHRNv4i16_shift |
| 4248 | UINT64_C(1327537152), // SQRSHRNv4i32_shift |
| 4249 | UINT64_C(1326488576), // SQRSHRNv8i16_shift |
| 4250 | UINT64_C(252222464), // SQRSHRNv8i8_shift |
| 4251 | UINT64_C(1160251392), // SQRSHRUNB_ZZI_B |
| 4252 | UINT64_C(1160775680), // SQRSHRUNB_ZZI_H |
| 4253 | UINT64_C(1163921408), // SQRSHRUNB_ZZI_S |
| 4254 | UINT64_C(1160252416), // SQRSHRUNT_ZZI_B |
| 4255 | UINT64_C(1160776704), // SQRSHRUNT_ZZI_H |
| 4256 | UINT64_C(1163922432), // SQRSHRUNT_ZZI_S |
| 4257 | UINT64_C(2131266560), // SQRSHRUNb |
| 4258 | UINT64_C(2131790848), // SQRSHRUNh |
| 4259 | UINT64_C(2132839424), // SQRSHRUNs |
| 4260 | UINT64_C(1862831104), // SQRSHRUNv16i8_shift |
| 4261 | UINT64_C(790662144), // SQRSHRUNv2i32_shift |
| 4262 | UINT64_C(789613568), // SQRSHRUNv4i16_shift |
| 4263 | UINT64_C(1864403968), // SQRSHRUNv4i32_shift |
| 4264 | UINT64_C(1863355392), // SQRSHRUNv8i16_shift |
| 4265 | UINT64_C(789089280), // SQRSHRUNv8i8_shift |
| 4266 | UINT64_C(1141669888), // SQSHLR_ZPmZ_B |
| 4267 | UINT64_C(1154252800), // SQSHLR_ZPmZ_D |
| 4268 | UINT64_C(1145864192), // SQSHLR_ZPmZ_H |
| 4269 | UINT64_C(1150058496), // SQSHLR_ZPmZ_S |
| 4270 | UINT64_C(68124928), // SQSHLU_ZPmI_B |
| 4271 | UINT64_C(76513280), // SQSHLU_ZPmI_D |
| 4272 | UINT64_C(68125184), // SQSHLU_ZPmI_H |
| 4273 | UINT64_C(72318976), // SQSHLU_ZPmI_S |
| 4274 | UINT64_C(2131256320), // SQSHLUb |
| 4275 | UINT64_C(2134926336), // SQSHLUd |
| 4276 | UINT64_C(2131780608), // SQSHLUh |
| 4277 | UINT64_C(2132829184), // SQSHLUs |
| 4278 | UINT64_C(1862820864), // SQSHLUv16i8_shift |
| 4279 | UINT64_C(790651904), // SQSHLUv2i32_shift |
| 4280 | UINT64_C(1866490880), // SQSHLUv2i64_shift |
| 4281 | UINT64_C(789603328), // SQSHLUv4i16_shift |
| 4282 | UINT64_C(1864393728), // SQSHLUv4i32_shift |
| 4283 | UINT64_C(1863345152), // SQSHLUv8i16_shift |
| 4284 | UINT64_C(789079040), // SQSHLUv8i8_shift |
| 4285 | UINT64_C(67535104), // SQSHL_ZPmI_B |
| 4286 | UINT64_C(75923456), // SQSHL_ZPmI_D |
| 4287 | UINT64_C(67535360), // SQSHL_ZPmI_H |
| 4288 | UINT64_C(71729152), // SQSHL_ZPmI_S |
| 4289 | UINT64_C(1141407744), // SQSHL_ZPmZ_B |
| 4290 | UINT64_C(1153990656), // SQSHL_ZPmZ_D |
| 4291 | UINT64_C(1145602048), // SQSHL_ZPmZ_H |
| 4292 | UINT64_C(1149796352), // SQSHL_ZPmZ_S |
| 4293 | UINT64_C(1594389504), // SQSHLb |
| 4294 | UINT64_C(1598059520), // SQSHLd |
| 4295 | UINT64_C(1594913792), // SQSHLh |
| 4296 | UINT64_C(1595962368), // SQSHLs |
| 4297 | UINT64_C(1310739456), // SQSHLv16i8 |
| 4298 | UINT64_C(1325954048), // SQSHLv16i8_shift |
| 4299 | UINT64_C(1583369216), // SQSHLv1i16 |
| 4300 | UINT64_C(1587563520), // SQSHLv1i32 |
| 4301 | UINT64_C(1591757824), // SQSHLv1i64 |
| 4302 | UINT64_C(1579174912), // SQSHLv1i8 |
| 4303 | UINT64_C(245386240), // SQSHLv2i32 |
| 4304 | UINT64_C(253785088), // SQSHLv2i32_shift |
| 4305 | UINT64_C(1323322368), // SQSHLv2i64 |
| 4306 | UINT64_C(1329624064), // SQSHLv2i64_shift |
| 4307 | UINT64_C(241191936), // SQSHLv4i16 |
| 4308 | UINT64_C(252736512), // SQSHLv4i16_shift |
| 4309 | UINT64_C(1319128064), // SQSHLv4i32 |
| 4310 | UINT64_C(1327526912), // SQSHLv4i32_shift |
| 4311 | UINT64_C(1314933760), // SQSHLv8i16 |
| 4312 | UINT64_C(1326478336), // SQSHLv8i16_shift |
| 4313 | UINT64_C(236997632), // SQSHLv8i8 |
| 4314 | UINT64_C(252212224), // SQSHLv8i8_shift |
| 4315 | UINT64_C(1160257536), // SQSHRNB_ZZI_B |
| 4316 | UINT64_C(1160781824), // SQSHRNB_ZZI_H |
| 4317 | UINT64_C(1163927552), // SQSHRNB_ZZI_S |
| 4318 | UINT64_C(1160258560), // SQSHRNT_ZZI_B |
| 4319 | UINT64_C(1160782848), // SQSHRNT_ZZI_H |
| 4320 | UINT64_C(1163928576), // SQSHRNT_ZZI_S |
| 4321 | UINT64_C(1594397696), // SQSHRNb |
| 4322 | UINT64_C(1594921984), // SQSHRNh |
| 4323 | UINT64_C(1595970560), // SQSHRNs |
| 4324 | UINT64_C(1325962240), // SQSHRNv16i8_shift |
| 4325 | UINT64_C(253793280), // SQSHRNv2i32_shift |
| 4326 | UINT64_C(252744704), // SQSHRNv4i16_shift |
| 4327 | UINT64_C(1327535104), // SQSHRNv4i32_shift |
| 4328 | UINT64_C(1326486528), // SQSHRNv8i16_shift |
| 4329 | UINT64_C(252220416), // SQSHRNv8i8_shift |
| 4330 | UINT64_C(1160249344), // SQSHRUNB_ZZI_B |
| 4331 | UINT64_C(1160773632), // SQSHRUNB_ZZI_H |
| 4332 | UINT64_C(1163919360), // SQSHRUNB_ZZI_S |
| 4333 | UINT64_C(1160250368), // SQSHRUNT_ZZI_B |
| 4334 | UINT64_C(1160774656), // SQSHRUNT_ZZI_H |
| 4335 | UINT64_C(1163920384), // SQSHRUNT_ZZI_S |
| 4336 | UINT64_C(2131264512), // SQSHRUNb |
| 4337 | UINT64_C(2131788800), // SQSHRUNh |
| 4338 | UINT64_C(2132837376), // SQSHRUNs |
| 4339 | UINT64_C(1862829056), // SQSHRUNv16i8_shift |
| 4340 | UINT64_C(790660096), // SQSHRUNv2i32_shift |
| 4341 | UINT64_C(789611520), // SQSHRUNv4i16_shift |
| 4342 | UINT64_C(1864401920), // SQSHRUNv4i32_shift |
| 4343 | UINT64_C(1863353344), // SQSHRUNv8i16_shift |
| 4344 | UINT64_C(789087232), // SQSHRUNv8i8_shift |
| 4345 | UINT64_C(1142849536), // SQSUBR_ZPmZ_B |
| 4346 | UINT64_C(1155432448), // SQSUBR_ZPmZ_D |
| 4347 | UINT64_C(1147043840), // SQSUBR_ZPmZ_H |
| 4348 | UINT64_C(1151238144), // SQSUBR_ZPmZ_S |
| 4349 | UINT64_C(623296512), // SQSUB_ZI_B |
| 4350 | UINT64_C(635879424), // SQSUB_ZI_D |
| 4351 | UINT64_C(627490816), // SQSUB_ZI_H |
| 4352 | UINT64_C(631685120), // SQSUB_ZI_S |
| 4353 | UINT64_C(1142587392), // SQSUB_ZPmZ_B |
| 4354 | UINT64_C(1155170304), // SQSUB_ZPmZ_D |
| 4355 | UINT64_C(1146781696), // SQSUB_ZPmZ_H |
| 4356 | UINT64_C(1150976000), // SQSUB_ZPmZ_S |
| 4357 | UINT64_C(69212160), // SQSUB_ZZZ_B |
| 4358 | UINT64_C(81795072), // SQSUB_ZZZ_D |
| 4359 | UINT64_C(73406464), // SQSUB_ZZZ_H |
| 4360 | UINT64_C(77600768), // SQSUB_ZZZ_S |
| 4361 | UINT64_C(1310731264), // SQSUBv16i8 |
| 4362 | UINT64_C(1583361024), // SQSUBv1i16 |
| 4363 | UINT64_C(1587555328), // SQSUBv1i32 |
| 4364 | UINT64_C(1591749632), // SQSUBv1i64 |
| 4365 | UINT64_C(1579166720), // SQSUBv1i8 |
| 4366 | UINT64_C(245378048), // SQSUBv2i32 |
| 4367 | UINT64_C(1323314176), // SQSUBv2i64 |
| 4368 | UINT64_C(241183744), // SQSUBv4i16 |
| 4369 | UINT64_C(1319119872), // SQSUBv4i32 |
| 4370 | UINT64_C(1314925568), // SQSUBv8i16 |
| 4371 | UINT64_C(236989440), // SQSUBv8i8 |
| 4372 | UINT64_C(1160265728), // SQXTNB_ZZ_B |
| 4373 | UINT64_C(1160790016), // SQXTNB_ZZ_H |
| 4374 | UINT64_C(1163935744), // SQXTNB_ZZ_S |
| 4375 | UINT64_C(1160266752), // SQXTNT_ZZ_B |
| 4376 | UINT64_C(1160791040), // SQXTNT_ZZ_H |
| 4377 | UINT64_C(1163936768), // SQXTNT_ZZ_S |
| 4378 | UINT64_C(1310803968), // SQXTNv16i8 |
| 4379 | UINT64_C(1583433728), // SQXTNv1i16 |
| 4380 | UINT64_C(1587628032), // SQXTNv1i32 |
| 4381 | UINT64_C(1579239424), // SQXTNv1i8 |
| 4382 | UINT64_C(245450752), // SQXTNv2i32 |
| 4383 | UINT64_C(241256448), // SQXTNv4i16 |
| 4384 | UINT64_C(1319192576), // SQXTNv4i32 |
| 4385 | UINT64_C(1314998272), // SQXTNv8i16 |
| 4386 | UINT64_C(237062144), // SQXTNv8i8 |
| 4387 | UINT64_C(1160269824), // SQXTUNB_ZZ_B |
| 4388 | UINT64_C(1160794112), // SQXTUNB_ZZ_H |
| 4389 | UINT64_C(1163939840), // SQXTUNB_ZZ_S |
| 4390 | UINT64_C(1160270848), // SQXTUNT_ZZ_B |
| 4391 | UINT64_C(1160795136), // SQXTUNT_ZZ_H |
| 4392 | UINT64_C(1163940864), // SQXTUNT_ZZ_S |
| 4393 | UINT64_C(1847666688), // SQXTUNv16i8 |
| 4394 | UINT64_C(2120296448), // SQXTUNv1i16 |
| 4395 | UINT64_C(2124490752), // SQXTUNv1i32 |
| 4396 | UINT64_C(2116102144), // SQXTUNv1i8 |
| 4397 | UINT64_C(782313472), // SQXTUNv2i32 |
| 4398 | UINT64_C(778119168), // SQXTUNv4i16 |
| 4399 | UINT64_C(1856055296), // SQXTUNv4i32 |
| 4400 | UINT64_C(1851860992), // SQXTUNv8i16 |
| 4401 | UINT64_C(773924864), // SQXTUNv8i8 |
| 4402 | UINT64_C(1142194176), // SRHADD_ZPmZ_B |
| 4403 | UINT64_C(1154777088), // SRHADD_ZPmZ_D |
| 4404 | UINT64_C(1146388480), // SRHADD_ZPmZ_H |
| 4405 | UINT64_C(1150582784), // SRHADD_ZPmZ_S |
| 4406 | UINT64_C(1310725120), // SRHADDv16i8 |
| 4407 | UINT64_C(245371904), // SRHADDv2i32 |
| 4408 | UINT64_C(241177600), // SRHADDv4i16 |
| 4409 | UINT64_C(1319113728), // SRHADDv4i32 |
| 4410 | UINT64_C(1314919424), // SRHADDv8i16 |
| 4411 | UINT64_C(236983296), // SRHADDv8i8 |
| 4412 | UINT64_C(1158213632), // SRI_ZZI_B |
| 4413 | UINT64_C(1166077952), // SRI_ZZI_D |
| 4414 | UINT64_C(1158737920), // SRI_ZZI_H |
| 4415 | UINT64_C(1161883648), // SRI_ZZI_S |
| 4416 | UINT64_C(2134918144), // SRId |
| 4417 | UINT64_C(1862812672), // SRIv16i8_shift |
| 4418 | UINT64_C(790643712), // SRIv2i32_shift |
| 4419 | UINT64_C(1866482688), // SRIv2i64_shift |
| 4420 | UINT64_C(789595136), // SRIv4i16_shift |
| 4421 | UINT64_C(1864385536), // SRIv4i32_shift |
| 4422 | UINT64_C(1863336960), // SRIv8i16_shift |
| 4423 | UINT64_C(789070848), // SRIv8i8_shift |
| 4424 | UINT64_C(1141276672), // SRSHLR_ZPmZ_B |
| 4425 | UINT64_C(1153859584), // SRSHLR_ZPmZ_D |
| 4426 | UINT64_C(1145470976), // SRSHLR_ZPmZ_H |
| 4427 | UINT64_C(1149665280), // SRSHLR_ZPmZ_S |
| 4428 | UINT64_C(1141014528), // SRSHL_ZPmZ_B |
| 4429 | UINT64_C(1153597440), // SRSHL_ZPmZ_D |
| 4430 | UINT64_C(1145208832), // SRSHL_ZPmZ_H |
| 4431 | UINT64_C(1149403136), // SRSHL_ZPmZ_S |
| 4432 | UINT64_C(1310741504), // SRSHLv16i8 |
| 4433 | UINT64_C(1591759872), // SRSHLv1i64 |
| 4434 | UINT64_C(245388288), // SRSHLv2i32 |
| 4435 | UINT64_C(1323324416), // SRSHLv2i64 |
| 4436 | UINT64_C(241193984), // SRSHLv4i16 |
| 4437 | UINT64_C(1319130112), // SRSHLv4i32 |
| 4438 | UINT64_C(1314935808), // SRSHLv8i16 |
| 4439 | UINT64_C(236999680), // SRSHLv8i8 |
| 4440 | UINT64_C(67928320), // SRSHR_ZPmI_B |
| 4441 | UINT64_C(76316672), // SRSHR_ZPmI_D |
| 4442 | UINT64_C(67928576), // SRSHR_ZPmI_H |
| 4443 | UINT64_C(72122368), // SRSHR_ZPmI_S |
| 4444 | UINT64_C(1598039040), // SRSHRd |
| 4445 | UINT64_C(1325933568), // SRSHRv16i8_shift |
| 4446 | UINT64_C(253764608), // SRSHRv2i32_shift |
| 4447 | UINT64_C(1329603584), // SRSHRv2i64_shift |
| 4448 | UINT64_C(252716032), // SRSHRv4i16_shift |
| 4449 | UINT64_C(1327506432), // SRSHRv4i32_shift |
| 4450 | UINT64_C(1326457856), // SRSHRv8i16_shift |
| 4451 | UINT64_C(252191744), // SRSHRv8i8_shift |
| 4452 | UINT64_C(1158211584), // SRSRA_ZZI_B |
| 4453 | UINT64_C(1166075904), // SRSRA_ZZI_D |
| 4454 | UINT64_C(1158735872), // SRSRA_ZZI_H |
| 4455 | UINT64_C(1161881600), // SRSRA_ZZI_S |
| 4456 | UINT64_C(1598043136), // SRSRAd |
| 4457 | UINT64_C(1325937664), // SRSRAv16i8_shift |
| 4458 | UINT64_C(253768704), // SRSRAv2i32_shift |
| 4459 | UINT64_C(1329607680), // SRSRAv2i64_shift |
| 4460 | UINT64_C(252720128), // SRSRAv4i16_shift |
| 4461 | UINT64_C(1327510528), // SRSRAv4i32_shift |
| 4462 | UINT64_C(1326461952), // SRSRAv8i16_shift |
| 4463 | UINT64_C(252195840), // SRSRAv8i8_shift |
| 4464 | UINT64_C(1161863168), // SSHLLB_ZZI_D |
| 4465 | UINT64_C(1158193152), // SSHLLB_ZZI_H |
| 4466 | UINT64_C(1158717440), // SSHLLB_ZZI_S |
| 4467 | UINT64_C(1161864192), // SSHLLT_ZZI_D |
| 4468 | UINT64_C(1158194176), // SSHLLT_ZZI_H |
| 4469 | UINT64_C(1158718464), // SSHLLT_ZZI_S |
| 4470 | UINT64_C(1325966336), // SSHLLv16i8_shift |
| 4471 | UINT64_C(253797376), // SSHLLv2i32_shift |
| 4472 | UINT64_C(252748800), // SSHLLv4i16_shift |
| 4473 | UINT64_C(1327539200), // SSHLLv4i32_shift |
| 4474 | UINT64_C(1326490624), // SSHLLv8i16_shift |
| 4475 | UINT64_C(252224512), // SSHLLv8i8_shift |
| 4476 | UINT64_C(1310737408), // SSHLv16i8 |
| 4477 | UINT64_C(1591755776), // SSHLv1i64 |
| 4478 | UINT64_C(245384192), // SSHLv2i32 |
| 4479 | UINT64_C(1323320320), // SSHLv2i64 |
| 4480 | UINT64_C(241189888), // SSHLv4i16 |
| 4481 | UINT64_C(1319126016), // SSHLv4i32 |
| 4482 | UINT64_C(1314931712), // SSHLv8i16 |
| 4483 | UINT64_C(236995584), // SSHLv8i8 |
| 4484 | UINT64_C(1598030848), // SSHRd |
| 4485 | UINT64_C(1325925376), // SSHRv16i8_shift |
| 4486 | UINT64_C(253756416), // SSHRv2i32_shift |
| 4487 | UINT64_C(1329595392), // SSHRv2i64_shift |
| 4488 | UINT64_C(252707840), // SSHRv4i16_shift |
| 4489 | UINT64_C(1327498240), // SSHRv4i32_shift |
| 4490 | UINT64_C(1326449664), // SSHRv8i16_shift |
| 4491 | UINT64_C(252183552), // SSHRv8i8_shift |
| 4492 | UINT64_C(1158209536), // SSRA_ZZI_B |
| 4493 | UINT64_C(1166073856), // SSRA_ZZI_D |
| 4494 | UINT64_C(1158733824), // SSRA_ZZI_H |
| 4495 | UINT64_C(1161879552), // SSRA_ZZI_S |
| 4496 | UINT64_C(1598034944), // SSRAd |
| 4497 | UINT64_C(1325929472), // SSRAv16i8_shift |
| 4498 | UINT64_C(253760512), // SSRAv2i32_shift |
| 4499 | UINT64_C(1329599488), // SSRAv2i64_shift |
| 4500 | UINT64_C(252711936), // SSRAv4i16_shift |
| 4501 | UINT64_C(1327502336), // SSRAv4i32_shift |
| 4502 | UINT64_C(1326453760), // SSRAv8i16_shift |
| 4503 | UINT64_C(252187648), // SSRAv8i8_shift |
| 4504 | UINT64_C(3829440512), // SST1B_D_IMM |
| 4505 | UINT64_C(3825246208), // SST1B_D_REAL |
| 4506 | UINT64_C(3825254400), // SST1B_D_SXTW |
| 4507 | UINT64_C(3825238016), // SST1B_D_UXTW |
| 4508 | UINT64_C(3831537664), // SST1B_S_IMM |
| 4509 | UINT64_C(3829448704), // SST1B_S_SXTW |
| 4510 | UINT64_C(3829432320), // SST1B_S_UXTW |
| 4511 | UINT64_C(3854606336), // SST1D_IMM |
| 4512 | UINT64_C(3850412032), // SST1D_REAL |
| 4513 | UINT64_C(3852509184), // SST1D_SCALED_SCALED_REAL |
| 4514 | UINT64_C(3850420224), // SST1D_SXTW |
| 4515 | UINT64_C(3852517376), // SST1D_SXTW_SCALED |
| 4516 | UINT64_C(3850403840), // SST1D_UXTW |
| 4517 | UINT64_C(3852500992), // SST1D_UXTW_SCALED |
| 4518 | UINT64_C(3837829120), // SST1H_D_IMM |
| 4519 | UINT64_C(3833634816), // SST1H_D_REAL |
| 4520 | UINT64_C(3835731968), // SST1H_D_SCALED_SCALED_REAL |
| 4521 | UINT64_C(3833643008), // SST1H_D_SXTW |
| 4522 | UINT64_C(3835740160), // SST1H_D_SXTW_SCALED |
| 4523 | UINT64_C(3833626624), // SST1H_D_UXTW |
| 4524 | UINT64_C(3835723776), // SST1H_D_UXTW_SCALED |
| 4525 | UINT64_C(3839926272), // SST1H_S_IMM |
| 4526 | UINT64_C(3837837312), // SST1H_S_SXTW |
| 4527 | UINT64_C(3839934464), // SST1H_S_SXTW_SCALED |
| 4528 | UINT64_C(3837820928), // SST1H_S_UXTW |
| 4529 | UINT64_C(3839918080), // SST1H_S_UXTW_SCALED |
| 4530 | UINT64_C(3846217728), // SST1W_D_IMM |
| 4531 | UINT64_C(3842023424), // SST1W_D_REAL |
| 4532 | UINT64_C(3844120576), // SST1W_D_SCALED_SCALED_REAL |
| 4533 | UINT64_C(3842031616), // SST1W_D_SXTW |
| 4534 | UINT64_C(3844128768), // SST1W_D_SXTW_SCALED |
| 4535 | UINT64_C(3842015232), // SST1W_D_UXTW |
| 4536 | UINT64_C(3844112384), // SST1W_D_UXTW_SCALED |
| 4537 | UINT64_C(3848314880), // SST1W_IMM |
| 4538 | UINT64_C(3846225920), // SST1W_SXTW |
| 4539 | UINT64_C(3848323072), // SST1W_SXTW_SCALED |
| 4540 | UINT64_C(3846209536), // SST1W_UXTW |
| 4541 | UINT64_C(3848306688), // SST1W_UXTW_SCALED |
| 4542 | UINT64_C(1170245632), // SSUBLBT_ZZZ_D |
| 4543 | UINT64_C(1161857024), // SSUBLBT_ZZZ_H |
| 4544 | UINT64_C(1166051328), // SSUBLBT_ZZZ_S |
| 4545 | UINT64_C(1170214912), // SSUBLB_ZZZ_D |
| 4546 | UINT64_C(1161826304), // SSUBLB_ZZZ_H |
| 4547 | UINT64_C(1166020608), // SSUBLB_ZZZ_S |
| 4548 | UINT64_C(1170246656), // SSUBLTB_ZZZ_D |
| 4549 | UINT64_C(1161858048), // SSUBLTB_ZZZ_H |
| 4550 | UINT64_C(1166052352), // SSUBLTB_ZZZ_S |
| 4551 | UINT64_C(1170215936), // SSUBLT_ZZZ_D |
| 4552 | UINT64_C(1161827328), // SSUBLT_ZZZ_H |
| 4553 | UINT64_C(1166021632), // SSUBLT_ZZZ_S |
| 4554 | UINT64_C(1310728192), // SSUBLv16i8_v8i16 |
| 4555 | UINT64_C(245374976), // SSUBLv2i32_v2i64 |
| 4556 | UINT64_C(241180672), // SSUBLv4i16_v4i32 |
| 4557 | UINT64_C(1319116800), // SSUBLv4i32_v2i64 |
| 4558 | UINT64_C(1314922496), // SSUBLv8i16_v4i32 |
| 4559 | UINT64_C(236986368), // SSUBLv8i8_v8i16 |
| 4560 | UINT64_C(1170231296), // SSUBWB_ZZZ_D |
| 4561 | UINT64_C(1161842688), // SSUBWB_ZZZ_H |
| 4562 | UINT64_C(1166036992), // SSUBWB_ZZZ_S |
| 4563 | UINT64_C(1170232320), // SSUBWT_ZZZ_D |
| 4564 | UINT64_C(1161843712), // SSUBWT_ZZZ_H |
| 4565 | UINT64_C(1166038016), // SSUBWT_ZZZ_S |
| 4566 | UINT64_C(1310732288), // SSUBWv16i8_v8i16 |
| 4567 | UINT64_C(245379072), // SSUBWv2i32_v2i64 |
| 4568 | UINT64_C(241184768), // SSUBWv4i16_v4i32 |
| 4569 | UINT64_C(1319120896), // SSUBWv4i32_v2i64 |
| 4570 | UINT64_C(1314926592), // SSUBWv8i16_v4i32 |
| 4571 | UINT64_C(236990464), // SSUBWv8i8_v8i16 |
| 4572 | UINT64_C(3825221632), // ST1B |
| 4573 | UINT64_C(3831513088), // ST1B_D |
| 4574 | UINT64_C(3831554048), // ST1B_D_IMM |
| 4575 | UINT64_C(3827318784), // ST1B_H |
| 4576 | UINT64_C(3827359744), // ST1B_H_IMM |
| 4577 | UINT64_C(3825262592), // ST1B_IMM |
| 4578 | UINT64_C(3829415936), // ST1B_S |
| 4579 | UINT64_C(3829456896), // ST1B_S_IMM |
| 4580 | UINT64_C(3856678912), // ST1D |
| 4581 | UINT64_C(3856719872), // ST1D_IMM |
| 4582 | UINT64_C(1275076608), // ST1Fourv16b |
| 4583 | UINT64_C(1283465216), // ST1Fourv16b_POST |
| 4584 | UINT64_C(201337856), // ST1Fourv1d |
| 4585 | UINT64_C(209726464), // ST1Fourv1d_POST |
| 4586 | UINT64_C(1275079680), // ST1Fourv2d |
| 4587 | UINT64_C(1283468288), // ST1Fourv2d_POST |
| 4588 | UINT64_C(201336832), // ST1Fourv2s |
| 4589 | UINT64_C(209725440), // ST1Fourv2s_POST |
| 4590 | UINT64_C(201335808), // ST1Fourv4h |
| 4591 | UINT64_C(209724416), // ST1Fourv4h_POST |
| 4592 | UINT64_C(1275078656), // ST1Fourv4s |
| 4593 | UINT64_C(1283467264), // ST1Fourv4s_POST |
| 4594 | UINT64_C(201334784), // ST1Fourv8b |
| 4595 | UINT64_C(209723392), // ST1Fourv8b_POST |
| 4596 | UINT64_C(1275077632), // ST1Fourv8h |
| 4597 | UINT64_C(1283466240), // ST1Fourv8h_POST |
| 4598 | UINT64_C(3835707392), // ST1H |
| 4599 | UINT64_C(3839901696), // ST1H_D |
| 4600 | UINT64_C(3839942656), // ST1H_D_IMM |
| 4601 | UINT64_C(3835748352), // ST1H_IMM |
| 4602 | UINT64_C(3837804544), // ST1H_S |
| 4603 | UINT64_C(3837845504), // ST1H_S_IMM |
| 4604 | UINT64_C(1275097088), // ST1Onev16b |
| 4605 | UINT64_C(1283485696), // ST1Onev16b_POST |
| 4606 | UINT64_C(201358336), // ST1Onev1d |
| 4607 | UINT64_C(209746944), // ST1Onev1d_POST |
| 4608 | UINT64_C(1275100160), // ST1Onev2d |
| 4609 | UINT64_C(1283488768), // ST1Onev2d_POST |
| 4610 | UINT64_C(201357312), // ST1Onev2s |
| 4611 | UINT64_C(209745920), // ST1Onev2s_POST |
| 4612 | UINT64_C(201356288), // ST1Onev4h |
| 4613 | UINT64_C(209744896), // ST1Onev4h_POST |
| 4614 | UINT64_C(1275099136), // ST1Onev4s |
| 4615 | UINT64_C(1283487744), // ST1Onev4s_POST |
| 4616 | UINT64_C(201355264), // ST1Onev8b |
| 4617 | UINT64_C(209743872), // ST1Onev8b_POST |
| 4618 | UINT64_C(1275098112), // ST1Onev8h |
| 4619 | UINT64_C(1283486720), // ST1Onev8h_POST |
| 4620 | UINT64_C(1275092992), // ST1Threev16b |
| 4621 | UINT64_C(1283481600), // ST1Threev16b_POST |
| 4622 | UINT64_C(201354240), // ST1Threev1d |
| 4623 | UINT64_C(209742848), // ST1Threev1d_POST |
| 4624 | UINT64_C(1275096064), // ST1Threev2d |
| 4625 | UINT64_C(1283484672), // ST1Threev2d_POST |
| 4626 | UINT64_C(201353216), // ST1Threev2s |
| 4627 | UINT64_C(209741824), // ST1Threev2s_POST |
| 4628 | UINT64_C(201352192), // ST1Threev4h |
| 4629 | UINT64_C(209740800), // ST1Threev4h_POST |
| 4630 | UINT64_C(1275095040), // ST1Threev4s |
| 4631 | UINT64_C(1283483648), // ST1Threev4s_POST |
| 4632 | UINT64_C(201351168), // ST1Threev8b |
| 4633 | UINT64_C(209739776), // ST1Threev8b_POST |
| 4634 | UINT64_C(1275094016), // ST1Threev8h |
| 4635 | UINT64_C(1283482624), // ST1Threev8h_POST |
| 4636 | UINT64_C(1275109376), // ST1Twov16b |
| 4637 | UINT64_C(1283497984), // ST1Twov16b_POST |
| 4638 | UINT64_C(201370624), // ST1Twov1d |
| 4639 | UINT64_C(209759232), // ST1Twov1d_POST |
| 4640 | UINT64_C(1275112448), // ST1Twov2d |
| 4641 | UINT64_C(1283501056), // ST1Twov2d_POST |
| 4642 | UINT64_C(201369600), // ST1Twov2s |
| 4643 | UINT64_C(209758208), // ST1Twov2s_POST |
| 4644 | UINT64_C(201368576), // ST1Twov4h |
| 4645 | UINT64_C(209757184), // ST1Twov4h_POST |
| 4646 | UINT64_C(1275111424), // ST1Twov4s |
| 4647 | UINT64_C(1283500032), // ST1Twov4s_POST |
| 4648 | UINT64_C(201367552), // ST1Twov8b |
| 4649 | UINT64_C(209756160), // ST1Twov8b_POST |
| 4650 | UINT64_C(1275110400), // ST1Twov8h |
| 4651 | UINT64_C(1283499008), // ST1Twov8h_POST |
| 4652 | UINT64_C(3846193152), // ST1W |
| 4653 | UINT64_C(3848290304), // ST1W_D |
| 4654 | UINT64_C(3848331264), // ST1W_D_IMM |
| 4655 | UINT64_C(3846234112), // ST1W_IMM |
| 4656 | UINT64_C(218120192), // ST1i16 |
| 4657 | UINT64_C(226508800), // ST1i16_POST |
| 4658 | UINT64_C(218136576), // ST1i32 |
| 4659 | UINT64_C(226525184), // ST1i32_POST |
| 4660 | UINT64_C(218137600), // ST1i64 |
| 4661 | UINT64_C(226526208), // ST1i64_POST |
| 4662 | UINT64_C(218103808), // ST1i8 |
| 4663 | UINT64_C(226492416), // ST1i8_POST |
| 4664 | UINT64_C(3827326976), // ST2B |
| 4665 | UINT64_C(3828408320), // ST2B_IMM |
| 4666 | UINT64_C(3852492800), // ST2D |
| 4667 | UINT64_C(3853574144), // ST2D_IMM |
| 4668 | UINT64_C(3651143680), // ST2GOffset |
| 4669 | UINT64_C(3651142656), // ST2GPostIndex |
| 4670 | UINT64_C(3651144704), // ST2GPreIndex |
| 4671 | UINT64_C(3835715584), // ST2H |
| 4672 | UINT64_C(3836796928), // ST2H_IMM |
| 4673 | UINT64_C(1275101184), // ST2Twov16b |
| 4674 | UINT64_C(1283489792), // ST2Twov16b_POST |
| 4675 | UINT64_C(1275104256), // ST2Twov2d |
| 4676 | UINT64_C(1283492864), // ST2Twov2d_POST |
| 4677 | UINT64_C(201361408), // ST2Twov2s |
| 4678 | UINT64_C(209750016), // ST2Twov2s_POST |
| 4679 | UINT64_C(201360384), // ST2Twov4h |
| 4680 | UINT64_C(209748992), // ST2Twov4h_POST |
| 4681 | UINT64_C(1275103232), // ST2Twov4s |
| 4682 | UINT64_C(1283491840), // ST2Twov4s_POST |
| 4683 | UINT64_C(201359360), // ST2Twov8b |
| 4684 | UINT64_C(209747968), // ST2Twov8b_POST |
| 4685 | UINT64_C(1275102208), // ST2Twov8h |
| 4686 | UINT64_C(1283490816), // ST2Twov8h_POST |
| 4687 | UINT64_C(3844104192), // ST2W |
| 4688 | UINT64_C(3845185536), // ST2W_IMM |
| 4689 | UINT64_C(220217344), // ST2i16 |
| 4690 | UINT64_C(228605952), // ST2i16_POST |
| 4691 | UINT64_C(220233728), // ST2i32 |
| 4692 | UINT64_C(228622336), // ST2i32_POST |
| 4693 | UINT64_C(220234752), // ST2i64 |
| 4694 | UINT64_C(228623360), // ST2i64_POST |
| 4695 | UINT64_C(220200960), // ST2i8 |
| 4696 | UINT64_C(228589568), // ST2i8_POST |
| 4697 | UINT64_C(3829424128), // ST3B |
| 4698 | UINT64_C(3830505472), // ST3B_IMM |
| 4699 | UINT64_C(3854589952), // ST3D |
| 4700 | UINT64_C(3855671296), // ST3D_IMM |
| 4701 | UINT64_C(3837812736), // ST3H |
| 4702 | UINT64_C(3838894080), // ST3H_IMM |
| 4703 | UINT64_C(1275084800), // ST3Threev16b |
| 4704 | UINT64_C(1283473408), // ST3Threev16b_POST |
| 4705 | UINT64_C(1275087872), // ST3Threev2d |
| 4706 | UINT64_C(1283476480), // ST3Threev2d_POST |
| 4707 | UINT64_C(201345024), // ST3Threev2s |
| 4708 | UINT64_C(209733632), // ST3Threev2s_POST |
| 4709 | UINT64_C(201344000), // ST3Threev4h |
| 4710 | UINT64_C(209732608), // ST3Threev4h_POST |
| 4711 | UINT64_C(1275086848), // ST3Threev4s |
| 4712 | UINT64_C(1283475456), // ST3Threev4s_POST |
| 4713 | UINT64_C(201342976), // ST3Threev8b |
| 4714 | UINT64_C(209731584), // ST3Threev8b_POST |
| 4715 | UINT64_C(1275085824), // ST3Threev8h |
| 4716 | UINT64_C(1283474432), // ST3Threev8h_POST |
| 4717 | UINT64_C(3846201344), // ST3W |
| 4718 | UINT64_C(3847282688), // ST3W_IMM |
| 4719 | UINT64_C(218128384), // ST3i16 |
| 4720 | UINT64_C(226516992), // ST3i16_POST |
| 4721 | UINT64_C(218144768), // ST3i32 |
| 4722 | UINT64_C(226533376), // ST3i32_POST |
| 4723 | UINT64_C(218145792), // ST3i64 |
| 4724 | UINT64_C(226534400), // ST3i64_POST |
| 4725 | UINT64_C(218112000), // ST3i8 |
| 4726 | UINT64_C(226500608), // ST3i8_POST |
| 4727 | UINT64_C(3831521280), // ST4B |
| 4728 | UINT64_C(3832602624), // ST4B_IMM |
| 4729 | UINT64_C(3856687104), // ST4D |
| 4730 | UINT64_C(3857768448), // ST4D_IMM |
| 4731 | UINT64_C(1275068416), // ST4Fourv16b |
| 4732 | UINT64_C(1283457024), // ST4Fourv16b_POST |
| 4733 | UINT64_C(1275071488), // ST4Fourv2d |
| 4734 | UINT64_C(1283460096), // ST4Fourv2d_POST |
| 4735 | UINT64_C(201328640), // ST4Fourv2s |
| 4736 | UINT64_C(209717248), // ST4Fourv2s_POST |
| 4737 | UINT64_C(201327616), // ST4Fourv4h |
| 4738 | UINT64_C(209716224), // ST4Fourv4h_POST |
| 4739 | UINT64_C(1275070464), // ST4Fourv4s |
| 4740 | UINT64_C(1283459072), // ST4Fourv4s_POST |
| 4741 | UINT64_C(201326592), // ST4Fourv8b |
| 4742 | UINT64_C(209715200), // ST4Fourv8b_POST |
| 4743 | UINT64_C(1275069440), // ST4Fourv8h |
| 4744 | UINT64_C(1283458048), // ST4Fourv8h_POST |
| 4745 | UINT64_C(3839909888), // ST4H |
| 4746 | UINT64_C(3840991232), // ST4H_IMM |
| 4747 | UINT64_C(3848298496), // ST4W |
| 4748 | UINT64_C(3849379840), // ST4W_IMM |
| 4749 | UINT64_C(220225536), // ST4i16 |
| 4750 | UINT64_C(228614144), // ST4i16_POST |
| 4751 | UINT64_C(220241920), // ST4i32 |
| 4752 | UINT64_C(228630528), // ST4i32_POST |
| 4753 | UINT64_C(220242944), // ST4i64 |
| 4754 | UINT64_C(228631552), // ST4i64_POST |
| 4755 | UINT64_C(220209152), // ST4i8 |
| 4756 | UINT64_C(228597760), // ST4i8_POST |
| 4757 | UINT64_C(4164915200), // ST64B |
| 4758 | UINT64_C(4162891776), // ST64BV |
| 4759 | UINT64_C(4162887680), // ST64BV0 |
| 4760 | UINT64_C(3651141632), // STGM |
| 4761 | UINT64_C(3642755072), // STGOffset |
| 4762 | UINT64_C(1761607680), // STGPi |
| 4763 | UINT64_C(3642754048), // STGPostIndex |
| 4764 | UINT64_C(1753219072), // STGPpost |
| 4765 | UINT64_C(1769996288), // STGPpre |
| 4766 | UINT64_C(3642756096), // STGPreIndex |
| 4767 | UINT64_C(144669696), // STLLRB |
| 4768 | UINT64_C(1218411520), // STLLRH |
| 4769 | UINT64_C(2292153344), // STLLRW |
| 4770 | UINT64_C(3365895168), // STLLRX |
| 4771 | UINT64_C(144702464), // STLRB |
| 4772 | UINT64_C(1218444288), // STLRH |
| 4773 | UINT64_C(2292186112), // STLRW |
| 4774 | UINT64_C(3365927936), // STLRX |
| 4775 | UINT64_C(419430400), // STLURBi |
| 4776 | UINT64_C(1493172224), // STLURHi |
| 4777 | UINT64_C(2566914048), // STLURWi |
| 4778 | UINT64_C(3640655872), // STLURXi |
| 4779 | UINT64_C(2283831296), // STLXPW |
| 4780 | UINT64_C(3357573120), // STLXPX |
| 4781 | UINT64_C(134250496), // STLXRB |
| 4782 | UINT64_C(1207992320), // STLXRH |
| 4783 | UINT64_C(2281734144), // STLXRW |
| 4784 | UINT64_C(3355475968), // STLXRX |
| 4785 | UINT64_C(1811939328), // STNPDi |
| 4786 | UINT64_C(2885681152), // STNPQi |
| 4787 | UINT64_C(738197504), // STNPSi |
| 4788 | UINT64_C(671088640), // STNPWi |
| 4789 | UINT64_C(2818572288), // STNPXi |
| 4790 | UINT64_C(3826311168), // STNT1B_ZRI |
| 4791 | UINT64_C(3825229824), // STNT1B_ZRR |
| 4792 | UINT64_C(3825213440), // STNT1B_ZZR_D_REAL |
| 4793 | UINT64_C(3829407744), // STNT1B_ZZR_S_REAL |
| 4794 | UINT64_C(3851476992), // STNT1D_ZRI |
| 4795 | UINT64_C(3850395648), // STNT1D_ZRR |
| 4796 | UINT64_C(3850379264), // STNT1D_ZZR_D_REAL |
| 4797 | UINT64_C(3834699776), // STNT1H_ZRI |
| 4798 | UINT64_C(3833618432), // STNT1H_ZRR |
| 4799 | UINT64_C(3833602048), // STNT1H_ZZR_D_REAL |
| 4800 | UINT64_C(3837796352), // STNT1H_ZZR_S_REAL |
| 4801 | UINT64_C(3843088384), // STNT1W_ZRI |
| 4802 | UINT64_C(3842007040), // STNT1W_ZRR |
| 4803 | UINT64_C(3841990656), // STNT1W_ZZR_D_REAL |
| 4804 | UINT64_C(3846184960), // STNT1W_ZZR_S_REAL |
| 4805 | UINT64_C(1828716544), // STPDi |
| 4806 | UINT64_C(1820327936), // STPDpost |
| 4807 | UINT64_C(1837105152), // STPDpre |
| 4808 | UINT64_C(2902458368), // STPQi |
| 4809 | UINT64_C(2894069760), // STPQpost |
| 4810 | UINT64_C(2910846976), // STPQpre |
| 4811 | UINT64_C(754974720), // STPSi |
| 4812 | UINT64_C(746586112), // STPSpost |
| 4813 | UINT64_C(763363328), // STPSpre |
| 4814 | UINT64_C(687865856), // STPWi |
| 4815 | UINT64_C(679477248), // STPWpost |
| 4816 | UINT64_C(696254464), // STPWpre |
| 4817 | UINT64_C(2835349504), // STPXi |
| 4818 | UINT64_C(2826960896), // STPXpost |
| 4819 | UINT64_C(2843738112), // STPXpre |
| 4820 | UINT64_C(939525120), // STRBBpost |
| 4821 | UINT64_C(939527168), // STRBBpre |
| 4822 | UINT64_C(941639680), // STRBBroW |
| 4823 | UINT64_C(941647872), // STRBBroX |
| 4824 | UINT64_C(956301312), // STRBBui |
| 4825 | UINT64_C(1006633984), // STRBpost |
| 4826 | UINT64_C(1006636032), // STRBpre |
| 4827 | UINT64_C(1008748544), // STRBroW |
| 4828 | UINT64_C(1008756736), // STRBroX |
| 4829 | UINT64_C(1023410176), // STRBui |
| 4830 | UINT64_C(4227859456), // STRDpost |
| 4831 | UINT64_C(4227861504), // STRDpre |
| 4832 | UINT64_C(4229974016), // STRDroW |
| 4833 | UINT64_C(4229982208), // STRDroX |
| 4834 | UINT64_C(4244635648), // STRDui |
| 4835 | UINT64_C(2013266944), // STRHHpost |
| 4836 | UINT64_C(2013268992), // STRHHpre |
| 4837 | UINT64_C(2015381504), // STRHHroW |
| 4838 | UINT64_C(2015389696), // STRHHroX |
| 4839 | UINT64_C(2030043136), // STRHHui |
| 4840 | UINT64_C(2080375808), // STRHpost |
| 4841 | UINT64_C(2080377856), // STRHpre |
| 4842 | UINT64_C(2082490368), // STRHroW |
| 4843 | UINT64_C(2082498560), // STRHroX |
| 4844 | UINT64_C(2097152000), // STRHui |
| 4845 | UINT64_C(1015022592), // STRQpost |
| 4846 | UINT64_C(1015024640), // STRQpre |
| 4847 | UINT64_C(1017137152), // STRQroW |
| 4848 | UINT64_C(1017145344), // STRQroX |
| 4849 | UINT64_C(1031798784), // STRQui |
| 4850 | UINT64_C(3154117632), // STRSpost |
| 4851 | UINT64_C(3154119680), // STRSpre |
| 4852 | UINT64_C(3156232192), // STRSroW |
| 4853 | UINT64_C(3156240384), // STRSroX |
| 4854 | UINT64_C(3170893824), // STRSui |
| 4855 | UINT64_C(3087008768), // STRWpost |
| 4856 | UINT64_C(3087010816), // STRWpre |
| 4857 | UINT64_C(3089123328), // STRWroW |
| 4858 | UINT64_C(3089131520), // STRWroX |
| 4859 | UINT64_C(3103784960), // STRWui |
| 4860 | UINT64_C(4160750592), // STRXpost |
| 4861 | UINT64_C(4160752640), // STRXpre |
| 4862 | UINT64_C(4162865152), // STRXroW |
| 4863 | UINT64_C(4162873344), // STRXroX |
| 4864 | UINT64_C(4177526784), // STRXui |
| 4865 | UINT64_C(3850371072), // STR_PXI |
| 4866 | UINT64_C(3850387456), // STR_ZXI |
| 4867 | UINT64_C(939526144), // STTRBi |
| 4868 | UINT64_C(2013267968), // STTRHi |
| 4869 | UINT64_C(3087009792), // STTRWi |
| 4870 | UINT64_C(4160751616), // STTRXi |
| 4871 | UINT64_C(939524096), // STURBBi |
| 4872 | UINT64_C(1006632960), // STURBi |
| 4873 | UINT64_C(4227858432), // STURDi |
| 4874 | UINT64_C(2013265920), // STURHHi |
| 4875 | UINT64_C(2080374784), // STURHi |
| 4876 | UINT64_C(1015021568), // STURQi |
| 4877 | UINT64_C(3154116608), // STURSi |
| 4878 | UINT64_C(3087007744), // STURWi |
| 4879 | UINT64_C(4160749568), // STURXi |
| 4880 | UINT64_C(2283798528), // STXPW |
| 4881 | UINT64_C(3357540352), // STXPX |
| 4882 | UINT64_C(134217728), // STXRB |
| 4883 | UINT64_C(1207959552), // STXRH |
| 4884 | UINT64_C(2281701376), // STXRW |
| 4885 | UINT64_C(3355443200), // STXRX |
| 4886 | UINT64_C(3655337984), // STZ2GOffset |
| 4887 | UINT64_C(3655336960), // STZ2GPostIndex |
| 4888 | UINT64_C(3655339008), // STZ2GPreIndex |
| 4889 | UINT64_C(3642753024), // STZGM |
| 4890 | UINT64_C(3646949376), // STZGOffset |
| 4891 | UINT64_C(3646948352), // STZGPostIndex |
| 4892 | UINT64_C(3646950400), // STZGPreIndex |
| 4893 | UINT64_C(3514826752), // SUBG |
| 4894 | UINT64_C(1163948032), // SUBHNB_ZZZ_B |
| 4895 | UINT64_C(1168142336), // SUBHNB_ZZZ_H |
| 4896 | UINT64_C(1172336640), // SUBHNB_ZZZ_S |
| 4897 | UINT64_C(1163949056), // SUBHNT_ZZZ_B |
| 4898 | UINT64_C(1168143360), // SUBHNT_ZZZ_H |
| 4899 | UINT64_C(1172337664), // SUBHNT_ZZZ_S |
| 4900 | UINT64_C(245391360), // SUBHNv2i64_v2i32 |
| 4901 | UINT64_C(1319133184), // SUBHNv2i64_v4i32 |
| 4902 | UINT64_C(241197056), // SUBHNv4i32_v4i16 |
| 4903 | UINT64_C(1314938880), // SUBHNv4i32_v8i16 |
| 4904 | UINT64_C(1310744576), // SUBHNv8i16_v16i8 |
| 4905 | UINT64_C(237002752), // SUBHNv8i16_v8i8 |
| 4906 | UINT64_C(2596274176), // SUBP |
| 4907 | UINT64_C(3133145088), // SUBPS |
| 4908 | UINT64_C(623099904), // SUBR_ZI_B |
| 4909 | UINT64_C(635682816), // SUBR_ZI_D |
| 4910 | UINT64_C(627294208), // SUBR_ZI_H |
| 4911 | UINT64_C(631488512), // SUBR_ZI_S |
| 4912 | UINT64_C(67305472), // SUBR_ZPmZ_B |
| 4913 | UINT64_C(79888384), // SUBR_ZPmZ_D |
| 4914 | UINT64_C(71499776), // SUBR_ZPmZ_H |
| 4915 | UINT64_C(75694080), // SUBR_ZPmZ_S |
| 4916 | UINT64_C(1895825408), // SUBSWri |
| 4917 | UINT64_C(1795162112), // SUBSWrs |
| 4918 | UINT64_C(1797259264), // SUBSWrx |
| 4919 | UINT64_C(4043309056), // SUBSXri |
| 4920 | UINT64_C(3942645760), // SUBSXrs |
| 4921 | UINT64_C(3944742912), // SUBSXrx |
| 4922 | UINT64_C(3944767488), // SUBSXrx64 |
| 4923 | UINT64_C(1358954496), // SUBWri |
| 4924 | UINT64_C(1258291200), // SUBWrs |
| 4925 | UINT64_C(1260388352), // SUBWrx |
| 4926 | UINT64_C(3506438144), // SUBXri |
| 4927 | UINT64_C(3405774848), // SUBXrs |
| 4928 | UINT64_C(3407872000), // SUBXrx |
| 4929 | UINT64_C(3407896576), // SUBXrx64 |
| 4930 | UINT64_C(622968832), // SUB_ZI_B |
| 4931 | UINT64_C(635551744), // SUB_ZI_D |
| 4932 | UINT64_C(627163136), // SUB_ZI_H |
| 4933 | UINT64_C(631357440), // SUB_ZI_S |
| 4934 | UINT64_C(67174400), // SUB_ZPmZ_B |
| 4935 | UINT64_C(79757312), // SUB_ZPmZ_D |
| 4936 | UINT64_C(71368704), // SUB_ZPmZ_H |
| 4937 | UINT64_C(75563008), // SUB_ZPmZ_S |
| 4938 | UINT64_C(69207040), // SUB_ZZZ_B |
| 4939 | UINT64_C(81789952), // SUB_ZZZ_D |
| 4940 | UINT64_C(73401344), // SUB_ZZZ_H |
| 4941 | UINT64_C(77595648), // SUB_ZZZ_S |
| 4942 | UINT64_C(1847624704), // SUBv16i8 |
| 4943 | UINT64_C(2128643072), // SUBv1i64 |
| 4944 | UINT64_C(782271488), // SUBv2i32 |
| 4945 | UINT64_C(1860207616), // SUBv2i64 |
| 4946 | UINT64_C(778077184), // SUBv4i16 |
| 4947 | UINT64_C(1856013312), // SUBv4i32 |
| 4948 | UINT64_C(1851819008), // SUBv8i16 |
| 4949 | UINT64_C(773882880), // SUBv8i8 |
| 4950 | UINT64_C(1151343616), // SUDOT_ZZZI |
| 4951 | UINT64_C(1325461504), // SUDOTlanev16i8 |
| 4952 | UINT64_C(251719680), // SUDOTlanev8i8 |
| 4953 | UINT64_C(99694592), // SUNPKHI_ZZ_D |
| 4954 | UINT64_C(91305984), // SUNPKHI_ZZ_H |
| 4955 | UINT64_C(95500288), // SUNPKHI_ZZ_S |
| 4956 | UINT64_C(99629056), // SUNPKLO_ZZ_D |
| 4957 | UINT64_C(91240448), // SUNPKLO_ZZ_H |
| 4958 | UINT64_C(95434752), // SUNPKLO_ZZ_S |
| 4959 | UINT64_C(1142718464), // SUQADD_ZPmZ_B |
| 4960 | UINT64_C(1155301376), // SUQADD_ZPmZ_D |
| 4961 | UINT64_C(1146912768), // SUQADD_ZPmZ_H |
| 4962 | UINT64_C(1151107072), // SUQADD_ZPmZ_S |
| 4963 | UINT64_C(1310734336), // SUQADDv16i8 |
| 4964 | UINT64_C(1583364096), // SUQADDv1i16 |
| 4965 | UINT64_C(1587558400), // SUQADDv1i32 |
| 4966 | UINT64_C(1591752704), // SUQADDv1i64 |
| 4967 | UINT64_C(1579169792), // SUQADDv1i8 |
| 4968 | UINT64_C(245381120), // SUQADDv2i32 |
| 4969 | UINT64_C(1323317248), // SUQADDv2i64 |
| 4970 | UINT64_C(241186816), // SUQADDv4i16 |
| 4971 | UINT64_C(1319122944), // SUQADDv4i32 |
| 4972 | UINT64_C(1314928640), // SUQADDv8i16 |
| 4973 | UINT64_C(236992512), // SUQADDv8i8 |
| 4974 | UINT64_C(3556769793), // SVC |
| 4975 | UINT64_C(950042624), // SWPAB |
| 4976 | UINT64_C(2023784448), // SWPAH |
| 4977 | UINT64_C(954236928), // SWPALB |
| 4978 | UINT64_C(2027978752), // SWPALH |
| 4979 | UINT64_C(3101720576), // SWPALW |
| 4980 | UINT64_C(4175462400), // SWPALX |
| 4981 | UINT64_C(3097526272), // SWPAW |
| 4982 | UINT64_C(4171268096), // SWPAX |
| 4983 | UINT64_C(941654016), // SWPB |
| 4984 | UINT64_C(2015395840), // SWPH |
| 4985 | UINT64_C(945848320), // SWPLB |
| 4986 | UINT64_C(2019590144), // SWPLH |
| 4987 | UINT64_C(3093331968), // SWPLW |
| 4988 | UINT64_C(4167073792), // SWPLX |
| 4989 | UINT64_C(3089137664), // SWPW |
| 4990 | UINT64_C(4162879488), // SWPX |
| 4991 | UINT64_C(80781312), // SXTB_ZPmZ_D |
| 4992 | UINT64_C(72392704), // SXTB_ZPmZ_H |
| 4993 | UINT64_C(76587008), // SXTB_ZPmZ_S |
| 4994 | UINT64_C(80912384), // SXTH_ZPmZ_D |
| 4995 | UINT64_C(76718080), // SXTH_ZPmZ_S |
| 4996 | UINT64_C(81043456), // SXTW_ZPmZ_D |
| 4997 | UINT64_C(3576168448), // SYSLxt |
| 4998 | UINT64_C(3574071296), // SYSxt |
| 4999 | UINT64_C(85993472), // TBL_ZZZZ_B |
| 5000 | UINT64_C(98576384), // TBL_ZZZZ_D |
| 5001 | UINT64_C(90187776), // TBL_ZZZZ_H |
| 5002 | UINT64_C(94382080), // TBL_ZZZZ_S |
| 5003 | UINT64_C(85995520), // TBL_ZZZ_B |
| 5004 | UINT64_C(98578432), // TBL_ZZZ_D |
| 5005 | UINT64_C(90189824), // TBL_ZZZ_H |
| 5006 | UINT64_C(94384128), // TBL_ZZZ_S |
| 5007 | UINT64_C(1308647424), // TBLv16i8Four |
| 5008 | UINT64_C(1308622848), // TBLv16i8One |
| 5009 | UINT64_C(1308639232), // TBLv16i8Three |
| 5010 | UINT64_C(1308631040), // TBLv16i8Two |
| 5011 | UINT64_C(234905600), // TBLv8i8Four |
| 5012 | UINT64_C(234881024), // TBLv8i8One |
| 5013 | UINT64_C(234897408), // TBLv8i8Three |
| 5014 | UINT64_C(234889216), // TBLv8i8Two |
| 5015 | UINT64_C(922746880), // TBNZW |
| 5016 | UINT64_C(3070230528), // TBNZX |
| 5017 | UINT64_C(85994496), // TBX_ZZZ_B |
| 5018 | UINT64_C(98577408), // TBX_ZZZ_D |
| 5019 | UINT64_C(90188800), // TBX_ZZZ_H |
| 5020 | UINT64_C(94383104), // TBX_ZZZ_S |
| 5021 | UINT64_C(1308651520), // TBXv16i8Four |
| 5022 | UINT64_C(1308626944), // TBXv16i8One |
| 5023 | UINT64_C(1308643328), // TBXv16i8Three |
| 5024 | UINT64_C(1308635136), // TBXv16i8Two |
| 5025 | UINT64_C(234909696), // TBXv8i8Four |
| 5026 | UINT64_C(234885120), // TBXv8i8One |
| 5027 | UINT64_C(234901504), // TBXv8i8Three |
| 5028 | UINT64_C(234893312), // TBXv8i8Two |
| 5029 | UINT64_C(905969664), // TBZW |
| 5030 | UINT64_C(3053453312), // TBZX |
| 5031 | UINT64_C(3563061248), // TCANCEL |
| 5032 | UINT64_C(3573756031), // TCOMMIT |
| 5033 | UINT64_C(86003712), // TRN1_PPP_B |
| 5034 | UINT64_C(98586624), // TRN1_PPP_D |
| 5035 | UINT64_C(90198016), // TRN1_PPP_H |
| 5036 | UINT64_C(94392320), // TRN1_PPP_S |
| 5037 | UINT64_C(86011904), // TRN1_ZZZ_B |
| 5038 | UINT64_C(98594816), // TRN1_ZZZ_D |
| 5039 | UINT64_C(90206208), // TRN1_ZZZ_H |
| 5040 | UINT64_C(94377984), // TRN1_ZZZ_Q |
| 5041 | UINT64_C(94400512), // TRN1_ZZZ_S |
| 5042 | UINT64_C(1308633088), // TRN1v16i8 |
| 5043 | UINT64_C(243279872), // TRN1v2i32 |
| 5044 | UINT64_C(1321216000), // TRN1v2i64 |
| 5045 | UINT64_C(239085568), // TRN1v4i16 |
| 5046 | UINT64_C(1317021696), // TRN1v4i32 |
| 5047 | UINT64_C(1312827392), // TRN1v8i16 |
| 5048 | UINT64_C(234891264), // TRN1v8i8 |
| 5049 | UINT64_C(86004736), // TRN2_PPP_B |
| 5050 | UINT64_C(98587648), // TRN2_PPP_D |
| 5051 | UINT64_C(90199040), // TRN2_PPP_H |
| 5052 | UINT64_C(94393344), // TRN2_PPP_S |
| 5053 | UINT64_C(86012928), // TRN2_ZZZ_B |
| 5054 | UINT64_C(98595840), // TRN2_ZZZ_D |
| 5055 | UINT64_C(90207232), // TRN2_ZZZ_H |
| 5056 | UINT64_C(94379008), // TRN2_ZZZ_Q |
| 5057 | UINT64_C(94401536), // TRN2_ZZZ_S |
| 5058 | UINT64_C(1308649472), // TRN2v16i8 |
| 5059 | UINT64_C(243296256), // TRN2v2i32 |
| 5060 | UINT64_C(1321232384), // TRN2v2i64 |
| 5061 | UINT64_C(239101952), // TRN2v4i16 |
| 5062 | UINT64_C(1317038080), // TRN2v4i32 |
| 5063 | UINT64_C(1312843776), // TRN2v8i16 |
| 5064 | UINT64_C(234907648), // TRN2v8i8 |
| 5065 | UINT64_C(3573752415), // TSB |
| 5066 | UINT64_C(3575853152), // TSTART |
| 5067 | UINT64_C(3575853408), // TTEST |
| 5068 | UINT64_C(1170262016), // UABALB_ZZZ_D |
| 5069 | UINT64_C(1161873408), // UABALB_ZZZ_H |
| 5070 | UINT64_C(1166067712), // UABALB_ZZZ_S |
| 5071 | UINT64_C(1170263040), // UABALT_ZZZ_D |
| 5072 | UINT64_C(1161874432), // UABALT_ZZZ_H |
| 5073 | UINT64_C(1166068736), // UABALT_ZZZ_S |
| 5074 | UINT64_C(1847611392), // UABALv16i8_v8i16 |
| 5075 | UINT64_C(782258176), // UABALv2i32_v2i64 |
| 5076 | UINT64_C(778063872), // UABALv4i16_v4i32 |
| 5077 | UINT64_C(1856000000), // UABALv4i32_v2i64 |
| 5078 | UINT64_C(1851805696), // UABALv8i16_v4i32 |
| 5079 | UINT64_C(773869568), // UABALv8i8_v8i16 |
| 5080 | UINT64_C(1157692416), // UABA_ZZZ_B |
| 5081 | UINT64_C(1170275328), // UABA_ZZZ_D |
| 5082 | UINT64_C(1161886720), // UABA_ZZZ_H |
| 5083 | UINT64_C(1166081024), // UABA_ZZZ_S |
| 5084 | UINT64_C(1847622656), // UABAv16i8 |
| 5085 | UINT64_C(782269440), // UABAv2i32 |
| 5086 | UINT64_C(778075136), // UABAv4i16 |
| 5087 | UINT64_C(1856011264), // UABAv4i32 |
| 5088 | UINT64_C(1851816960), // UABAv8i16 |
| 5089 | UINT64_C(773880832), // UABAv8i8 |
| 5090 | UINT64_C(1170225152), // UABDLB_ZZZ_D |
| 5091 | UINT64_C(1161836544), // UABDLB_ZZZ_H |
| 5092 | UINT64_C(1166030848), // UABDLB_ZZZ_S |
| 5093 | UINT64_C(1170226176), // UABDLT_ZZZ_D |
| 5094 | UINT64_C(1161837568), // UABDLT_ZZZ_H |
| 5095 | UINT64_C(1166031872), // UABDLT_ZZZ_S |
| 5096 | UINT64_C(1847619584), // UABDLv16i8_v8i16 |
| 5097 | UINT64_C(782266368), // UABDLv2i32_v2i64 |
| 5098 | UINT64_C(778072064), // UABDLv4i16_v4i32 |
| 5099 | UINT64_C(1856008192), // UABDLv4i32_v2i64 |
| 5100 | UINT64_C(1851813888), // UABDLv8i16_v4i32 |
| 5101 | UINT64_C(773877760), // UABDLv8i8_v8i16 |
| 5102 | UINT64_C(67960832), // UABD_ZPmZ_B |
| 5103 | UINT64_C(80543744), // UABD_ZPmZ_D |
| 5104 | UINT64_C(72155136), // UABD_ZPmZ_H |
| 5105 | UINT64_C(76349440), // UABD_ZPmZ_S |
| 5106 | UINT64_C(1847620608), // UABDv16i8 |
| 5107 | UINT64_C(782267392), // UABDv2i32 |
| 5108 | UINT64_C(778073088), // UABDv4i16 |
| 5109 | UINT64_C(1856009216), // UABDv4i32 |
| 5110 | UINT64_C(1851814912), // UABDv8i16 |
| 5111 | UINT64_C(773878784), // UABDv8i8 |
| 5112 | UINT64_C(1153802240), // UADALP_ZPmZ_D |
| 5113 | UINT64_C(1145413632), // UADALP_ZPmZ_H |
| 5114 | UINT64_C(1149607936), // UADALP_ZPmZ_S |
| 5115 | UINT64_C(1847617536), // UADALPv16i8_v8i16 |
| 5116 | UINT64_C(782264320), // UADALPv2i32_v1i64 |
| 5117 | UINT64_C(778070016), // UADALPv4i16_v2i32 |
| 5118 | UINT64_C(1856006144), // UADALPv4i32_v2i64 |
| 5119 | UINT64_C(1851811840), // UADALPv8i16_v4i32 |
| 5120 | UINT64_C(773875712), // UADALPv8i8_v4i16 |
| 5121 | UINT64_C(1170212864), // UADDLB_ZZZ_D |
| 5122 | UINT64_C(1161824256), // UADDLB_ZZZ_H |
| 5123 | UINT64_C(1166018560), // UADDLB_ZZZ_S |
| 5124 | UINT64_C(1847601152), // UADDLPv16i8_v8i16 |
| 5125 | UINT64_C(782247936), // UADDLPv2i32_v1i64 |
| 5126 | UINT64_C(778053632), // UADDLPv4i16_v2i32 |
| 5127 | UINT64_C(1855989760), // UADDLPv4i32_v2i64 |
| 5128 | UINT64_C(1851795456), // UADDLPv8i16_v4i32 |
| 5129 | UINT64_C(773859328), // UADDLPv8i8_v4i16 |
| 5130 | UINT64_C(1170213888), // UADDLT_ZZZ_D |
| 5131 | UINT64_C(1161825280), // UADDLT_ZZZ_H |
| 5132 | UINT64_C(1166019584), // UADDLT_ZZZ_S |
| 5133 | UINT64_C(1848653824), // UADDLVv16i8v |
| 5134 | UINT64_C(779106304), // UADDLVv4i16v |
| 5135 | UINT64_C(1857042432), // UADDLVv4i32v |
| 5136 | UINT64_C(1852848128), // UADDLVv8i16v |
| 5137 | UINT64_C(774912000), // UADDLVv8i8v |
| 5138 | UINT64_C(1847590912), // UADDLv16i8_v8i16 |
| 5139 | UINT64_C(782237696), // UADDLv2i32_v2i64 |
| 5140 | UINT64_C(778043392), // UADDLv4i16_v4i32 |
| 5141 | UINT64_C(1855979520), // UADDLv4i32_v2i64 |
| 5142 | UINT64_C(1851785216), // UADDLv8i16_v4i32 |
| 5143 | UINT64_C(773849088), // UADDLv8i8_v8i16 |
| 5144 | UINT64_C(67182592), // UADDV_VPZ_B |
| 5145 | UINT64_C(79765504), // UADDV_VPZ_D |
| 5146 | UINT64_C(71376896), // UADDV_VPZ_H |
| 5147 | UINT64_C(75571200), // UADDV_VPZ_S |
| 5148 | UINT64_C(1170229248), // UADDWB_ZZZ_D |
| 5149 | UINT64_C(1161840640), // UADDWB_ZZZ_H |
| 5150 | UINT64_C(1166034944), // UADDWB_ZZZ_S |
| 5151 | UINT64_C(1170230272), // UADDWT_ZZZ_D |
| 5152 | UINT64_C(1161841664), // UADDWT_ZZZ_H |
| 5153 | UINT64_C(1166035968), // UADDWT_ZZZ_S |
| 5154 | UINT64_C(1847595008), // UADDWv16i8_v8i16 |
| 5155 | UINT64_C(782241792), // UADDWv2i32_v2i64 |
| 5156 | UINT64_C(778047488), // UADDWv4i16_v4i32 |
| 5157 | UINT64_C(1855983616), // UADDWv4i32_v2i64 |
| 5158 | UINT64_C(1851789312), // UADDWv8i16_v4i32 |
| 5159 | UINT64_C(773853184), // UADDWv8i8_v8i16 |
| 5160 | UINT64_C(1392508928), // UBFMWri |
| 5161 | UINT64_C(3544186880), // UBFMXri |
| 5162 | UINT64_C(507740160), // UCVTFSWDri |
| 5163 | UINT64_C(516128768), // UCVTFSWHri |
| 5164 | UINT64_C(503545856), // UCVTFSWSri |
| 5165 | UINT64_C(2655191040), // UCVTFSXDri |
| 5166 | UINT64_C(2663579648), // UCVTFSXHri |
| 5167 | UINT64_C(2650996736), // UCVTFSXSri |
| 5168 | UINT64_C(509804544), // UCVTFUWDri |
| 5169 | UINT64_C(518193152), // UCVTFUWHri |
| 5170 | UINT64_C(505610240), // UCVTFUWSri |
| 5171 | UINT64_C(2657288192), // UCVTFUXDri |
| 5172 | UINT64_C(2665676800), // UCVTFUXHri |
| 5173 | UINT64_C(2653093888), // UCVTFUXSri |
| 5174 | UINT64_C(1708630016), // UCVTF_ZPmZ_DtoD |
| 5175 | UINT64_C(1700241408), // UCVTF_ZPmZ_DtoH |
| 5176 | UINT64_C(1708498944), // UCVTF_ZPmZ_DtoS |
| 5177 | UINT64_C(1699979264), // UCVTF_ZPmZ_HtoH |
| 5178 | UINT64_C(1708236800), // UCVTF_ZPmZ_StoD |
| 5179 | UINT64_C(1700110336), // UCVTF_ZPmZ_StoH |
| 5180 | UINT64_C(1704304640), // UCVTF_ZPmZ_StoS |
| 5181 | UINT64_C(2134959104), // UCVTFd |
| 5182 | UINT64_C(2131813376), // UCVTFh |
| 5183 | UINT64_C(2132861952), // UCVTFs |
| 5184 | UINT64_C(2121914368), // UCVTFv1i16 |
| 5185 | UINT64_C(2116147200), // UCVTFv1i32 |
| 5186 | UINT64_C(2120341504), // UCVTFv1i64 |
| 5187 | UINT64_C(773969920), // UCVTFv2f32 |
| 5188 | UINT64_C(1851906048), // UCVTFv2f64 |
| 5189 | UINT64_C(790684672), // UCVTFv2i32_shift |
| 5190 | UINT64_C(1866523648), // UCVTFv2i64_shift |
| 5191 | UINT64_C(779737088), // UCVTFv4f16 |
| 5192 | UINT64_C(1847711744), // UCVTFv4f32 |
| 5193 | UINT64_C(789636096), // UCVTFv4i16_shift |
| 5194 | UINT64_C(1864426496), // UCVTFv4i32_shift |
| 5195 | UINT64_C(1853478912), // UCVTFv8f16 |
| 5196 | UINT64_C(1863377920), // UCVTFv8i16_shift |
| 5197 | UINT64_C(0), // UDF |
| 5198 | UINT64_C(81199104), // UDIVR_ZPmZ_D |
| 5199 | UINT64_C(77004800), // UDIVR_ZPmZ_S |
| 5200 | UINT64_C(448792576), // UDIVWr |
| 5201 | UINT64_C(2596276224), // UDIVXr |
| 5202 | UINT64_C(81068032), // UDIV_ZPmZ_D |
| 5203 | UINT64_C(76873728), // UDIV_ZPmZ_S |
| 5204 | UINT64_C(1155531776), // UDOT_ZZZI_D |
| 5205 | UINT64_C(1151337472), // UDOT_ZZZI_S |
| 5206 | UINT64_C(1153434624), // UDOT_ZZZ_D |
| 5207 | UINT64_C(1149240320), // UDOT_ZZZ_S |
| 5208 | UINT64_C(1870716928), // UDOTlanev16i8 |
| 5209 | UINT64_C(796975104), // UDOTlanev8i8 |
| 5210 | UINT64_C(1853920256), // UDOTv16i8 |
| 5211 | UINT64_C(780178432), // UDOTv8i8 |
| 5212 | UINT64_C(1141997568), // UHADD_ZPmZ_B |
| 5213 | UINT64_C(1154580480), // UHADD_ZPmZ_D |
| 5214 | UINT64_C(1146191872), // UHADD_ZPmZ_H |
| 5215 | UINT64_C(1150386176), // UHADD_ZPmZ_S |
| 5216 | UINT64_C(1847591936), // UHADDv16i8 |
| 5217 | UINT64_C(782238720), // UHADDv2i32 |
| 5218 | UINT64_C(778044416), // UHADDv4i16 |
| 5219 | UINT64_C(1855980544), // UHADDv4i32 |
| 5220 | UINT64_C(1851786240), // UHADDv8i16 |
| 5221 | UINT64_C(773850112), // UHADDv8i8 |
| 5222 | UINT64_C(1142390784), // UHSUBR_ZPmZ_B |
| 5223 | UINT64_C(1154973696), // UHSUBR_ZPmZ_D |
| 5224 | UINT64_C(1146585088), // UHSUBR_ZPmZ_H |
| 5225 | UINT64_C(1150779392), // UHSUBR_ZPmZ_S |
| 5226 | UINT64_C(1142128640), // UHSUB_ZPmZ_B |
| 5227 | UINT64_C(1154711552), // UHSUB_ZPmZ_D |
| 5228 | UINT64_C(1146322944), // UHSUB_ZPmZ_H |
| 5229 | UINT64_C(1150517248), // UHSUB_ZPmZ_S |
| 5230 | UINT64_C(1847600128), // UHSUBv16i8 |
| 5231 | UINT64_C(782246912), // UHSUBv2i32 |
| 5232 | UINT64_C(778052608), // UHSUBv4i16 |
| 5233 | UINT64_C(1855988736), // UHSUBv4i32 |
| 5234 | UINT64_C(1851794432), // UHSUBv8i16 |
| 5235 | UINT64_C(773858304), // UHSUBv8i8 |
| 5236 | UINT64_C(2610954240), // UMADDLrrr |
| 5237 | UINT64_C(1142267904), // UMAXP_ZPmZ_B |
| 5238 | UINT64_C(1154850816), // UMAXP_ZPmZ_D |
| 5239 | UINT64_C(1146462208), // UMAXP_ZPmZ_H |
| 5240 | UINT64_C(1150656512), // UMAXP_ZPmZ_S |
| 5241 | UINT64_C(1847632896), // UMAXPv16i8 |
| 5242 | UINT64_C(782279680), // UMAXPv2i32 |
| 5243 | UINT64_C(778085376), // UMAXPv4i16 |
| 5244 | UINT64_C(1856021504), // UMAXPv4i32 |
| 5245 | UINT64_C(1851827200), // UMAXPv8i16 |
| 5246 | UINT64_C(773891072), // UMAXPv8i8 |
| 5247 | UINT64_C(67706880), // UMAXV_VPZ_B |
| 5248 | UINT64_C(80289792), // UMAXV_VPZ_D |
| 5249 | UINT64_C(71901184), // UMAXV_VPZ_H |
| 5250 | UINT64_C(76095488), // UMAXV_VPZ_S |
| 5251 | UINT64_C(1848682496), // UMAXVv16i8v |
| 5252 | UINT64_C(779134976), // UMAXVv4i16v |
| 5253 | UINT64_C(1857071104), // UMAXVv4i32v |
| 5254 | UINT64_C(1852876800), // UMAXVv8i16v |
| 5255 | UINT64_C(774940672), // UMAXVv8i8v |
| 5256 | UINT64_C(623493120), // UMAX_ZI_B |
| 5257 | UINT64_C(636076032), // UMAX_ZI_D |
| 5258 | UINT64_C(627687424), // UMAX_ZI_H |
| 5259 | UINT64_C(631881728), // UMAX_ZI_S |
| 5260 | UINT64_C(67698688), // UMAX_ZPmZ_B |
| 5261 | UINT64_C(80281600), // UMAX_ZPmZ_D |
| 5262 | UINT64_C(71892992), // UMAX_ZPmZ_H |
| 5263 | UINT64_C(76087296), // UMAX_ZPmZ_S |
| 5264 | UINT64_C(1847616512), // UMAXv16i8 |
| 5265 | UINT64_C(782263296), // UMAXv2i32 |
| 5266 | UINT64_C(778068992), // UMAXv4i16 |
| 5267 | UINT64_C(1856005120), // UMAXv4i32 |
| 5268 | UINT64_C(1851810816), // UMAXv8i16 |
| 5269 | UINT64_C(773874688), // UMAXv8i8 |
| 5270 | UINT64_C(1142398976), // UMINP_ZPmZ_B |
| 5271 | UINT64_C(1154981888), // UMINP_ZPmZ_D |
| 5272 | UINT64_C(1146593280), // UMINP_ZPmZ_H |
| 5273 | UINT64_C(1150787584), // UMINP_ZPmZ_S |
| 5274 | UINT64_C(1847634944), // UMINPv16i8 |
| 5275 | UINT64_C(782281728), // UMINPv2i32 |
| 5276 | UINT64_C(778087424), // UMINPv4i16 |
| 5277 | UINT64_C(1856023552), // UMINPv4i32 |
| 5278 | UINT64_C(1851829248), // UMINPv8i16 |
| 5279 | UINT64_C(773893120), // UMINPv8i8 |
| 5280 | UINT64_C(67837952), // UMINV_VPZ_B |
| 5281 | UINT64_C(80420864), // UMINV_VPZ_D |
| 5282 | UINT64_C(72032256), // UMINV_VPZ_H |
| 5283 | UINT64_C(76226560), // UMINV_VPZ_S |
| 5284 | UINT64_C(1848748032), // UMINVv16i8v |
| 5285 | UINT64_C(779200512), // UMINVv4i16v |
| 5286 | UINT64_C(1857136640), // UMINVv4i32v |
| 5287 | UINT64_C(1852942336), // UMINVv8i16v |
| 5288 | UINT64_C(775006208), // UMINVv8i8v |
| 5289 | UINT64_C(623624192), // UMIN_ZI_B |
| 5290 | UINT64_C(636207104), // UMIN_ZI_D |
| 5291 | UINT64_C(627818496), // UMIN_ZI_H |
| 5292 | UINT64_C(632012800), // UMIN_ZI_S |
| 5293 | UINT64_C(67829760), // UMIN_ZPmZ_B |
| 5294 | UINT64_C(80412672), // UMIN_ZPmZ_D |
| 5295 | UINT64_C(72024064), // UMIN_ZPmZ_H |
| 5296 | UINT64_C(76218368), // UMIN_ZPmZ_S |
| 5297 | UINT64_C(1847618560), // UMINv16i8 |
| 5298 | UINT64_C(782265344), // UMINv2i32 |
| 5299 | UINT64_C(778071040), // UMINv4i16 |
| 5300 | UINT64_C(1856007168), // UMINv4i32 |
| 5301 | UINT64_C(1851812864), // UMINv8i16 |
| 5302 | UINT64_C(773876736), // UMINv8i8 |
| 5303 | UINT64_C(1155567616), // UMLALB_ZZZI_D |
| 5304 | UINT64_C(1151373312), // UMLALB_ZZZI_S |
| 5305 | UINT64_C(1153452032), // UMLALB_ZZZ_D |
| 5306 | UINT64_C(1145063424), // UMLALB_ZZZ_H |
| 5307 | UINT64_C(1149257728), // UMLALB_ZZZ_S |
| 5308 | UINT64_C(1155568640), // UMLALT_ZZZI_D |
| 5309 | UINT64_C(1151374336), // UMLALT_ZZZI_S |
| 5310 | UINT64_C(1153453056), // UMLALT_ZZZ_D |
| 5311 | UINT64_C(1145064448), // UMLALT_ZZZ_H |
| 5312 | UINT64_C(1149258752), // UMLALT_ZZZ_S |
| 5313 | UINT64_C(1847623680), // UMLALv16i8_v8i16 |
| 5314 | UINT64_C(796925952), // UMLALv2i32_indexed |
| 5315 | UINT64_C(782270464), // UMLALv2i32_v2i64 |
| 5316 | UINT64_C(792731648), // UMLALv4i16_indexed |
| 5317 | UINT64_C(778076160), // UMLALv4i16_v4i32 |
| 5318 | UINT64_C(1870667776), // UMLALv4i32_indexed |
| 5319 | UINT64_C(1856012288), // UMLALv4i32_v2i64 |
| 5320 | UINT64_C(1866473472), // UMLALv8i16_indexed |
| 5321 | UINT64_C(1851817984), // UMLALv8i16_v4i32 |
| 5322 | UINT64_C(773881856), // UMLALv8i8_v8i16 |
| 5323 | UINT64_C(1155575808), // UMLSLB_ZZZI_D |
| 5324 | UINT64_C(1151381504), // UMLSLB_ZZZI_S |
| 5325 | UINT64_C(1153456128), // UMLSLB_ZZZ_D |
| 5326 | UINT64_C(1145067520), // UMLSLB_ZZZ_H |
| 5327 | UINT64_C(1149261824), // UMLSLB_ZZZ_S |
| 5328 | UINT64_C(1155576832), // UMLSLT_ZZZI_D |
| 5329 | UINT64_C(1151382528), // UMLSLT_ZZZI_S |
| 5330 | UINT64_C(1153457152), // UMLSLT_ZZZ_D |
| 5331 | UINT64_C(1145068544), // UMLSLT_ZZZ_H |
| 5332 | UINT64_C(1149262848), // UMLSLT_ZZZ_S |
| 5333 | UINT64_C(1847631872), // UMLSLv16i8_v8i16 |
| 5334 | UINT64_C(796942336), // UMLSLv2i32_indexed |
| 5335 | UINT64_C(782278656), // UMLSLv2i32_v2i64 |
| 5336 | UINT64_C(792748032), // UMLSLv4i16_indexed |
| 5337 | UINT64_C(778084352), // UMLSLv4i16_v4i32 |
| 5338 | UINT64_C(1870684160), // UMLSLv4i32_indexed |
| 5339 | UINT64_C(1856020480), // UMLSLv4i32_v2i64 |
| 5340 | UINT64_C(1866489856), // UMLSLv8i16_indexed |
| 5341 | UINT64_C(1851826176), // UMLSLv8i16_v4i32 |
| 5342 | UINT64_C(773890048), // UMLSLv8i8_v8i16 |
| 5343 | UINT64_C(1853924352), // UMMLA |
| 5344 | UINT64_C(1170249728), // UMMLA_ZZZ |
| 5345 | UINT64_C(235027456), // UMOVvi16 |
| 5346 | UINT64_C(235158528), // UMOVvi32 |
| 5347 | UINT64_C(1309162496), // UMOVvi64 |
| 5348 | UINT64_C(234961920), // UMOVvi8 |
| 5349 | UINT64_C(2610987008), // UMSUBLrrr |
| 5350 | UINT64_C(68354048), // UMULH_ZPmZ_B |
| 5351 | UINT64_C(80936960), // UMULH_ZPmZ_D |
| 5352 | UINT64_C(72548352), // UMULH_ZPmZ_H |
| 5353 | UINT64_C(76742656), // UMULH_ZPmZ_S |
| 5354 | UINT64_C(69233664), // UMULH_ZZZ_B |
| 5355 | UINT64_C(81816576), // UMULH_ZZZ_D |
| 5356 | UINT64_C(73427968), // UMULH_ZZZ_H |
| 5357 | UINT64_C(77622272), // UMULH_ZZZ_S |
| 5358 | UINT64_C(2613051392), // UMULHrr |
| 5359 | UINT64_C(1155584000), // UMULLB_ZZZI_D |
| 5360 | UINT64_C(1151389696), // UMULLB_ZZZI_S |
| 5361 | UINT64_C(1170241536), // UMULLB_ZZZ_D |
| 5362 | UINT64_C(1161852928), // UMULLB_ZZZ_H |
| 5363 | UINT64_C(1166047232), // UMULLB_ZZZ_S |
| 5364 | UINT64_C(1155585024), // UMULLT_ZZZI_D |
| 5365 | UINT64_C(1151390720), // UMULLT_ZZZI_S |
| 5366 | UINT64_C(1170242560), // UMULLT_ZZZ_D |
| 5367 | UINT64_C(1161853952), // UMULLT_ZZZ_H |
| 5368 | UINT64_C(1166048256), // UMULLT_ZZZ_S |
| 5369 | UINT64_C(1847640064), // UMULLv16i8_v8i16 |
| 5370 | UINT64_C(796958720), // UMULLv2i32_indexed |
| 5371 | UINT64_C(782286848), // UMULLv2i32_v2i64 |
| 5372 | UINT64_C(792764416), // UMULLv4i16_indexed |
| 5373 | UINT64_C(778092544), // UMULLv4i16_v4i32 |
| 5374 | UINT64_C(1870700544), // UMULLv4i32_indexed |
| 5375 | UINT64_C(1856028672), // UMULLv4i32_v2i64 |
| 5376 | UINT64_C(1866506240), // UMULLv8i16_indexed |
| 5377 | UINT64_C(1851834368), // UMULLv8i16_v4i32 |
| 5378 | UINT64_C(773898240), // UMULLv8i8_v8i16 |
| 5379 | UINT64_C(623230976), // UQADD_ZI_B |
| 5380 | UINT64_C(635813888), // UQADD_ZI_D |
| 5381 | UINT64_C(627425280), // UQADD_ZI_H |
| 5382 | UINT64_C(631619584), // UQADD_ZI_S |
| 5383 | UINT64_C(1142521856), // UQADD_ZPmZ_B |
| 5384 | UINT64_C(1155104768), // UQADD_ZPmZ_D |
| 5385 | UINT64_C(1146716160), // UQADD_ZPmZ_H |
| 5386 | UINT64_C(1150910464), // UQADD_ZPmZ_S |
| 5387 | UINT64_C(69211136), // UQADD_ZZZ_B |
| 5388 | UINT64_C(81794048), // UQADD_ZZZ_D |
| 5389 | UINT64_C(73405440), // UQADD_ZZZ_H |
| 5390 | UINT64_C(77599744), // UQADD_ZZZ_S |
| 5391 | UINT64_C(1847593984), // UQADDv16i8 |
| 5392 | UINT64_C(2120223744), // UQADDv1i16 |
| 5393 | UINT64_C(2124418048), // UQADDv1i32 |
| 5394 | UINT64_C(2128612352), // UQADDv1i64 |
| 5395 | UINT64_C(2116029440), // UQADDv1i8 |
| 5396 | UINT64_C(782240768), // UQADDv2i32 |
| 5397 | UINT64_C(1860176896), // UQADDv2i64 |
| 5398 | UINT64_C(778046464), // UQADDv4i16 |
| 5399 | UINT64_C(1855982592), // UQADDv4i32 |
| 5400 | UINT64_C(1851788288), // UQADDv8i16 |
| 5401 | UINT64_C(773852160), // UQADDv8i8 |
| 5402 | UINT64_C(69270528), // UQDECB_WPiI |
| 5403 | UINT64_C(70319104), // UQDECB_XPiI |
| 5404 | UINT64_C(81853440), // UQDECD_WPiI |
| 5405 | UINT64_C(82902016), // UQDECD_XPiI |
| 5406 | UINT64_C(81841152), // UQDECD_ZPiI |
| 5407 | UINT64_C(73464832), // UQDECH_WPiI |
| 5408 | UINT64_C(74513408), // UQDECH_XPiI |
| 5409 | UINT64_C(73452544), // UQDECH_ZPiI |
| 5410 | UINT64_C(623609856), // UQDECP_WP_B |
| 5411 | UINT64_C(636192768), // UQDECP_WP_D |
| 5412 | UINT64_C(627804160), // UQDECP_WP_H |
| 5413 | UINT64_C(631998464), // UQDECP_WP_S |
| 5414 | UINT64_C(623610880), // UQDECP_XP_B |
| 5415 | UINT64_C(636193792), // UQDECP_XP_D |
| 5416 | UINT64_C(627805184), // UQDECP_XP_H |
| 5417 | UINT64_C(631999488), // UQDECP_XP_S |
| 5418 | UINT64_C(636190720), // UQDECP_ZP_D |
| 5419 | UINT64_C(627802112), // UQDECP_ZP_H |
| 5420 | UINT64_C(631996416), // UQDECP_ZP_S |
| 5421 | UINT64_C(77659136), // UQDECW_WPiI |
| 5422 | UINT64_C(78707712), // UQDECW_XPiI |
| 5423 | UINT64_C(77646848), // UQDECW_ZPiI |
| 5424 | UINT64_C(69268480), // UQINCB_WPiI |
| 5425 | UINT64_C(70317056), // UQINCB_XPiI |
| 5426 | UINT64_C(81851392), // UQINCD_WPiI |
| 5427 | UINT64_C(82899968), // UQINCD_XPiI |
| 5428 | UINT64_C(81839104), // UQINCD_ZPiI |
| 5429 | UINT64_C(73462784), // UQINCH_WPiI |
| 5430 | UINT64_C(74511360), // UQINCH_XPiI |
| 5431 | UINT64_C(73450496), // UQINCH_ZPiI |
| 5432 | UINT64_C(623478784), // UQINCP_WP_B |
| 5433 | UINT64_C(636061696), // UQINCP_WP_D |
| 5434 | UINT64_C(627673088), // UQINCP_WP_H |
| 5435 | UINT64_C(631867392), // UQINCP_WP_S |
| 5436 | UINT64_C(623479808), // UQINCP_XP_B |
| 5437 | UINT64_C(636062720), // UQINCP_XP_D |
| 5438 | UINT64_C(627674112), // UQINCP_XP_H |
| 5439 | UINT64_C(631868416), // UQINCP_XP_S |
| 5440 | UINT64_C(636059648), // UQINCP_ZP_D |
| 5441 | UINT64_C(627671040), // UQINCP_ZP_H |
| 5442 | UINT64_C(631865344), // UQINCP_ZP_S |
| 5443 | UINT64_C(77657088), // UQINCW_WPiI |
| 5444 | UINT64_C(78705664), // UQINCW_XPiI |
| 5445 | UINT64_C(77644800), // UQINCW_ZPiI |
| 5446 | UINT64_C(1141866496), // UQRSHLR_ZPmZ_B |
| 5447 | UINT64_C(1154449408), // UQRSHLR_ZPmZ_D |
| 5448 | UINT64_C(1146060800), // UQRSHLR_ZPmZ_H |
| 5449 | UINT64_C(1150255104), // UQRSHLR_ZPmZ_S |
| 5450 | UINT64_C(1141604352), // UQRSHL_ZPmZ_B |
| 5451 | UINT64_C(1154187264), // UQRSHL_ZPmZ_D |
| 5452 | UINT64_C(1145798656), // UQRSHL_ZPmZ_H |
| 5453 | UINT64_C(1149992960), // UQRSHL_ZPmZ_S |
| 5454 | UINT64_C(1847614464), // UQRSHLv16i8 |
| 5455 | UINT64_C(2120244224), // UQRSHLv1i16 |
| 5456 | UINT64_C(2124438528), // UQRSHLv1i32 |
| 5457 | UINT64_C(2128632832), // UQRSHLv1i64 |
| 5458 | UINT64_C(2116049920), // UQRSHLv1i8 |
| 5459 | UINT64_C(782261248), // UQRSHLv2i32 |
| 5460 | UINT64_C(1860197376), // UQRSHLv2i64 |
| 5461 | UINT64_C(778066944), // UQRSHLv4i16 |
| 5462 | UINT64_C(1856003072), // UQRSHLv4i32 |
| 5463 | UINT64_C(1851808768), // UQRSHLv8i16 |
| 5464 | UINT64_C(773872640), // UQRSHLv8i8 |
| 5465 | UINT64_C(1160263680), // UQRSHRNB_ZZI_B |
| 5466 | UINT64_C(1160787968), // UQRSHRNB_ZZI_H |
| 5467 | UINT64_C(1163933696), // UQRSHRNB_ZZI_S |
| 5468 | UINT64_C(1160264704), // UQRSHRNT_ZZI_B |
| 5469 | UINT64_C(1160788992), // UQRSHRNT_ZZI_H |
| 5470 | UINT64_C(1163934720), // UQRSHRNT_ZZI_S |
| 5471 | UINT64_C(2131270656), // UQRSHRNb |
| 5472 | UINT64_C(2131794944), // UQRSHRNh |
| 5473 | UINT64_C(2132843520), // UQRSHRNs |
| 5474 | UINT64_C(1862835200), // UQRSHRNv16i8_shift |
| 5475 | UINT64_C(790666240), // UQRSHRNv2i32_shift |
| 5476 | UINT64_C(789617664), // UQRSHRNv4i16_shift |
| 5477 | UINT64_C(1864408064), // UQRSHRNv4i32_shift |
| 5478 | UINT64_C(1863359488), // UQRSHRNv8i16_shift |
| 5479 | UINT64_C(789093376), // UQRSHRNv8i8_shift |
| 5480 | UINT64_C(1141735424), // UQSHLR_ZPmZ_B |
| 5481 | UINT64_C(1154318336), // UQSHLR_ZPmZ_D |
| 5482 | UINT64_C(1145929728), // UQSHLR_ZPmZ_H |
| 5483 | UINT64_C(1150124032), // UQSHLR_ZPmZ_S |
| 5484 | UINT64_C(67600640), // UQSHL_ZPmI_B |
| 5485 | UINT64_C(75988992), // UQSHL_ZPmI_D |
| 5486 | UINT64_C(67600896), // UQSHL_ZPmI_H |
| 5487 | UINT64_C(71794688), // UQSHL_ZPmI_S |
| 5488 | UINT64_C(1141473280), // UQSHL_ZPmZ_B |
| 5489 | UINT64_C(1154056192), // UQSHL_ZPmZ_D |
| 5490 | UINT64_C(1145667584), // UQSHL_ZPmZ_H |
| 5491 | UINT64_C(1149861888), // UQSHL_ZPmZ_S |
| 5492 | UINT64_C(2131260416), // UQSHLb |
| 5493 | UINT64_C(2134930432), // UQSHLd |
| 5494 | UINT64_C(2131784704), // UQSHLh |
| 5495 | UINT64_C(2132833280), // UQSHLs |
| 5496 | UINT64_C(1847610368), // UQSHLv16i8 |
| 5497 | UINT64_C(1862824960), // UQSHLv16i8_shift |
| 5498 | UINT64_C(2120240128), // UQSHLv1i16 |
| 5499 | UINT64_C(2124434432), // UQSHLv1i32 |
| 5500 | UINT64_C(2128628736), // UQSHLv1i64 |
| 5501 | UINT64_C(2116045824), // UQSHLv1i8 |
| 5502 | UINT64_C(782257152), // UQSHLv2i32 |
| 5503 | UINT64_C(790656000), // UQSHLv2i32_shift |
| 5504 | UINT64_C(1860193280), // UQSHLv2i64 |
| 5505 | UINT64_C(1866494976), // UQSHLv2i64_shift |
| 5506 | UINT64_C(778062848), // UQSHLv4i16 |
| 5507 | UINT64_C(789607424), // UQSHLv4i16_shift |
| 5508 | UINT64_C(1855998976), // UQSHLv4i32 |
| 5509 | UINT64_C(1864397824), // UQSHLv4i32_shift |
| 5510 | UINT64_C(1851804672), // UQSHLv8i16 |
| 5511 | UINT64_C(1863349248), // UQSHLv8i16_shift |
| 5512 | UINT64_C(773868544), // UQSHLv8i8 |
| 5513 | UINT64_C(789083136), // UQSHLv8i8_shift |
| 5514 | UINT64_C(1160261632), // UQSHRNB_ZZI_B |
| 5515 | UINT64_C(1160785920), // UQSHRNB_ZZI_H |
| 5516 | UINT64_C(1163931648), // UQSHRNB_ZZI_S |
| 5517 | UINT64_C(1160262656), // UQSHRNT_ZZI_B |
| 5518 | UINT64_C(1160786944), // UQSHRNT_ZZI_H |
| 5519 | UINT64_C(1163932672), // UQSHRNT_ZZI_S |
| 5520 | UINT64_C(2131268608), // UQSHRNb |
| 5521 | UINT64_C(2131792896), // UQSHRNh |
| 5522 | UINT64_C(2132841472), // UQSHRNs |
| 5523 | UINT64_C(1862833152), // UQSHRNv16i8_shift |
| 5524 | UINT64_C(790664192), // UQSHRNv2i32_shift |
| 5525 | UINT64_C(789615616), // UQSHRNv4i16_shift |
| 5526 | UINT64_C(1864406016), // UQSHRNv4i32_shift |
| 5527 | UINT64_C(1863357440), // UQSHRNv8i16_shift |
| 5528 | UINT64_C(789091328), // UQSHRNv8i8_shift |
| 5529 | UINT64_C(1142915072), // UQSUBR_ZPmZ_B |
| 5530 | UINT64_C(1155497984), // UQSUBR_ZPmZ_D |
| 5531 | UINT64_C(1147109376), // UQSUBR_ZPmZ_H |
| 5532 | UINT64_C(1151303680), // UQSUBR_ZPmZ_S |
| 5533 | UINT64_C(623362048), // UQSUB_ZI_B |
| 5534 | UINT64_C(635944960), // UQSUB_ZI_D |
| 5535 | UINT64_C(627556352), // UQSUB_ZI_H |
| 5536 | UINT64_C(631750656), // UQSUB_ZI_S |
| 5537 | UINT64_C(1142652928), // UQSUB_ZPmZ_B |
| 5538 | UINT64_C(1155235840), // UQSUB_ZPmZ_D |
| 5539 | UINT64_C(1146847232), // UQSUB_ZPmZ_H |
| 5540 | UINT64_C(1151041536), // UQSUB_ZPmZ_S |
| 5541 | UINT64_C(69213184), // UQSUB_ZZZ_B |
| 5542 | UINT64_C(81796096), // UQSUB_ZZZ_D |
| 5543 | UINT64_C(73407488), // UQSUB_ZZZ_H |
| 5544 | UINT64_C(77601792), // UQSUB_ZZZ_S |
| 5545 | UINT64_C(1847602176), // UQSUBv16i8 |
| 5546 | UINT64_C(2120231936), // UQSUBv1i16 |
| 5547 | UINT64_C(2124426240), // UQSUBv1i32 |
| 5548 | UINT64_C(2128620544), // UQSUBv1i64 |
| 5549 | UINT64_C(2116037632), // UQSUBv1i8 |
| 5550 | UINT64_C(782248960), // UQSUBv2i32 |
| 5551 | UINT64_C(1860185088), // UQSUBv2i64 |
| 5552 | UINT64_C(778054656), // UQSUBv4i16 |
| 5553 | UINT64_C(1855990784), // UQSUBv4i32 |
| 5554 | UINT64_C(1851796480), // UQSUBv8i16 |
| 5555 | UINT64_C(773860352), // UQSUBv8i8 |
| 5556 | UINT64_C(1160267776), // UQXTNB_ZZ_B |
| 5557 | UINT64_C(1160792064), // UQXTNB_ZZ_H |
| 5558 | UINT64_C(1163937792), // UQXTNB_ZZ_S |
| 5559 | UINT64_C(1160268800), // UQXTNT_ZZ_B |
| 5560 | UINT64_C(1160793088), // UQXTNT_ZZ_H |
| 5561 | UINT64_C(1163938816), // UQXTNT_ZZ_S |
| 5562 | UINT64_C(1847674880), // UQXTNv16i8 |
| 5563 | UINT64_C(2120304640), // UQXTNv1i16 |
| 5564 | UINT64_C(2124498944), // UQXTNv1i32 |
| 5565 | UINT64_C(2116110336), // UQXTNv1i8 |
| 5566 | UINT64_C(782321664), // UQXTNv2i32 |
| 5567 | UINT64_C(778127360), // UQXTNv4i16 |
| 5568 | UINT64_C(1856063488), // UQXTNv4i32 |
| 5569 | UINT64_C(1851869184), // UQXTNv8i16 |
| 5570 | UINT64_C(773933056), // UQXTNv8i8 |
| 5571 | UINT64_C(1149280256), // URECPE_ZPmZ_S |
| 5572 | UINT64_C(245483520), // URECPEv2i32 |
| 5573 | UINT64_C(1319225344), // URECPEv4i32 |
| 5574 | UINT64_C(1142259712), // URHADD_ZPmZ_B |
| 5575 | UINT64_C(1154842624), // URHADD_ZPmZ_D |
| 5576 | UINT64_C(1146454016), // URHADD_ZPmZ_H |
| 5577 | UINT64_C(1150648320), // URHADD_ZPmZ_S |
| 5578 | UINT64_C(1847596032), // URHADDv16i8 |
| 5579 | UINT64_C(782242816), // URHADDv2i32 |
| 5580 | UINT64_C(778048512), // URHADDv4i16 |
| 5581 | UINT64_C(1855984640), // URHADDv4i32 |
| 5582 | UINT64_C(1851790336), // URHADDv8i16 |
| 5583 | UINT64_C(773854208), // URHADDv8i8 |
| 5584 | UINT64_C(1141342208), // URSHLR_ZPmZ_B |
| 5585 | UINT64_C(1153925120), // URSHLR_ZPmZ_D |
| 5586 | UINT64_C(1145536512), // URSHLR_ZPmZ_H |
| 5587 | UINT64_C(1149730816), // URSHLR_ZPmZ_S |
| 5588 | UINT64_C(1141080064), // URSHL_ZPmZ_B |
| 5589 | UINT64_C(1153662976), // URSHL_ZPmZ_D |
| 5590 | UINT64_C(1145274368), // URSHL_ZPmZ_H |
| 5591 | UINT64_C(1149468672), // URSHL_ZPmZ_S |
| 5592 | UINT64_C(1847612416), // URSHLv16i8 |
| 5593 | UINT64_C(2128630784), // URSHLv1i64 |
| 5594 | UINT64_C(782259200), // URSHLv2i32 |
| 5595 | UINT64_C(1860195328), // URSHLv2i64 |
| 5596 | UINT64_C(778064896), // URSHLv4i16 |
| 5597 | UINT64_C(1856001024), // URSHLv4i32 |
| 5598 | UINT64_C(1851806720), // URSHLv8i16 |
| 5599 | UINT64_C(773870592), // URSHLv8i8 |
| 5600 | UINT64_C(67993856), // URSHR_ZPmI_B |
| 5601 | UINT64_C(76382208), // URSHR_ZPmI_D |
| 5602 | UINT64_C(67994112), // URSHR_ZPmI_H |
| 5603 | UINT64_C(72187904), // URSHR_ZPmI_S |
| 5604 | UINT64_C(2134909952), // URSHRd |
| 5605 | UINT64_C(1862804480), // URSHRv16i8_shift |
| 5606 | UINT64_C(790635520), // URSHRv2i32_shift |
| 5607 | UINT64_C(1866474496), // URSHRv2i64_shift |
| 5608 | UINT64_C(789586944), // URSHRv4i16_shift |
| 5609 | UINT64_C(1864377344), // URSHRv4i32_shift |
| 5610 | UINT64_C(1863328768), // URSHRv8i16_shift |
| 5611 | UINT64_C(789062656), // URSHRv8i8_shift |
| 5612 | UINT64_C(1149345792), // URSQRTE_ZPmZ_S |
| 5613 | UINT64_C(782354432), // URSQRTEv2i32 |
| 5614 | UINT64_C(1856096256), // URSQRTEv4i32 |
| 5615 | UINT64_C(1158212608), // URSRA_ZZI_B |
| 5616 | UINT64_C(1166076928), // URSRA_ZZI_D |
| 5617 | UINT64_C(1158736896), // URSRA_ZZI_H |
| 5618 | UINT64_C(1161882624), // URSRA_ZZI_S |
| 5619 | UINT64_C(2134914048), // URSRAd |
| 5620 | UINT64_C(1862808576), // URSRAv16i8_shift |
| 5621 | UINT64_C(790639616), // URSRAv2i32_shift |
| 5622 | UINT64_C(1866478592), // URSRAv2i64_shift |
| 5623 | UINT64_C(789591040), // URSRAv4i16_shift |
| 5624 | UINT64_C(1864381440), // URSRAv4i32_shift |
| 5625 | UINT64_C(1863332864), // URSRAv8i16_shift |
| 5626 | UINT64_C(789066752), // URSRAv8i8_shift |
| 5627 | UINT64_C(1149270016), // USDOT_ZZZ |
| 5628 | UINT64_C(1151342592), // USDOT_ZZZI |
| 5629 | UINT64_C(1333850112), // USDOTlanev16i8 |
| 5630 | UINT64_C(260108288), // USDOTlanev8i8 |
| 5631 | UINT64_C(1317051392), // USDOTv16i8 |
| 5632 | UINT64_C(243309568), // USDOTv8i8 |
| 5633 | UINT64_C(1161865216), // USHLLB_ZZI_D |
| 5634 | UINT64_C(1158195200), // USHLLB_ZZI_H |
| 5635 | UINT64_C(1158719488), // USHLLB_ZZI_S |
| 5636 | UINT64_C(1161866240), // USHLLT_ZZI_D |
| 5637 | UINT64_C(1158196224), // USHLLT_ZZI_H |
| 5638 | UINT64_C(1158720512), // USHLLT_ZZI_S |
| 5639 | UINT64_C(1862837248), // USHLLv16i8_shift |
| 5640 | UINT64_C(790668288), // USHLLv2i32_shift |
| 5641 | UINT64_C(789619712), // USHLLv4i16_shift |
| 5642 | UINT64_C(1864410112), // USHLLv4i32_shift |
| 5643 | UINT64_C(1863361536), // USHLLv8i16_shift |
| 5644 | UINT64_C(789095424), // USHLLv8i8_shift |
| 5645 | UINT64_C(1847608320), // USHLv16i8 |
| 5646 | UINT64_C(2128626688), // USHLv1i64 |
| 5647 | UINT64_C(782255104), // USHLv2i32 |
| 5648 | UINT64_C(1860191232), // USHLv2i64 |
| 5649 | UINT64_C(778060800), // USHLv4i16 |
| 5650 | UINT64_C(1855996928), // USHLv4i32 |
| 5651 | UINT64_C(1851802624), // USHLv8i16 |
| 5652 | UINT64_C(773866496), // USHLv8i8 |
| 5653 | UINT64_C(2134901760), // USHRd |
| 5654 | UINT64_C(1862796288), // USHRv16i8_shift |
| 5655 | UINT64_C(790627328), // USHRv2i32_shift |
| 5656 | UINT64_C(1866466304), // USHRv2i64_shift |
| 5657 | UINT64_C(789578752), // USHRv4i16_shift |
| 5658 | UINT64_C(1864369152), // USHRv4i32_shift |
| 5659 | UINT64_C(1863320576), // USHRv8i16_shift |
| 5660 | UINT64_C(789054464), // USHRv8i8_shift |
| 5661 | UINT64_C(1317055488), // USMMLA |
| 5662 | UINT64_C(1166055424), // USMMLA_ZZZ |
| 5663 | UINT64_C(1142784000), // USQADD_ZPmZ_B |
| 5664 | UINT64_C(1155366912), // USQADD_ZPmZ_D |
| 5665 | UINT64_C(1146978304), // USQADD_ZPmZ_H |
| 5666 | UINT64_C(1151172608), // USQADD_ZPmZ_S |
| 5667 | UINT64_C(1847605248), // USQADDv16i8 |
| 5668 | UINT64_C(2120235008), // USQADDv1i16 |
| 5669 | UINT64_C(2124429312), // USQADDv1i32 |
| 5670 | UINT64_C(2128623616), // USQADDv1i64 |
| 5671 | UINT64_C(2116040704), // USQADDv1i8 |
| 5672 | UINT64_C(782252032), // USQADDv2i32 |
| 5673 | UINT64_C(1860188160), // USQADDv2i64 |
| 5674 | UINT64_C(778057728), // USQADDv4i16 |
| 5675 | UINT64_C(1855993856), // USQADDv4i32 |
| 5676 | UINT64_C(1851799552), // USQADDv8i16 |
| 5677 | UINT64_C(773863424), // USQADDv8i8 |
| 5678 | UINT64_C(1158210560), // USRA_ZZI_B |
| 5679 | UINT64_C(1166074880), // USRA_ZZI_D |
| 5680 | UINT64_C(1158734848), // USRA_ZZI_H |
| 5681 | UINT64_C(1161880576), // USRA_ZZI_S |
| 5682 | UINT64_C(2134905856), // USRAd |
| 5683 | UINT64_C(1862800384), // USRAv16i8_shift |
| 5684 | UINT64_C(790631424), // USRAv2i32_shift |
| 5685 | UINT64_C(1866470400), // USRAv2i64_shift |
| 5686 | UINT64_C(789582848), // USRAv4i16_shift |
| 5687 | UINT64_C(1864373248), // USRAv4i32_shift |
| 5688 | UINT64_C(1863324672), // USRAv8i16_shift |
| 5689 | UINT64_C(789058560), // USRAv8i8_shift |
| 5690 | UINT64_C(1170216960), // USUBLB_ZZZ_D |
| 5691 | UINT64_C(1161828352), // USUBLB_ZZZ_H |
| 5692 | UINT64_C(1166022656), // USUBLB_ZZZ_S |
| 5693 | UINT64_C(1170217984), // USUBLT_ZZZ_D |
| 5694 | UINT64_C(1161829376), // USUBLT_ZZZ_H |
| 5695 | UINT64_C(1166023680), // USUBLT_ZZZ_S |
| 5696 | UINT64_C(1847599104), // USUBLv16i8_v8i16 |
| 5697 | UINT64_C(782245888), // USUBLv2i32_v2i64 |
| 5698 | UINT64_C(778051584), // USUBLv4i16_v4i32 |
| 5699 | UINT64_C(1855987712), // USUBLv4i32_v2i64 |
| 5700 | UINT64_C(1851793408), // USUBLv8i16_v4i32 |
| 5701 | UINT64_C(773857280), // USUBLv8i8_v8i16 |
| 5702 | UINT64_C(1170233344), // USUBWB_ZZZ_D |
| 5703 | UINT64_C(1161844736), // USUBWB_ZZZ_H |
| 5704 | UINT64_C(1166039040), // USUBWB_ZZZ_S |
| 5705 | UINT64_C(1170234368), // USUBWT_ZZZ_D |
| 5706 | UINT64_C(1161845760), // USUBWT_ZZZ_H |
| 5707 | UINT64_C(1166040064), // USUBWT_ZZZ_S |
| 5708 | UINT64_C(1847603200), // USUBWv16i8_v8i16 |
| 5709 | UINT64_C(782249984), // USUBWv2i32_v2i64 |
| 5710 | UINT64_C(778055680), // USUBWv4i16_v4i32 |
| 5711 | UINT64_C(1855991808), // USUBWv4i32_v2i64 |
| 5712 | UINT64_C(1851797504), // USUBWv8i16_v4i32 |
| 5713 | UINT64_C(773861376), // USUBWv8i8_v8i16 |
| 5714 | UINT64_C(99825664), // UUNPKHI_ZZ_D |
| 5715 | UINT64_C(91437056), // UUNPKHI_ZZ_H |
| 5716 | UINT64_C(95631360), // UUNPKHI_ZZ_S |
| 5717 | UINT64_C(99760128), // UUNPKLO_ZZ_D |
| 5718 | UINT64_C(91371520), // UUNPKLO_ZZ_H |
| 5719 | UINT64_C(95565824), // UUNPKLO_ZZ_S |
| 5720 | UINT64_C(80846848), // UXTB_ZPmZ_D |
| 5721 | UINT64_C(72458240), // UXTB_ZPmZ_H |
| 5722 | UINT64_C(76652544), // UXTB_ZPmZ_S |
| 5723 | UINT64_C(80977920), // UXTH_ZPmZ_D |
| 5724 | UINT64_C(76783616), // UXTH_ZPmZ_S |
| 5725 | UINT64_C(81108992), // UXTW_ZPmZ_D |
| 5726 | UINT64_C(86001664), // UZP1_PPP_B |
| 5727 | UINT64_C(98584576), // UZP1_PPP_D |
| 5728 | UINT64_C(90195968), // UZP1_PPP_H |
| 5729 | UINT64_C(94390272), // UZP1_PPP_S |
| 5730 | UINT64_C(86009856), // UZP1_ZZZ_B |
| 5731 | UINT64_C(98592768), // UZP1_ZZZ_D |
| 5732 | UINT64_C(90204160), // UZP1_ZZZ_H |
| 5733 | UINT64_C(94373888), // UZP1_ZZZ_Q |
| 5734 | UINT64_C(94398464), // UZP1_ZZZ_S |
| 5735 | UINT64_C(1308628992), // UZP1v16i8 |
| 5736 | UINT64_C(243275776), // UZP1v2i32 |
| 5737 | UINT64_C(1321211904), // UZP1v2i64 |
| 5738 | UINT64_C(239081472), // UZP1v4i16 |
| 5739 | UINT64_C(1317017600), // UZP1v4i32 |
| 5740 | UINT64_C(1312823296), // UZP1v8i16 |
| 5741 | UINT64_C(234887168), // UZP1v8i8 |
| 5742 | UINT64_C(86002688), // UZP2_PPP_B |
| 5743 | UINT64_C(98585600), // UZP2_PPP_D |
| 5744 | UINT64_C(90196992), // UZP2_PPP_H |
| 5745 | UINT64_C(94391296), // UZP2_PPP_S |
| 5746 | UINT64_C(86010880), // UZP2_ZZZ_B |
| 5747 | UINT64_C(98593792), // UZP2_ZZZ_D |
| 5748 | UINT64_C(90205184), // UZP2_ZZZ_H |
| 5749 | UINT64_C(94374912), // UZP2_ZZZ_Q |
| 5750 | UINT64_C(94399488), // UZP2_ZZZ_S |
| 5751 | UINT64_C(1308645376), // UZP2v16i8 |
| 5752 | UINT64_C(243292160), // UZP2v2i32 |
| 5753 | UINT64_C(1321228288), // UZP2v2i64 |
| 5754 | UINT64_C(239097856), // UZP2v4i16 |
| 5755 | UINT64_C(1317033984), // UZP2v4i32 |
| 5756 | UINT64_C(1312839680), // UZP2v8i16 |
| 5757 | UINT64_C(234903552), // UZP2v8i8 |
| 5758 | UINT64_C(3573747712), // WFET |
| 5759 | UINT64_C(3573747744), // WFIT |
| 5760 | UINT64_C(622854144), // WHILEGE_PWW_B |
| 5761 | UINT64_C(635437056), // WHILEGE_PWW_D |
| 5762 | UINT64_C(627048448), // WHILEGE_PWW_H |
| 5763 | UINT64_C(631242752), // WHILEGE_PWW_S |
| 5764 | UINT64_C(622858240), // WHILEGE_PXX_B |
| 5765 | UINT64_C(635441152), // WHILEGE_PXX_D |
| 5766 | UINT64_C(627052544), // WHILEGE_PXX_H |
| 5767 | UINT64_C(631246848), // WHILEGE_PXX_S |
| 5768 | UINT64_C(622854160), // WHILEGT_PWW_B |
| 5769 | UINT64_C(635437072), // WHILEGT_PWW_D |
| 5770 | UINT64_C(627048464), // WHILEGT_PWW_H |
| 5771 | UINT64_C(631242768), // WHILEGT_PWW_S |
| 5772 | UINT64_C(622858256), // WHILEGT_PXX_B |
| 5773 | UINT64_C(635441168), // WHILEGT_PXX_D |
| 5774 | UINT64_C(627052560), // WHILEGT_PXX_H |
| 5775 | UINT64_C(631246864), // WHILEGT_PXX_S |
| 5776 | UINT64_C(622856208), // WHILEHI_PWW_B |
| 5777 | UINT64_C(635439120), // WHILEHI_PWW_D |
| 5778 | UINT64_C(627050512), // WHILEHI_PWW_H |
| 5779 | UINT64_C(631244816), // WHILEHI_PWW_S |
| 5780 | UINT64_C(622860304), // WHILEHI_PXX_B |
| 5781 | UINT64_C(635443216), // WHILEHI_PXX_D |
| 5782 | UINT64_C(627054608), // WHILEHI_PXX_H |
| 5783 | UINT64_C(631248912), // WHILEHI_PXX_S |
| 5784 | UINT64_C(622856192), // WHILEHS_PWW_B |
| 5785 | UINT64_C(635439104), // WHILEHS_PWW_D |
| 5786 | UINT64_C(627050496), // WHILEHS_PWW_H |
| 5787 | UINT64_C(631244800), // WHILEHS_PWW_S |
| 5788 | UINT64_C(622860288), // WHILEHS_PXX_B |
| 5789 | UINT64_C(635443200), // WHILEHS_PXX_D |
| 5790 | UINT64_C(627054592), // WHILEHS_PXX_H |
| 5791 | UINT64_C(631248896), // WHILEHS_PXX_S |
| 5792 | UINT64_C(622855184), // WHILELE_PWW_B |
| 5793 | UINT64_C(635438096), // WHILELE_PWW_D |
| 5794 | UINT64_C(627049488), // WHILELE_PWW_H |
| 5795 | UINT64_C(631243792), // WHILELE_PWW_S |
| 5796 | UINT64_C(622859280), // WHILELE_PXX_B |
| 5797 | UINT64_C(635442192), // WHILELE_PXX_D |
| 5798 | UINT64_C(627053584), // WHILELE_PXX_H |
| 5799 | UINT64_C(631247888), // WHILELE_PXX_S |
| 5800 | UINT64_C(622857216), // WHILELO_PWW_B |
| 5801 | UINT64_C(635440128), // WHILELO_PWW_D |
| 5802 | UINT64_C(627051520), // WHILELO_PWW_H |
| 5803 | UINT64_C(631245824), // WHILELO_PWW_S |
| 5804 | UINT64_C(622861312), // WHILELO_PXX_B |
| 5805 | UINT64_C(635444224), // WHILELO_PXX_D |
| 5806 | UINT64_C(627055616), // WHILELO_PXX_H |
| 5807 | UINT64_C(631249920), // WHILELO_PXX_S |
| 5808 | UINT64_C(622857232), // WHILELS_PWW_B |
| 5809 | UINT64_C(635440144), // WHILELS_PWW_D |
| 5810 | UINT64_C(627051536), // WHILELS_PWW_H |
| 5811 | UINT64_C(631245840), // WHILELS_PWW_S |
| 5812 | UINT64_C(622861328), // WHILELS_PXX_B |
| 5813 | UINT64_C(635444240), // WHILELS_PXX_D |
| 5814 | UINT64_C(627055632), // WHILELS_PXX_H |
| 5815 | UINT64_C(631249936), // WHILELS_PXX_S |
| 5816 | UINT64_C(622855168), // WHILELT_PWW_B |
| 5817 | UINT64_C(635438080), // WHILELT_PWW_D |
| 5818 | UINT64_C(627049472), // WHILELT_PWW_H |
| 5819 | UINT64_C(631243776), // WHILELT_PWW_S |
| 5820 | UINT64_C(622859264), // WHILELT_PXX_B |
| 5821 | UINT64_C(635442176), // WHILELT_PXX_D |
| 5822 | UINT64_C(627053568), // WHILELT_PXX_H |
| 5823 | UINT64_C(631247872), // WHILELT_PXX_S |
| 5824 | UINT64_C(622866448), // WHILERW_PXX_B |
| 5825 | UINT64_C(635449360), // WHILERW_PXX_D |
| 5826 | UINT64_C(627060752), // WHILERW_PXX_H |
| 5827 | UINT64_C(631255056), // WHILERW_PXX_S |
| 5828 | UINT64_C(622866432), // WHILEWR_PXX_B |
| 5829 | UINT64_C(635449344), // WHILEWR_PXX_D |
| 5830 | UINT64_C(627060736), // WHILEWR_PXX_H |
| 5831 | UINT64_C(631255040), // WHILEWR_PXX_S |
| 5832 | UINT64_C(623415296), // WRFFR |
| 5833 | UINT64_C(3573563455), // XAFLAG |
| 5834 | UINT64_C(3464495104), // XAR |
| 5835 | UINT64_C(69743616), // XAR_ZZZI_B |
| 5836 | UINT64_C(77607936), // XAR_ZZZI_D |
| 5837 | UINT64_C(70267904), // XAR_ZZZI_H |
| 5838 | UINT64_C(73413632), // XAR_ZZZI_S |
| 5839 | UINT64_C(3670099936), // XPACD |
| 5840 | UINT64_C(3670098912), // XPACI |
| 5841 | UINT64_C(3573752063), // XPACLRI |
| 5842 | UINT64_C(1310795776), // XTNv16i8 |
| 5843 | UINT64_C(245442560), // XTNv2i32 |
| 5844 | UINT64_C(241248256), // XTNv4i16 |
| 5845 | UINT64_C(1319184384), // XTNv4i32 |
| 5846 | UINT64_C(1314990080), // XTNv8i16 |
| 5847 | UINT64_C(237053952), // XTNv8i8 |
| 5848 | UINT64_C(85999616), // ZIP1_PPP_B |
| 5849 | UINT64_C(98582528), // ZIP1_PPP_D |
| 5850 | UINT64_C(90193920), // ZIP1_PPP_H |
| 5851 | UINT64_C(94388224), // ZIP1_PPP_S |
| 5852 | UINT64_C(86007808), // ZIP1_ZZZ_B |
| 5853 | UINT64_C(98590720), // ZIP1_ZZZ_D |
| 5854 | UINT64_C(90202112), // ZIP1_ZZZ_H |
| 5855 | UINT64_C(94371840), // ZIP1_ZZZ_Q |
| 5856 | UINT64_C(94396416), // ZIP1_ZZZ_S |
| 5857 | UINT64_C(1308637184), // ZIP1v16i8 |
| 5858 | UINT64_C(243283968), // ZIP1v2i32 |
| 5859 | UINT64_C(1321220096), // ZIP1v2i64 |
| 5860 | UINT64_C(239089664), // ZIP1v4i16 |
| 5861 | UINT64_C(1317025792), // ZIP1v4i32 |
| 5862 | UINT64_C(1312831488), // ZIP1v8i16 |
| 5863 | UINT64_C(234895360), // ZIP1v8i8 |
| 5864 | UINT64_C(86000640), // ZIP2_PPP_B |
| 5865 | UINT64_C(98583552), // ZIP2_PPP_D |
| 5866 | UINT64_C(90194944), // ZIP2_PPP_H |
| 5867 | UINT64_C(94389248), // ZIP2_PPP_S |
| 5868 | UINT64_C(86008832), // ZIP2_ZZZ_B |
| 5869 | UINT64_C(98591744), // ZIP2_ZZZ_D |
| 5870 | UINT64_C(90203136), // ZIP2_ZZZ_H |
| 5871 | UINT64_C(94372864), // ZIP2_ZZZ_Q |
| 5872 | UINT64_C(94397440), // ZIP2_ZZZ_S |
| 5873 | UINT64_C(1308653568), // ZIP2v16i8 |
| 5874 | UINT64_C(243300352), // ZIP2v2i32 |
| 5875 | UINT64_C(1321236480), // ZIP2v2i64 |
| 5876 | UINT64_C(239106048), // ZIP2v4i16 |
| 5877 | UINT64_C(1317042176), // ZIP2v4i32 |
| 5878 | UINT64_C(1312847872), // ZIP2v8i16 |
| 5879 | UINT64_C(234911744), // ZIP2v8i8 |
| 5880 | UINT64_C(0) |
| 5881 | }; |
| 5882 | const unsigned opcode = MI.getOpcode(); |
| 5883 | uint64_t Value = InstBits[opcode]; |
| 5884 | uint64_t op = 0; |
| 5885 | (void)op; // suppress warning |
| 5886 | switch (opcode) { |
| 5887 | case AArch64::AUTIA1716: |
| 5888 | case AArch64::AUTIASP: |
| 5889 | case AArch64::AUTIAZ: |
| 5890 | case AArch64::AUTIB1716: |
| 5891 | case AArch64::AUTIBSP: |
| 5892 | case AArch64::AUTIBZ: |
| 5893 | case AArch64::AXFLAG: |
| 5894 | case AArch64::BRB_IALL: |
| 5895 | case AArch64::BRB_INJ: |
| 5896 | case AArch64::CFINV: |
| 5897 | case AArch64::DRPS: |
| 5898 | case AArch64::ERET: |
| 5899 | case AArch64::ERETAA: |
| 5900 | case AArch64::ERETAB: |
| 5901 | case AArch64::PACIA1716: |
| 5902 | case AArch64::PACIASP: |
| 5903 | case AArch64::PACIAZ: |
| 5904 | case AArch64::PACIB1716: |
| 5905 | case AArch64::PACIBSP: |
| 5906 | case AArch64::PACIBZ: |
| 5907 | case AArch64::RETAA: |
| 5908 | case AArch64::RETAB: |
| 5909 | case AArch64::SB: |
| 5910 | case AArch64::SETFFR: |
| 5911 | case AArch64::TCOMMIT: |
| 5912 | case AArch64::TSB: |
| 5913 | case AArch64::XAFLAG: |
| 5914 | case AArch64::XPACLRI: { |
| 5915 | break; |
| 5916 | } |
| 5917 | case AArch64::DSBnXS: { |
| 5918 | // op: CRm |
| 5919 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 5920 | op &= UINT64_C(12); |
| 5921 | op <<= 8; |
| 5922 | Value |= op; |
| 5923 | break; |
| 5924 | } |
| 5925 | case AArch64::CLREX: |
| 5926 | case AArch64::DMB: |
| 5927 | case AArch64::DSB: |
| 5928 | case AArch64::ISB: { |
| 5929 | // op: CRm |
| 5930 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 5931 | op &= UINT64_C(15); |
| 5932 | op <<= 8; |
| 5933 | Value |= op; |
| 5934 | break; |
| 5935 | } |
| 5936 | case AArch64::PFALSE: |
| 5937 | case AArch64::RDFFR_P_REAL: { |
| 5938 | // op: Pd |
| 5939 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 5940 | op &= UINT64_C(15); |
| 5941 | Value |= op; |
| 5942 | break; |
| 5943 | } |
| 5944 | case AArch64::ANDS_PPzPP: |
| 5945 | case AArch64::AND_PPzPP: |
| 5946 | case AArch64::BICS_PPzPP: |
| 5947 | case AArch64::BIC_PPzPP: |
| 5948 | case AArch64::BRKPAS_PPzPP: |
| 5949 | case AArch64::BRKPA_PPzPP: |
| 5950 | case AArch64::BRKPBS_PPzPP: |
| 5951 | case AArch64::BRKPB_PPzPP: |
| 5952 | case AArch64::EORS_PPzPP: |
| 5953 | case AArch64::EOR_PPzPP: |
| 5954 | case AArch64::NANDS_PPzPP: |
| 5955 | case AArch64::NAND_PPzPP: |
| 5956 | case AArch64::NORS_PPzPP: |
| 5957 | case AArch64::NOR_PPzPP: |
| 5958 | case AArch64::ORNS_PPzPP: |
| 5959 | case AArch64::ORN_PPzPP: |
| 5960 | case AArch64::ORRS_PPzPP: |
| 5961 | case AArch64::ORR_PPzPP: |
| 5962 | case AArch64::SEL_PPPP: { |
| 5963 | // op: Pd |
| 5964 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 5965 | op &= UINT64_C(15); |
| 5966 | Value |= op; |
| 5967 | // op: Pg |
| 5968 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 5969 | op &= UINT64_C(15); |
| 5970 | op <<= 10; |
| 5971 | Value |= op; |
| 5972 | // op: Pm |
| 5973 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 5974 | op &= UINT64_C(15); |
| 5975 | op <<= 16; |
| 5976 | Value |= op; |
| 5977 | // op: Pn |
| 5978 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 5979 | op &= UINT64_C(15); |
| 5980 | op <<= 5; |
| 5981 | Value |= op; |
| 5982 | break; |
| 5983 | } |
| 5984 | case AArch64::BRKAS_PPzP: |
| 5985 | case AArch64::BRKA_PPzP: |
| 5986 | case AArch64::BRKBS_PPzP: |
| 5987 | case AArch64::BRKB_PPzP: { |
| 5988 | // op: Pd |
| 5989 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 5990 | op &= UINT64_C(15); |
| 5991 | Value |= op; |
| 5992 | // op: Pg |
| 5993 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 5994 | op &= UINT64_C(15); |
| 5995 | op <<= 10; |
| 5996 | Value |= op; |
| 5997 | // op: Pn |
| 5998 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 5999 | op &= UINT64_C(15); |
| 6000 | op <<= 5; |
| 6001 | Value |= op; |
| 6002 | break; |
| 6003 | } |
| 6004 | case AArch64::RDFFRS_PPz: |
| 6005 | case AArch64::RDFFR_PPz_REAL: { |
| 6006 | // op: Pd |
| 6007 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6008 | op &= UINT64_C(15); |
| 6009 | Value |= op; |
| 6010 | // op: Pg |
| 6011 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6012 | op &= UINT64_C(15); |
| 6013 | op <<= 5; |
| 6014 | Value |= op; |
| 6015 | break; |
| 6016 | } |
| 6017 | case AArch64::CMPEQ_PPzZZ_B: |
| 6018 | case AArch64::CMPEQ_PPzZZ_D: |
| 6019 | case AArch64::CMPEQ_PPzZZ_H: |
| 6020 | case AArch64::CMPEQ_PPzZZ_S: |
| 6021 | case AArch64::CMPEQ_WIDE_PPzZZ_B: |
| 6022 | case AArch64::CMPEQ_WIDE_PPzZZ_H: |
| 6023 | case AArch64::CMPEQ_WIDE_PPzZZ_S: |
| 6024 | case AArch64::CMPGE_PPzZZ_B: |
| 6025 | case AArch64::CMPGE_PPzZZ_D: |
| 6026 | case AArch64::CMPGE_PPzZZ_H: |
| 6027 | case AArch64::CMPGE_PPzZZ_S: |
| 6028 | case AArch64::CMPGE_WIDE_PPzZZ_B: |
| 6029 | case AArch64::CMPGE_WIDE_PPzZZ_H: |
| 6030 | case AArch64::CMPGE_WIDE_PPzZZ_S: |
| 6031 | case AArch64::CMPGT_PPzZZ_B: |
| 6032 | case AArch64::CMPGT_PPzZZ_D: |
| 6033 | case AArch64::CMPGT_PPzZZ_H: |
| 6034 | case AArch64::CMPGT_PPzZZ_S: |
| 6035 | case AArch64::CMPGT_WIDE_PPzZZ_B: |
| 6036 | case AArch64::CMPGT_WIDE_PPzZZ_H: |
| 6037 | case AArch64::CMPGT_WIDE_PPzZZ_S: |
| 6038 | case AArch64::CMPHI_PPzZZ_B: |
| 6039 | case AArch64::CMPHI_PPzZZ_D: |
| 6040 | case AArch64::CMPHI_PPzZZ_H: |
| 6041 | case AArch64::CMPHI_PPzZZ_S: |
| 6042 | case AArch64::CMPHI_WIDE_PPzZZ_B: |
| 6043 | case AArch64::CMPHI_WIDE_PPzZZ_H: |
| 6044 | case AArch64::CMPHI_WIDE_PPzZZ_S: |
| 6045 | case AArch64::CMPHS_PPzZZ_B: |
| 6046 | case AArch64::CMPHS_PPzZZ_D: |
| 6047 | case AArch64::CMPHS_PPzZZ_H: |
| 6048 | case AArch64::CMPHS_PPzZZ_S: |
| 6049 | case AArch64::CMPHS_WIDE_PPzZZ_B: |
| 6050 | case AArch64::CMPHS_WIDE_PPzZZ_H: |
| 6051 | case AArch64::CMPHS_WIDE_PPzZZ_S: |
| 6052 | case AArch64::CMPLE_WIDE_PPzZZ_B: |
| 6053 | case AArch64::CMPLE_WIDE_PPzZZ_H: |
| 6054 | case AArch64::CMPLE_WIDE_PPzZZ_S: |
| 6055 | case AArch64::CMPLO_WIDE_PPzZZ_B: |
| 6056 | case AArch64::CMPLO_WIDE_PPzZZ_H: |
| 6057 | case AArch64::CMPLO_WIDE_PPzZZ_S: |
| 6058 | case AArch64::CMPLS_WIDE_PPzZZ_B: |
| 6059 | case AArch64::CMPLS_WIDE_PPzZZ_H: |
| 6060 | case AArch64::CMPLS_WIDE_PPzZZ_S: |
| 6061 | case AArch64::CMPLT_WIDE_PPzZZ_B: |
| 6062 | case AArch64::CMPLT_WIDE_PPzZZ_H: |
| 6063 | case AArch64::CMPLT_WIDE_PPzZZ_S: |
| 6064 | case AArch64::CMPNE_PPzZZ_B: |
| 6065 | case AArch64::CMPNE_PPzZZ_D: |
| 6066 | case AArch64::CMPNE_PPzZZ_H: |
| 6067 | case AArch64::CMPNE_PPzZZ_S: |
| 6068 | case AArch64::CMPNE_WIDE_PPzZZ_B: |
| 6069 | case AArch64::CMPNE_WIDE_PPzZZ_H: |
| 6070 | case AArch64::CMPNE_WIDE_PPzZZ_S: |
| 6071 | case AArch64::FACGE_PPzZZ_D: |
| 6072 | case AArch64::FACGE_PPzZZ_H: |
| 6073 | case AArch64::FACGE_PPzZZ_S: |
| 6074 | case AArch64::FACGT_PPzZZ_D: |
| 6075 | case AArch64::FACGT_PPzZZ_H: |
| 6076 | case AArch64::FACGT_PPzZZ_S: |
| 6077 | case AArch64::FCMEQ_PPzZZ_D: |
| 6078 | case AArch64::FCMEQ_PPzZZ_H: |
| 6079 | case AArch64::FCMEQ_PPzZZ_S: |
| 6080 | case AArch64::FCMGE_PPzZZ_D: |
| 6081 | case AArch64::FCMGE_PPzZZ_H: |
| 6082 | case AArch64::FCMGE_PPzZZ_S: |
| 6083 | case AArch64::FCMGT_PPzZZ_D: |
| 6084 | case AArch64::FCMGT_PPzZZ_H: |
| 6085 | case AArch64::FCMGT_PPzZZ_S: |
| 6086 | case AArch64::FCMNE_PPzZZ_D: |
| 6087 | case AArch64::FCMNE_PPzZZ_H: |
| 6088 | case AArch64::FCMNE_PPzZZ_S: |
| 6089 | case AArch64::FCMUO_PPzZZ_D: |
| 6090 | case AArch64::FCMUO_PPzZZ_H: |
| 6091 | case AArch64::FCMUO_PPzZZ_S: |
| 6092 | case AArch64::MATCH_PPzZZ_B: |
| 6093 | case AArch64::MATCH_PPzZZ_H: |
| 6094 | case AArch64::NMATCH_PPzZZ_B: |
| 6095 | case AArch64::NMATCH_PPzZZ_H: { |
| 6096 | // op: Pd |
| 6097 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6098 | op &= UINT64_C(15); |
| 6099 | Value |= op; |
| 6100 | // op: Pg |
| 6101 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6102 | op &= UINT64_C(7); |
| 6103 | op <<= 10; |
| 6104 | Value |= op; |
| 6105 | // op: Zm |
| 6106 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6107 | op &= UINT64_C(31); |
| 6108 | op <<= 16; |
| 6109 | Value |= op; |
| 6110 | // op: Zn |
| 6111 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6112 | op &= UINT64_C(31); |
| 6113 | op <<= 5; |
| 6114 | Value |= op; |
| 6115 | break; |
| 6116 | } |
| 6117 | case AArch64::FCMEQ_PPzZ0_D: |
| 6118 | case AArch64::FCMEQ_PPzZ0_H: |
| 6119 | case AArch64::FCMEQ_PPzZ0_S: |
| 6120 | case AArch64::FCMGE_PPzZ0_D: |
| 6121 | case AArch64::FCMGE_PPzZ0_H: |
| 6122 | case AArch64::FCMGE_PPzZ0_S: |
| 6123 | case AArch64::FCMGT_PPzZ0_D: |
| 6124 | case AArch64::FCMGT_PPzZ0_H: |
| 6125 | case AArch64::FCMGT_PPzZ0_S: |
| 6126 | case AArch64::FCMLE_PPzZ0_D: |
| 6127 | case AArch64::FCMLE_PPzZ0_H: |
| 6128 | case AArch64::FCMLE_PPzZ0_S: |
| 6129 | case AArch64::FCMLT_PPzZ0_D: |
| 6130 | case AArch64::FCMLT_PPzZ0_H: |
| 6131 | case AArch64::FCMLT_PPzZ0_S: |
| 6132 | case AArch64::FCMNE_PPzZ0_D: |
| 6133 | case AArch64::FCMNE_PPzZ0_H: |
| 6134 | case AArch64::FCMNE_PPzZ0_S: { |
| 6135 | // op: Pd |
| 6136 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6137 | op &= UINT64_C(15); |
| 6138 | Value |= op; |
| 6139 | // op: Pg |
| 6140 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6141 | op &= UINT64_C(7); |
| 6142 | op <<= 10; |
| 6143 | Value |= op; |
| 6144 | // op: Zn |
| 6145 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6146 | op &= UINT64_C(31); |
| 6147 | op <<= 5; |
| 6148 | Value |= op; |
| 6149 | break; |
| 6150 | } |
| 6151 | case AArch64::CMPEQ_PPzZI_B: |
| 6152 | case AArch64::CMPEQ_PPzZI_D: |
| 6153 | case AArch64::CMPEQ_PPzZI_H: |
| 6154 | case AArch64::CMPEQ_PPzZI_S: |
| 6155 | case AArch64::CMPGE_PPzZI_B: |
| 6156 | case AArch64::CMPGE_PPzZI_D: |
| 6157 | case AArch64::CMPGE_PPzZI_H: |
| 6158 | case AArch64::CMPGE_PPzZI_S: |
| 6159 | case AArch64::CMPGT_PPzZI_B: |
| 6160 | case AArch64::CMPGT_PPzZI_D: |
| 6161 | case AArch64::CMPGT_PPzZI_H: |
| 6162 | case AArch64::CMPGT_PPzZI_S: |
| 6163 | case AArch64::CMPLE_PPzZI_B: |
| 6164 | case AArch64::CMPLE_PPzZI_D: |
| 6165 | case AArch64::CMPLE_PPzZI_H: |
| 6166 | case AArch64::CMPLE_PPzZI_S: |
| 6167 | case AArch64::CMPLT_PPzZI_B: |
| 6168 | case AArch64::CMPLT_PPzZI_D: |
| 6169 | case AArch64::CMPLT_PPzZI_H: |
| 6170 | case AArch64::CMPLT_PPzZI_S: |
| 6171 | case AArch64::CMPNE_PPzZI_B: |
| 6172 | case AArch64::CMPNE_PPzZI_D: |
| 6173 | case AArch64::CMPNE_PPzZI_H: |
| 6174 | case AArch64::CMPNE_PPzZI_S: { |
| 6175 | // op: Pd |
| 6176 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6177 | op &= UINT64_C(15); |
| 6178 | Value |= op; |
| 6179 | // op: Pg |
| 6180 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6181 | op &= UINT64_C(7); |
| 6182 | op <<= 10; |
| 6183 | Value |= op; |
| 6184 | // op: Zn |
| 6185 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6186 | op &= UINT64_C(31); |
| 6187 | op <<= 5; |
| 6188 | Value |= op; |
| 6189 | // op: imm5 |
| 6190 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6191 | op &= UINT64_C(31); |
| 6192 | op <<= 16; |
| 6193 | Value |= op; |
| 6194 | break; |
| 6195 | } |
| 6196 | case AArch64::CMPHI_PPzZI_B: |
| 6197 | case AArch64::CMPHI_PPzZI_D: |
| 6198 | case AArch64::CMPHI_PPzZI_H: |
| 6199 | case AArch64::CMPHI_PPzZI_S: |
| 6200 | case AArch64::CMPHS_PPzZI_B: |
| 6201 | case AArch64::CMPHS_PPzZI_D: |
| 6202 | case AArch64::CMPHS_PPzZI_H: |
| 6203 | case AArch64::CMPHS_PPzZI_S: |
| 6204 | case AArch64::CMPLO_PPzZI_B: |
| 6205 | case AArch64::CMPLO_PPzZI_D: |
| 6206 | case AArch64::CMPLO_PPzZI_H: |
| 6207 | case AArch64::CMPLO_PPzZI_S: |
| 6208 | case AArch64::CMPLS_PPzZI_B: |
| 6209 | case AArch64::CMPLS_PPzZI_D: |
| 6210 | case AArch64::CMPLS_PPzZI_H: |
| 6211 | case AArch64::CMPLS_PPzZI_S: { |
| 6212 | // op: Pd |
| 6213 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6214 | op &= UINT64_C(15); |
| 6215 | Value |= op; |
| 6216 | // op: Pg |
| 6217 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6218 | op &= UINT64_C(7); |
| 6219 | op <<= 10; |
| 6220 | Value |= op; |
| 6221 | // op: Zn |
| 6222 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6223 | op &= UINT64_C(31); |
| 6224 | op <<= 5; |
| 6225 | Value |= op; |
| 6226 | // op: imm7 |
| 6227 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6228 | op &= UINT64_C(127); |
| 6229 | op <<= 14; |
| 6230 | Value |= op; |
| 6231 | break; |
| 6232 | } |
| 6233 | case AArch64::BRKA_PPmP: |
| 6234 | case AArch64::BRKB_PPmP: { |
| 6235 | // op: Pd |
| 6236 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6237 | op &= UINT64_C(15); |
| 6238 | Value |= op; |
| 6239 | // op: Pg |
| 6240 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6241 | op &= UINT64_C(15); |
| 6242 | op <<= 10; |
| 6243 | Value |= op; |
| 6244 | // op: Pn |
| 6245 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6246 | op &= UINT64_C(15); |
| 6247 | op <<= 5; |
| 6248 | Value |= op; |
| 6249 | break; |
| 6250 | } |
| 6251 | case AArch64::TRN1_PPP_B: |
| 6252 | case AArch64::TRN1_PPP_D: |
| 6253 | case AArch64::TRN1_PPP_H: |
| 6254 | case AArch64::TRN1_PPP_S: |
| 6255 | case AArch64::TRN2_PPP_B: |
| 6256 | case AArch64::TRN2_PPP_D: |
| 6257 | case AArch64::TRN2_PPP_H: |
| 6258 | case AArch64::TRN2_PPP_S: |
| 6259 | case AArch64::UZP1_PPP_B: |
| 6260 | case AArch64::UZP1_PPP_D: |
| 6261 | case AArch64::UZP1_PPP_H: |
| 6262 | case AArch64::UZP1_PPP_S: |
| 6263 | case AArch64::UZP2_PPP_B: |
| 6264 | case AArch64::UZP2_PPP_D: |
| 6265 | case AArch64::UZP2_PPP_H: |
| 6266 | case AArch64::UZP2_PPP_S: |
| 6267 | case AArch64::ZIP1_PPP_B: |
| 6268 | case AArch64::ZIP1_PPP_D: |
| 6269 | case AArch64::ZIP1_PPP_H: |
| 6270 | case AArch64::ZIP1_PPP_S: |
| 6271 | case AArch64::ZIP2_PPP_B: |
| 6272 | case AArch64::ZIP2_PPP_D: |
| 6273 | case AArch64::ZIP2_PPP_H: |
| 6274 | case AArch64::ZIP2_PPP_S: { |
| 6275 | // op: Pd |
| 6276 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6277 | op &= UINT64_C(15); |
| 6278 | Value |= op; |
| 6279 | // op: Pm |
| 6280 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6281 | op &= UINT64_C(15); |
| 6282 | op <<= 16; |
| 6283 | Value |= op; |
| 6284 | // op: Pn |
| 6285 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6286 | op &= UINT64_C(15); |
| 6287 | op <<= 5; |
| 6288 | Value |= op; |
| 6289 | break; |
| 6290 | } |
| 6291 | case AArch64::PUNPKHI_PP: |
| 6292 | case AArch64::PUNPKLO_PP: |
| 6293 | case AArch64::REV_PP_B: |
| 6294 | case AArch64::REV_PP_D: |
| 6295 | case AArch64::REV_PP_H: |
| 6296 | case AArch64::REV_PP_S: { |
| 6297 | // op: Pd |
| 6298 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6299 | op &= UINT64_C(15); |
| 6300 | Value |= op; |
| 6301 | // op: Pn |
| 6302 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6303 | op &= UINT64_C(15); |
| 6304 | op <<= 5; |
| 6305 | Value |= op; |
| 6306 | break; |
| 6307 | } |
| 6308 | case AArch64::WHILEGE_PWW_B: |
| 6309 | case AArch64::WHILEGE_PWW_D: |
| 6310 | case AArch64::WHILEGE_PWW_H: |
| 6311 | case AArch64::WHILEGE_PWW_S: |
| 6312 | case AArch64::WHILEGE_PXX_B: |
| 6313 | case AArch64::WHILEGE_PXX_D: |
| 6314 | case AArch64::WHILEGE_PXX_H: |
| 6315 | case AArch64::WHILEGE_PXX_S: |
| 6316 | case AArch64::WHILEGT_PWW_B: |
| 6317 | case AArch64::WHILEGT_PWW_D: |
| 6318 | case AArch64::WHILEGT_PWW_H: |
| 6319 | case AArch64::WHILEGT_PWW_S: |
| 6320 | case AArch64::WHILEGT_PXX_B: |
| 6321 | case AArch64::WHILEGT_PXX_D: |
| 6322 | case AArch64::WHILEGT_PXX_H: |
| 6323 | case AArch64::WHILEGT_PXX_S: |
| 6324 | case AArch64::WHILEHI_PWW_B: |
| 6325 | case AArch64::WHILEHI_PWW_D: |
| 6326 | case AArch64::WHILEHI_PWW_H: |
| 6327 | case AArch64::WHILEHI_PWW_S: |
| 6328 | case AArch64::WHILEHI_PXX_B: |
| 6329 | case AArch64::WHILEHI_PXX_D: |
| 6330 | case AArch64::WHILEHI_PXX_H: |
| 6331 | case AArch64::WHILEHI_PXX_S: |
| 6332 | case AArch64::WHILEHS_PWW_B: |
| 6333 | case AArch64::WHILEHS_PWW_D: |
| 6334 | case AArch64::WHILEHS_PWW_H: |
| 6335 | case AArch64::WHILEHS_PWW_S: |
| 6336 | case AArch64::WHILEHS_PXX_B: |
| 6337 | case AArch64::WHILEHS_PXX_D: |
| 6338 | case AArch64::WHILEHS_PXX_H: |
| 6339 | case AArch64::WHILEHS_PXX_S: |
| 6340 | case AArch64::WHILELE_PWW_B: |
| 6341 | case AArch64::WHILELE_PWW_D: |
| 6342 | case AArch64::WHILELE_PWW_H: |
| 6343 | case AArch64::WHILELE_PWW_S: |
| 6344 | case AArch64::WHILELE_PXX_B: |
| 6345 | case AArch64::WHILELE_PXX_D: |
| 6346 | case AArch64::WHILELE_PXX_H: |
| 6347 | case AArch64::WHILELE_PXX_S: |
| 6348 | case AArch64::WHILELO_PWW_B: |
| 6349 | case AArch64::WHILELO_PWW_D: |
| 6350 | case AArch64::WHILELO_PWW_H: |
| 6351 | case AArch64::WHILELO_PWW_S: |
| 6352 | case AArch64::WHILELO_PXX_B: |
| 6353 | case AArch64::WHILELO_PXX_D: |
| 6354 | case AArch64::WHILELO_PXX_H: |
| 6355 | case AArch64::WHILELO_PXX_S: |
| 6356 | case AArch64::WHILELS_PWW_B: |
| 6357 | case AArch64::WHILELS_PWW_D: |
| 6358 | case AArch64::WHILELS_PWW_H: |
| 6359 | case AArch64::WHILELS_PWW_S: |
| 6360 | case AArch64::WHILELS_PXX_B: |
| 6361 | case AArch64::WHILELS_PXX_D: |
| 6362 | case AArch64::WHILELS_PXX_H: |
| 6363 | case AArch64::WHILELS_PXX_S: |
| 6364 | case AArch64::WHILELT_PWW_B: |
| 6365 | case AArch64::WHILELT_PWW_D: |
| 6366 | case AArch64::WHILELT_PWW_H: |
| 6367 | case AArch64::WHILELT_PWW_S: |
| 6368 | case AArch64::WHILELT_PXX_B: |
| 6369 | case AArch64::WHILELT_PXX_D: |
| 6370 | case AArch64::WHILELT_PXX_H: |
| 6371 | case AArch64::WHILELT_PXX_S: |
| 6372 | case AArch64::WHILERW_PXX_B: |
| 6373 | case AArch64::WHILERW_PXX_D: |
| 6374 | case AArch64::WHILERW_PXX_H: |
| 6375 | case AArch64::WHILERW_PXX_S: |
| 6376 | case AArch64::WHILEWR_PXX_B: |
| 6377 | case AArch64::WHILEWR_PXX_D: |
| 6378 | case AArch64::WHILEWR_PXX_H: |
| 6379 | case AArch64::WHILEWR_PXX_S: { |
| 6380 | // op: Pd |
| 6381 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6382 | op &= UINT64_C(15); |
| 6383 | Value |= op; |
| 6384 | // op: Rm |
| 6385 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6386 | op &= UINT64_C(31); |
| 6387 | op <<= 16; |
| 6388 | Value |= op; |
| 6389 | // op: Rn |
| 6390 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6391 | op &= UINT64_C(31); |
| 6392 | op <<= 5; |
| 6393 | Value |= op; |
| 6394 | break; |
| 6395 | } |
| 6396 | case AArch64::PTRUES_B: |
| 6397 | case AArch64::PTRUES_D: |
| 6398 | case AArch64::PTRUES_H: |
| 6399 | case AArch64::PTRUES_S: |
| 6400 | case AArch64::PTRUE_B: |
| 6401 | case AArch64::PTRUE_D: |
| 6402 | case AArch64::PTRUE_H: |
| 6403 | case AArch64::PTRUE_S: { |
| 6404 | // op: Pd |
| 6405 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6406 | op &= UINT64_C(15); |
| 6407 | Value |= op; |
| 6408 | // op: pattern |
| 6409 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6410 | op &= UINT64_C(31); |
| 6411 | op <<= 5; |
| 6412 | Value |= op; |
| 6413 | break; |
| 6414 | } |
| 6415 | case AArch64::BRKNS_PPzP: |
| 6416 | case AArch64::BRKN_PPzP: { |
| 6417 | // op: Pdm |
| 6418 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6419 | op &= UINT64_C(15); |
| 6420 | Value |= op; |
| 6421 | // op: Pg |
| 6422 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6423 | op &= UINT64_C(15); |
| 6424 | op <<= 10; |
| 6425 | Value |= op; |
| 6426 | // op: Pn |
| 6427 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6428 | op &= UINT64_C(15); |
| 6429 | op <<= 5; |
| 6430 | Value |= op; |
| 6431 | break; |
| 6432 | } |
| 6433 | case AArch64::PFIRST_B: |
| 6434 | case AArch64::PNEXT_B: |
| 6435 | case AArch64::PNEXT_D: |
| 6436 | case AArch64::PNEXT_H: |
| 6437 | case AArch64::PNEXT_S: { |
| 6438 | // op: Pdn |
| 6439 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6440 | op &= UINT64_C(15); |
| 6441 | Value |= op; |
| 6442 | // op: Pg |
| 6443 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6444 | op &= UINT64_C(15); |
| 6445 | op <<= 5; |
| 6446 | Value |= op; |
| 6447 | break; |
| 6448 | } |
| 6449 | case AArch64::PTEST_PP: { |
| 6450 | // op: Pg |
| 6451 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6452 | op &= UINT64_C(15); |
| 6453 | op <<= 10; |
| 6454 | Value |= op; |
| 6455 | // op: Pn |
| 6456 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6457 | op &= UINT64_C(15); |
| 6458 | op <<= 5; |
| 6459 | Value |= op; |
| 6460 | break; |
| 6461 | } |
| 6462 | case AArch64::CNTP_XPP_B: |
| 6463 | case AArch64::CNTP_XPP_D: |
| 6464 | case AArch64::CNTP_XPP_H: |
| 6465 | case AArch64::CNTP_XPP_S: { |
| 6466 | // op: Pg |
| 6467 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6468 | op &= UINT64_C(15); |
| 6469 | op <<= 10; |
| 6470 | Value |= op; |
| 6471 | // op: Pn |
| 6472 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6473 | op &= UINT64_C(15); |
| 6474 | op <<= 5; |
| 6475 | Value |= op; |
| 6476 | // op: Rd |
| 6477 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6478 | op &= UINT64_C(31); |
| 6479 | Value |= op; |
| 6480 | break; |
| 6481 | } |
| 6482 | case AArch64::SEL_ZPZZ_B: |
| 6483 | case AArch64::SEL_ZPZZ_D: |
| 6484 | case AArch64::SEL_ZPZZ_H: |
| 6485 | case AArch64::SEL_ZPZZ_S: { |
| 6486 | // op: Pg |
| 6487 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6488 | op &= UINT64_C(15); |
| 6489 | op <<= 10; |
| 6490 | Value |= op; |
| 6491 | // op: Zd |
| 6492 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6493 | op &= UINT64_C(31); |
| 6494 | Value |= op; |
| 6495 | // op: Zm |
| 6496 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6497 | op &= UINT64_C(31); |
| 6498 | op <<= 16; |
| 6499 | Value |= op; |
| 6500 | // op: Zn |
| 6501 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6502 | op &= UINT64_C(31); |
| 6503 | op <<= 5; |
| 6504 | Value |= op; |
| 6505 | break; |
| 6506 | } |
| 6507 | case AArch64::LASTA_RPZ_B: |
| 6508 | case AArch64::LASTA_RPZ_D: |
| 6509 | case AArch64::LASTA_RPZ_H: |
| 6510 | case AArch64::LASTA_RPZ_S: |
| 6511 | case AArch64::LASTB_RPZ_B: |
| 6512 | case AArch64::LASTB_RPZ_D: |
| 6513 | case AArch64::LASTB_RPZ_H: |
| 6514 | case AArch64::LASTB_RPZ_S: { |
| 6515 | // op: Pg |
| 6516 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6517 | op &= UINT64_C(7); |
| 6518 | op <<= 10; |
| 6519 | Value |= op; |
| 6520 | // op: Rd |
| 6521 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6522 | op &= UINT64_C(31); |
| 6523 | Value |= op; |
| 6524 | // op: Zn |
| 6525 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6526 | op &= UINT64_C(31); |
| 6527 | op <<= 5; |
| 6528 | Value |= op; |
| 6529 | break; |
| 6530 | } |
| 6531 | case AArch64::CLASTA_RPZ_B: |
| 6532 | case AArch64::CLASTA_RPZ_D: |
| 6533 | case AArch64::CLASTA_RPZ_H: |
| 6534 | case AArch64::CLASTA_RPZ_S: |
| 6535 | case AArch64::CLASTB_RPZ_B: |
| 6536 | case AArch64::CLASTB_RPZ_D: |
| 6537 | case AArch64::CLASTB_RPZ_H: |
| 6538 | case AArch64::CLASTB_RPZ_S: { |
| 6539 | // op: Pg |
| 6540 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6541 | op &= UINT64_C(7); |
| 6542 | op <<= 10; |
| 6543 | Value |= op; |
| 6544 | // op: Rdn |
| 6545 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6546 | op &= UINT64_C(31); |
| 6547 | Value |= op; |
| 6548 | // op: Zm |
| 6549 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6550 | op &= UINT64_C(31); |
| 6551 | op <<= 5; |
| 6552 | Value |= op; |
| 6553 | break; |
| 6554 | } |
| 6555 | case AArch64::LD2B: |
| 6556 | case AArch64::LD2D: |
| 6557 | case AArch64::LD2H: |
| 6558 | case AArch64::LD2W: |
| 6559 | case AArch64::LD3B: |
| 6560 | case AArch64::LD3D: |
| 6561 | case AArch64::LD3H: |
| 6562 | case AArch64::LD3W: |
| 6563 | case AArch64::LD4B: |
| 6564 | case AArch64::LD4D: |
| 6565 | case AArch64::LD4H: |
| 6566 | case AArch64::LD4W: |
| 6567 | case AArch64::LDNT1B_ZRR: |
| 6568 | case AArch64::LDNT1D_ZRR: |
| 6569 | case AArch64::LDNT1H_ZRR: |
| 6570 | case AArch64::LDNT1W_ZRR: |
| 6571 | case AArch64::ST1B: |
| 6572 | case AArch64::ST1B_D: |
| 6573 | case AArch64::ST1B_H: |
| 6574 | case AArch64::ST1B_S: |
| 6575 | case AArch64::ST1D: |
| 6576 | case AArch64::ST1H: |
| 6577 | case AArch64::ST1H_D: |
| 6578 | case AArch64::ST1H_S: |
| 6579 | case AArch64::ST1W: |
| 6580 | case AArch64::ST1W_D: |
| 6581 | case AArch64::ST2B: |
| 6582 | case AArch64::ST2D: |
| 6583 | case AArch64::ST2H: |
| 6584 | case AArch64::ST2W: |
| 6585 | case AArch64::ST3B: |
| 6586 | case AArch64::ST3D: |
| 6587 | case AArch64::ST3H: |
| 6588 | case AArch64::ST3W: |
| 6589 | case AArch64::ST4B: |
| 6590 | case AArch64::ST4D: |
| 6591 | case AArch64::ST4H: |
| 6592 | case AArch64::ST4W: |
| 6593 | case AArch64::STNT1B_ZRR: |
| 6594 | case AArch64::STNT1D_ZRR: |
| 6595 | case AArch64::STNT1H_ZRR: |
| 6596 | case AArch64::STNT1W_ZRR: { |
| 6597 | // op: Pg |
| 6598 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6599 | op &= UINT64_C(7); |
| 6600 | op <<= 10; |
| 6601 | Value |= op; |
| 6602 | // op: Rm |
| 6603 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6604 | op &= UINT64_C(31); |
| 6605 | op <<= 16; |
| 6606 | Value |= op; |
| 6607 | // op: Rn |
| 6608 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6609 | op &= UINT64_C(31); |
| 6610 | op <<= 5; |
| 6611 | Value |= op; |
| 6612 | // op: Zt |
| 6613 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6614 | op &= UINT64_C(31); |
| 6615 | Value |= op; |
| 6616 | break; |
| 6617 | } |
| 6618 | case AArch64::LDNT1B_ZZR_D_REAL: |
| 6619 | case AArch64::LDNT1B_ZZR_S_REAL: |
| 6620 | case AArch64::LDNT1D_ZZR_D_REAL: |
| 6621 | case AArch64::LDNT1H_ZZR_D_REAL: |
| 6622 | case AArch64::LDNT1H_ZZR_S_REAL: |
| 6623 | case AArch64::LDNT1SB_ZZR_D_REAL: |
| 6624 | case AArch64::LDNT1SB_ZZR_S_REAL: |
| 6625 | case AArch64::LDNT1SH_ZZR_D_REAL: |
| 6626 | case AArch64::LDNT1SH_ZZR_S_REAL: |
| 6627 | case AArch64::LDNT1SW_ZZR_D_REAL: |
| 6628 | case AArch64::LDNT1W_ZZR_D_REAL: |
| 6629 | case AArch64::LDNT1W_ZZR_S_REAL: |
| 6630 | case AArch64::STNT1B_ZZR_D_REAL: |
| 6631 | case AArch64::STNT1B_ZZR_S_REAL: |
| 6632 | case AArch64::STNT1D_ZZR_D_REAL: |
| 6633 | case AArch64::STNT1H_ZZR_D_REAL: |
| 6634 | case AArch64::STNT1H_ZZR_S_REAL: |
| 6635 | case AArch64::STNT1W_ZZR_D_REAL: |
| 6636 | case AArch64::STNT1W_ZZR_S_REAL: { |
| 6637 | // op: Pg |
| 6638 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6639 | op &= UINT64_C(7); |
| 6640 | op <<= 10; |
| 6641 | Value |= op; |
| 6642 | // op: Rm |
| 6643 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6644 | op &= UINT64_C(31); |
| 6645 | op <<= 16; |
| 6646 | Value |= op; |
| 6647 | // op: Zn |
| 6648 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6649 | op &= UINT64_C(31); |
| 6650 | op <<= 5; |
| 6651 | Value |= op; |
| 6652 | // op: Zt |
| 6653 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6654 | op &= UINT64_C(31); |
| 6655 | Value |= op; |
| 6656 | break; |
| 6657 | } |
| 6658 | case AArch64::GLD1B_D_REAL: |
| 6659 | case AArch64::GLD1B_D_SXTW_REAL: |
| 6660 | case AArch64::GLD1B_D_UXTW_REAL: |
| 6661 | case AArch64::GLD1B_S_SXTW_REAL: |
| 6662 | case AArch64::GLD1B_S_UXTW_REAL: |
| 6663 | case AArch64::GLD1D_REAL: |
| 6664 | case AArch64::GLD1D_SCALED_REAL: |
| 6665 | case AArch64::GLD1D_SXTW_REAL: |
| 6666 | case AArch64::GLD1D_SXTW_SCALED_REAL: |
| 6667 | case AArch64::GLD1D_UXTW_REAL: |
| 6668 | case AArch64::GLD1D_UXTW_SCALED_REAL: |
| 6669 | case AArch64::GLD1H_D_REAL: |
| 6670 | case AArch64::GLD1H_D_SCALED_REAL: |
| 6671 | case AArch64::GLD1H_D_SXTW_REAL: |
| 6672 | case AArch64::GLD1H_D_SXTW_SCALED_REAL: |
| 6673 | case AArch64::GLD1H_D_UXTW_REAL: |
| 6674 | case AArch64::GLD1H_D_UXTW_SCALED_REAL: |
| 6675 | case AArch64::GLD1H_S_SXTW_REAL: |
| 6676 | case AArch64::GLD1H_S_SXTW_SCALED_REAL: |
| 6677 | case AArch64::GLD1H_S_UXTW_REAL: |
| 6678 | case AArch64::GLD1H_S_UXTW_SCALED_REAL: |
| 6679 | case AArch64::GLD1SB_D_REAL: |
| 6680 | case AArch64::GLD1SB_D_SXTW_REAL: |
| 6681 | case AArch64::GLD1SB_D_UXTW_REAL: |
| 6682 | case AArch64::GLD1SB_S_SXTW_REAL: |
| 6683 | case AArch64::GLD1SB_S_UXTW_REAL: |
| 6684 | case AArch64::GLD1SH_D_REAL: |
| 6685 | case AArch64::GLD1SH_D_SCALED_REAL: |
| 6686 | case AArch64::GLD1SH_D_SXTW_REAL: |
| 6687 | case AArch64::GLD1SH_D_SXTW_SCALED_REAL: |
| 6688 | case AArch64::GLD1SH_D_UXTW_REAL: |
| 6689 | case AArch64::GLD1SH_D_UXTW_SCALED_REAL: |
| 6690 | case AArch64::GLD1SH_S_SXTW_REAL: |
| 6691 | case AArch64::GLD1SH_S_SXTW_SCALED_REAL: |
| 6692 | case AArch64::GLD1SH_S_UXTW_REAL: |
| 6693 | case AArch64::GLD1SH_S_UXTW_SCALED_REAL: |
| 6694 | case AArch64::GLD1SW_D_REAL: |
| 6695 | case AArch64::GLD1SW_D_SCALED_REAL: |
| 6696 | case AArch64::GLD1SW_D_SXTW_REAL: |
| 6697 | case AArch64::GLD1SW_D_SXTW_SCALED_REAL: |
| 6698 | case AArch64::GLD1SW_D_UXTW_REAL: |
| 6699 | case AArch64::GLD1SW_D_UXTW_SCALED_REAL: |
| 6700 | case AArch64::GLD1W_D_REAL: |
| 6701 | case AArch64::GLD1W_D_SCALED_REAL: |
| 6702 | case AArch64::GLD1W_D_SXTW_REAL: |
| 6703 | case AArch64::GLD1W_D_SXTW_SCALED_REAL: |
| 6704 | case AArch64::GLD1W_D_UXTW_REAL: |
| 6705 | case AArch64::GLD1W_D_UXTW_SCALED_REAL: |
| 6706 | case AArch64::GLD1W_SXTW_REAL: |
| 6707 | case AArch64::GLD1W_SXTW_SCALED_REAL: |
| 6708 | case AArch64::GLD1W_UXTW_REAL: |
| 6709 | case AArch64::GLD1W_UXTW_SCALED_REAL: |
| 6710 | case AArch64::GLDFF1B_D_REAL: |
| 6711 | case AArch64::GLDFF1B_D_SXTW_REAL: |
| 6712 | case AArch64::GLDFF1B_D_UXTW_REAL: |
| 6713 | case AArch64::GLDFF1B_S_SXTW_REAL: |
| 6714 | case AArch64::GLDFF1B_S_UXTW_REAL: |
| 6715 | case AArch64::GLDFF1D_REAL: |
| 6716 | case AArch64::GLDFF1D_SCALED_REAL: |
| 6717 | case AArch64::GLDFF1D_SXTW_REAL: |
| 6718 | case AArch64::GLDFF1D_SXTW_SCALED_REAL: |
| 6719 | case AArch64::GLDFF1D_UXTW_REAL: |
| 6720 | case AArch64::GLDFF1D_UXTW_SCALED_REAL: |
| 6721 | case AArch64::GLDFF1H_D_REAL: |
| 6722 | case AArch64::GLDFF1H_D_SCALED_REAL: |
| 6723 | case AArch64::GLDFF1H_D_SXTW_REAL: |
| 6724 | case AArch64::GLDFF1H_D_SXTW_SCALED_REAL: |
| 6725 | case AArch64::GLDFF1H_D_UXTW_REAL: |
| 6726 | case AArch64::GLDFF1H_D_UXTW_SCALED_REAL: |
| 6727 | case AArch64::GLDFF1H_S_SXTW_REAL: |
| 6728 | case AArch64::GLDFF1H_S_SXTW_SCALED_REAL: |
| 6729 | case AArch64::GLDFF1H_S_UXTW_REAL: |
| 6730 | case AArch64::GLDFF1H_S_UXTW_SCALED_REAL: |
| 6731 | case AArch64::GLDFF1SB_D_REAL: |
| 6732 | case AArch64::GLDFF1SB_D_SXTW_REAL: |
| 6733 | case AArch64::GLDFF1SB_D_UXTW_REAL: |
| 6734 | case AArch64::GLDFF1SB_S_SXTW_REAL: |
| 6735 | case AArch64::GLDFF1SB_S_UXTW_REAL: |
| 6736 | case AArch64::GLDFF1SH_D_REAL: |
| 6737 | case AArch64::GLDFF1SH_D_SCALED_REAL: |
| 6738 | case AArch64::GLDFF1SH_D_SXTW_REAL: |
| 6739 | case AArch64::GLDFF1SH_D_SXTW_SCALED_REAL: |
| 6740 | case AArch64::GLDFF1SH_D_UXTW_REAL: |
| 6741 | case AArch64::GLDFF1SH_D_UXTW_SCALED_REAL: |
| 6742 | case AArch64::GLDFF1SH_S_SXTW_REAL: |
| 6743 | case AArch64::GLDFF1SH_S_SXTW_SCALED_REAL: |
| 6744 | case AArch64::GLDFF1SH_S_UXTW_REAL: |
| 6745 | case AArch64::GLDFF1SH_S_UXTW_SCALED_REAL: |
| 6746 | case AArch64::GLDFF1SW_D_REAL: |
| 6747 | case AArch64::GLDFF1SW_D_SCALED_REAL: |
| 6748 | case AArch64::GLDFF1SW_D_SXTW_REAL: |
| 6749 | case AArch64::GLDFF1SW_D_SXTW_SCALED_REAL: |
| 6750 | case AArch64::GLDFF1SW_D_UXTW_REAL: |
| 6751 | case AArch64::GLDFF1SW_D_UXTW_SCALED_REAL: |
| 6752 | case AArch64::GLDFF1W_D_REAL: |
| 6753 | case AArch64::GLDFF1W_D_SCALED_REAL: |
| 6754 | case AArch64::GLDFF1W_D_SXTW_REAL: |
| 6755 | case AArch64::GLDFF1W_D_SXTW_SCALED_REAL: |
| 6756 | case AArch64::GLDFF1W_D_UXTW_REAL: |
| 6757 | case AArch64::GLDFF1W_D_UXTW_SCALED_REAL: |
| 6758 | case AArch64::GLDFF1W_SXTW_REAL: |
| 6759 | case AArch64::GLDFF1W_SXTW_SCALED_REAL: |
| 6760 | case AArch64::GLDFF1W_UXTW_REAL: |
| 6761 | case AArch64::GLDFF1W_UXTW_SCALED_REAL: |
| 6762 | case AArch64::SST1B_D_REAL: |
| 6763 | case AArch64::SST1B_D_SXTW: |
| 6764 | case AArch64::SST1B_D_UXTW: |
| 6765 | case AArch64::SST1B_S_SXTW: |
| 6766 | case AArch64::SST1B_S_UXTW: |
| 6767 | case AArch64::SST1D_REAL: |
| 6768 | case AArch64::SST1D_SCALED_SCALED_REAL: |
| 6769 | case AArch64::SST1D_SXTW: |
| 6770 | case AArch64::SST1D_SXTW_SCALED: |
| 6771 | case AArch64::SST1D_UXTW: |
| 6772 | case AArch64::SST1D_UXTW_SCALED: |
| 6773 | case AArch64::SST1H_D_REAL: |
| 6774 | case AArch64::SST1H_D_SCALED_SCALED_REAL: |
| 6775 | case AArch64::SST1H_D_SXTW: |
| 6776 | case AArch64::SST1H_D_SXTW_SCALED: |
| 6777 | case AArch64::SST1H_D_UXTW: |
| 6778 | case AArch64::SST1H_D_UXTW_SCALED: |
| 6779 | case AArch64::SST1H_S_SXTW: |
| 6780 | case AArch64::SST1H_S_SXTW_SCALED: |
| 6781 | case AArch64::SST1H_S_UXTW: |
| 6782 | case AArch64::SST1H_S_UXTW_SCALED: |
| 6783 | case AArch64::SST1W_D_REAL: |
| 6784 | case AArch64::SST1W_D_SCALED_SCALED_REAL: |
| 6785 | case AArch64::SST1W_D_SXTW: |
| 6786 | case AArch64::SST1W_D_SXTW_SCALED: |
| 6787 | case AArch64::SST1W_D_UXTW: |
| 6788 | case AArch64::SST1W_D_UXTW_SCALED: |
| 6789 | case AArch64::SST1W_SXTW: |
| 6790 | case AArch64::SST1W_SXTW_SCALED: |
| 6791 | case AArch64::SST1W_UXTW: |
| 6792 | case AArch64::SST1W_UXTW_SCALED: { |
| 6793 | // op: Pg |
| 6794 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6795 | op &= UINT64_C(7); |
| 6796 | op <<= 10; |
| 6797 | Value |= op; |
| 6798 | // op: Rn |
| 6799 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6800 | op &= UINT64_C(31); |
| 6801 | op <<= 5; |
| 6802 | Value |= op; |
| 6803 | // op: Zm |
| 6804 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6805 | op &= UINT64_C(31); |
| 6806 | op <<= 16; |
| 6807 | Value |= op; |
| 6808 | // op: Zt |
| 6809 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6810 | op &= UINT64_C(31); |
| 6811 | Value |= op; |
| 6812 | break; |
| 6813 | } |
| 6814 | case AArch64::PRFB_D_SCALED: |
| 6815 | case AArch64::PRFB_D_SXTW_SCALED: |
| 6816 | case AArch64::PRFB_D_UXTW_SCALED: |
| 6817 | case AArch64::PRFB_S_SXTW_SCALED: |
| 6818 | case AArch64::PRFB_S_UXTW_SCALED: |
| 6819 | case AArch64::PRFD_D_SCALED: |
| 6820 | case AArch64::PRFD_D_SXTW_SCALED: |
| 6821 | case AArch64::PRFD_D_UXTW_SCALED: |
| 6822 | case AArch64::PRFD_S_SXTW_SCALED: |
| 6823 | case AArch64::PRFD_S_UXTW_SCALED: |
| 6824 | case AArch64::PRFH_D_SCALED: |
| 6825 | case AArch64::PRFH_D_SXTW_SCALED: |
| 6826 | case AArch64::PRFH_D_UXTW_SCALED: |
| 6827 | case AArch64::PRFH_S_SXTW_SCALED: |
| 6828 | case AArch64::PRFH_S_UXTW_SCALED: |
| 6829 | case AArch64::PRFW_D_SCALED: |
| 6830 | case AArch64::PRFW_D_SXTW_SCALED: |
| 6831 | case AArch64::PRFW_D_UXTW_SCALED: |
| 6832 | case AArch64::PRFW_S_SXTW_SCALED: |
| 6833 | case AArch64::PRFW_S_UXTW_SCALED: { |
| 6834 | // op: Pg |
| 6835 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6836 | op &= UINT64_C(7); |
| 6837 | op <<= 10; |
| 6838 | Value |= op; |
| 6839 | // op: Rn |
| 6840 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6841 | op &= UINT64_C(31); |
| 6842 | op <<= 5; |
| 6843 | Value |= op; |
| 6844 | // op: Zm |
| 6845 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6846 | op &= UINT64_C(31); |
| 6847 | op <<= 16; |
| 6848 | Value |= op; |
| 6849 | // op: prfop |
| 6850 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6851 | op &= UINT64_C(15); |
| 6852 | Value |= op; |
| 6853 | break; |
| 6854 | } |
| 6855 | case AArch64::LD1B_D_IMM_REAL: |
| 6856 | case AArch64::LD1B_H_IMM_REAL: |
| 6857 | case AArch64::LD1B_IMM_REAL: |
| 6858 | case AArch64::LD1B_S_IMM_REAL: |
| 6859 | case AArch64::LD1D_IMM_REAL: |
| 6860 | case AArch64::LD1H_D_IMM_REAL: |
| 6861 | case AArch64::LD1H_IMM_REAL: |
| 6862 | case AArch64::LD1H_S_IMM_REAL: |
| 6863 | case AArch64::LD1SB_D_IMM_REAL: |
| 6864 | case AArch64::LD1SB_H_IMM_REAL: |
| 6865 | case AArch64::LD1SB_S_IMM_REAL: |
| 6866 | case AArch64::LD1SH_D_IMM_REAL: |
| 6867 | case AArch64::LD1SH_S_IMM_REAL: |
| 6868 | case AArch64::LD1SW_D_IMM_REAL: |
| 6869 | case AArch64::LD1W_D_IMM_REAL: |
| 6870 | case AArch64::LD1W_IMM_REAL: |
| 6871 | case AArch64::LDNF1B_D_IMM_REAL: |
| 6872 | case AArch64::LDNF1B_H_IMM_REAL: |
| 6873 | case AArch64::LDNF1B_IMM_REAL: |
| 6874 | case AArch64::LDNF1B_S_IMM_REAL: |
| 6875 | case AArch64::LDNF1D_IMM_REAL: |
| 6876 | case AArch64::LDNF1H_D_IMM_REAL: |
| 6877 | case AArch64::LDNF1H_IMM_REAL: |
| 6878 | case AArch64::LDNF1H_S_IMM_REAL: |
| 6879 | case AArch64::LDNF1SB_D_IMM_REAL: |
| 6880 | case AArch64::LDNF1SB_H_IMM_REAL: |
| 6881 | case AArch64::LDNF1SB_S_IMM_REAL: |
| 6882 | case AArch64::LDNF1SH_D_IMM_REAL: |
| 6883 | case AArch64::LDNF1SH_S_IMM_REAL: |
| 6884 | case AArch64::LDNF1SW_D_IMM_REAL: |
| 6885 | case AArch64::LDNF1W_D_IMM_REAL: |
| 6886 | case AArch64::LDNF1W_IMM_REAL: |
| 6887 | case AArch64::ST1B_D_IMM: |
| 6888 | case AArch64::ST1B_H_IMM: |
| 6889 | case AArch64::ST1B_IMM: |
| 6890 | case AArch64::ST1B_S_IMM: |
| 6891 | case AArch64::ST1D_IMM: |
| 6892 | case AArch64::ST1H_D_IMM: |
| 6893 | case AArch64::ST1H_IMM: |
| 6894 | case AArch64::ST1H_S_IMM: |
| 6895 | case AArch64::ST1W_D_IMM: |
| 6896 | case AArch64::ST1W_IMM: |
| 6897 | case AArch64::ST2B_IMM: |
| 6898 | case AArch64::ST2D_IMM: |
| 6899 | case AArch64::ST2H_IMM: |
| 6900 | case AArch64::ST2W_IMM: |
| 6901 | case AArch64::ST3B_IMM: |
| 6902 | case AArch64::ST3D_IMM: |
| 6903 | case AArch64::ST3H_IMM: |
| 6904 | case AArch64::ST3W_IMM: |
| 6905 | case AArch64::ST4B_IMM: |
| 6906 | case AArch64::ST4D_IMM: |
| 6907 | case AArch64::ST4H_IMM: |
| 6908 | case AArch64::ST4W_IMM: |
| 6909 | case AArch64::STNT1B_ZRI: |
| 6910 | case AArch64::STNT1D_ZRI: |
| 6911 | case AArch64::STNT1H_ZRI: |
| 6912 | case AArch64::STNT1W_ZRI: { |
| 6913 | // op: Pg |
| 6914 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6915 | op &= UINT64_C(7); |
| 6916 | op <<= 10; |
| 6917 | Value |= op; |
| 6918 | // op: Rn |
| 6919 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6920 | op &= UINT64_C(31); |
| 6921 | op <<= 5; |
| 6922 | Value |= op; |
| 6923 | // op: Zt |
| 6924 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6925 | op &= UINT64_C(31); |
| 6926 | Value |= op; |
| 6927 | // op: imm4 |
| 6928 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6929 | op &= UINT64_C(15); |
| 6930 | op <<= 16; |
| 6931 | Value |= op; |
| 6932 | break; |
| 6933 | } |
| 6934 | case AArch64::LD1RB_D_IMM: |
| 6935 | case AArch64::LD1RB_H_IMM: |
| 6936 | case AArch64::LD1RB_IMM: |
| 6937 | case AArch64::LD1RB_S_IMM: |
| 6938 | case AArch64::LD1RD_IMM: |
| 6939 | case AArch64::LD1RH_D_IMM: |
| 6940 | case AArch64::LD1RH_IMM: |
| 6941 | case AArch64::LD1RH_S_IMM: |
| 6942 | case AArch64::LD1RSB_D_IMM: |
| 6943 | case AArch64::LD1RSB_H_IMM: |
| 6944 | case AArch64::LD1RSB_S_IMM: |
| 6945 | case AArch64::LD1RSH_D_IMM: |
| 6946 | case AArch64::LD1RSH_S_IMM: |
| 6947 | case AArch64::LD1RSW_IMM: |
| 6948 | case AArch64::LD1RW_D_IMM: |
| 6949 | case AArch64::LD1RW_IMM: { |
| 6950 | // op: Pg |
| 6951 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 6952 | op &= UINT64_C(7); |
| 6953 | op <<= 10; |
| 6954 | Value |= op; |
| 6955 | // op: Rn |
| 6956 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 6957 | op &= UINT64_C(31); |
| 6958 | op <<= 5; |
| 6959 | Value |= op; |
| 6960 | // op: Zt |
| 6961 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 6962 | op &= UINT64_C(31); |
| 6963 | Value |= op; |
| 6964 | // op: imm6 |
| 6965 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 6966 | op &= UINT64_C(63); |
| 6967 | op <<= 16; |
| 6968 | Value |= op; |
| 6969 | break; |
| 6970 | } |
| 6971 | case AArch64::ANDV_VPZ_B: |
| 6972 | case AArch64::ANDV_VPZ_D: |
| 6973 | case AArch64::ANDV_VPZ_H: |
| 6974 | case AArch64::ANDV_VPZ_S: |
| 6975 | case AArch64::EORV_VPZ_B: |
| 6976 | case AArch64::EORV_VPZ_D: |
| 6977 | case AArch64::EORV_VPZ_H: |
| 6978 | case AArch64::EORV_VPZ_S: |
| 6979 | case AArch64::LASTA_VPZ_B: |
| 6980 | case AArch64::LASTA_VPZ_D: |
| 6981 | case AArch64::LASTA_VPZ_H: |
| 6982 | case AArch64::LASTA_VPZ_S: |
| 6983 | case AArch64::LASTB_VPZ_B: |
| 6984 | case AArch64::LASTB_VPZ_D: |
| 6985 | case AArch64::LASTB_VPZ_H: |
| 6986 | case AArch64::LASTB_VPZ_S: |
| 6987 | case AArch64::ORV_VPZ_B: |
| 6988 | case AArch64::ORV_VPZ_D: |
| 6989 | case AArch64::ORV_VPZ_H: |
| 6990 | case AArch64::ORV_VPZ_S: |
| 6991 | case AArch64::SADDV_VPZ_B: |
| 6992 | case AArch64::SADDV_VPZ_H: |
| 6993 | case AArch64::SADDV_VPZ_S: |
| 6994 | case AArch64::SMAXV_VPZ_B: |
| 6995 | case AArch64::SMAXV_VPZ_D: |
| 6996 | case AArch64::SMAXV_VPZ_H: |
| 6997 | case AArch64::SMAXV_VPZ_S: |
| 6998 | case AArch64::SMINV_VPZ_B: |
| 6999 | case AArch64::SMINV_VPZ_D: |
| 7000 | case AArch64::SMINV_VPZ_H: |
| 7001 | case AArch64::SMINV_VPZ_S: |
| 7002 | case AArch64::UADDV_VPZ_B: |
| 7003 | case AArch64::UADDV_VPZ_D: |
| 7004 | case AArch64::UADDV_VPZ_H: |
| 7005 | case AArch64::UADDV_VPZ_S: |
| 7006 | case AArch64::UMAXV_VPZ_B: |
| 7007 | case AArch64::UMAXV_VPZ_D: |
| 7008 | case AArch64::UMAXV_VPZ_H: |
| 7009 | case AArch64::UMAXV_VPZ_S: |
| 7010 | case AArch64::UMINV_VPZ_B: |
| 7011 | case AArch64::UMINV_VPZ_D: |
| 7012 | case AArch64::UMINV_VPZ_H: |
| 7013 | case AArch64::UMINV_VPZ_S: { |
| 7014 | // op: Pg |
| 7015 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7016 | op &= UINT64_C(7); |
| 7017 | op <<= 10; |
| 7018 | Value |= op; |
| 7019 | // op: Vd |
| 7020 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7021 | op &= UINT64_C(31); |
| 7022 | Value |= op; |
| 7023 | // op: Zn |
| 7024 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7025 | op &= UINT64_C(31); |
| 7026 | op <<= 5; |
| 7027 | Value |= op; |
| 7028 | break; |
| 7029 | } |
| 7030 | case AArch64::CLASTA_VPZ_B: |
| 7031 | case AArch64::CLASTA_VPZ_D: |
| 7032 | case AArch64::CLASTA_VPZ_H: |
| 7033 | case AArch64::CLASTA_VPZ_S: |
| 7034 | case AArch64::CLASTB_VPZ_B: |
| 7035 | case AArch64::CLASTB_VPZ_D: |
| 7036 | case AArch64::CLASTB_VPZ_H: |
| 7037 | case AArch64::CLASTB_VPZ_S: |
| 7038 | case AArch64::FADDA_VPZ_D: |
| 7039 | case AArch64::FADDA_VPZ_H: |
| 7040 | case AArch64::FADDA_VPZ_S: { |
| 7041 | // op: Pg |
| 7042 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7043 | op &= UINT64_C(7); |
| 7044 | op <<= 10; |
| 7045 | Value |= op; |
| 7046 | // op: Vdn |
| 7047 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7048 | op &= UINT64_C(31); |
| 7049 | Value |= op; |
| 7050 | // op: Zm |
| 7051 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7052 | op &= UINT64_C(31); |
| 7053 | op <<= 5; |
| 7054 | Value |= op; |
| 7055 | break; |
| 7056 | } |
| 7057 | case AArch64::FMAD_ZPmZZ_D: |
| 7058 | case AArch64::FMAD_ZPmZZ_H: |
| 7059 | case AArch64::FMAD_ZPmZZ_S: |
| 7060 | case AArch64::FMSB_ZPmZZ_D: |
| 7061 | case AArch64::FMSB_ZPmZZ_H: |
| 7062 | case AArch64::FMSB_ZPmZZ_S: |
| 7063 | case AArch64::FNMAD_ZPmZZ_D: |
| 7064 | case AArch64::FNMAD_ZPmZZ_H: |
| 7065 | case AArch64::FNMAD_ZPmZZ_S: |
| 7066 | case AArch64::FNMSB_ZPmZZ_D: |
| 7067 | case AArch64::FNMSB_ZPmZZ_H: |
| 7068 | case AArch64::FNMSB_ZPmZZ_S: { |
| 7069 | // op: Pg |
| 7070 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7071 | op &= UINT64_C(7); |
| 7072 | op <<= 10; |
| 7073 | Value |= op; |
| 7074 | // op: Za |
| 7075 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 7076 | op &= UINT64_C(31); |
| 7077 | op <<= 16; |
| 7078 | Value |= op; |
| 7079 | // op: Zdn |
| 7080 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7081 | op &= UINT64_C(31); |
| 7082 | Value |= op; |
| 7083 | // op: Zm |
| 7084 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7085 | op &= UINT64_C(31); |
| 7086 | op <<= 5; |
| 7087 | Value |= op; |
| 7088 | break; |
| 7089 | } |
| 7090 | case AArch64::COMPACT_ZPZ_D: |
| 7091 | case AArch64::COMPACT_ZPZ_S: |
| 7092 | case AArch64::MOVPRFX_ZPzZ_B: |
| 7093 | case AArch64::MOVPRFX_ZPzZ_D: |
| 7094 | case AArch64::MOVPRFX_ZPzZ_H: |
| 7095 | case AArch64::MOVPRFX_ZPzZ_S: { |
| 7096 | // op: Pg |
| 7097 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7098 | op &= UINT64_C(7); |
| 7099 | op <<= 10; |
| 7100 | Value |= op; |
| 7101 | // op: Zd |
| 7102 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7103 | op &= UINT64_C(31); |
| 7104 | Value |= op; |
| 7105 | // op: Zn |
| 7106 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7107 | op &= UINT64_C(31); |
| 7108 | op <<= 5; |
| 7109 | Value |= op; |
| 7110 | break; |
| 7111 | } |
| 7112 | case AArch64::FMLA_ZPmZZ_D: |
| 7113 | case AArch64::FMLA_ZPmZZ_H: |
| 7114 | case AArch64::FMLA_ZPmZZ_S: |
| 7115 | case AArch64::FMLS_ZPmZZ_D: |
| 7116 | case AArch64::FMLS_ZPmZZ_H: |
| 7117 | case AArch64::FMLS_ZPmZZ_S: |
| 7118 | case AArch64::FNMLA_ZPmZZ_D: |
| 7119 | case AArch64::FNMLA_ZPmZZ_H: |
| 7120 | case AArch64::FNMLA_ZPmZZ_S: |
| 7121 | case AArch64::FNMLS_ZPmZZ_D: |
| 7122 | case AArch64::FNMLS_ZPmZZ_H: |
| 7123 | case AArch64::FNMLS_ZPmZZ_S: |
| 7124 | case AArch64::MLA_ZPmZZ_B: |
| 7125 | case AArch64::MLA_ZPmZZ_D: |
| 7126 | case AArch64::MLA_ZPmZZ_H: |
| 7127 | case AArch64::MLA_ZPmZZ_S: |
| 7128 | case AArch64::MLS_ZPmZZ_B: |
| 7129 | case AArch64::MLS_ZPmZZ_D: |
| 7130 | case AArch64::MLS_ZPmZZ_H: |
| 7131 | case AArch64::MLS_ZPmZZ_S: { |
| 7132 | // op: Pg |
| 7133 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7134 | op &= UINT64_C(7); |
| 7135 | op <<= 10; |
| 7136 | Value |= op; |
| 7137 | // op: Zda |
| 7138 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7139 | op &= UINT64_C(31); |
| 7140 | Value |= op; |
| 7141 | // op: Zm |
| 7142 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 7143 | op &= UINT64_C(31); |
| 7144 | op <<= 16; |
| 7145 | Value |= op; |
| 7146 | // op: Zn |
| 7147 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7148 | op &= UINT64_C(31); |
| 7149 | op <<= 5; |
| 7150 | Value |= op; |
| 7151 | break; |
| 7152 | } |
| 7153 | case AArch64::MAD_ZPmZZ_B: |
| 7154 | case AArch64::MAD_ZPmZZ_D: |
| 7155 | case AArch64::MAD_ZPmZZ_H: |
| 7156 | case AArch64::MAD_ZPmZZ_S: |
| 7157 | case AArch64::MSB_ZPmZZ_B: |
| 7158 | case AArch64::MSB_ZPmZZ_D: |
| 7159 | case AArch64::MSB_ZPmZZ_H: |
| 7160 | case AArch64::MSB_ZPmZZ_S: { |
| 7161 | // op: Pg |
| 7162 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7163 | op &= UINT64_C(7); |
| 7164 | op <<= 10; |
| 7165 | Value |= op; |
| 7166 | // op: Zdn |
| 7167 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7168 | op &= UINT64_C(31); |
| 7169 | Value |= op; |
| 7170 | // op: Za |
| 7171 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 7172 | op &= UINT64_C(31); |
| 7173 | op <<= 5; |
| 7174 | Value |= op; |
| 7175 | // op: Zm |
| 7176 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7177 | op &= UINT64_C(31); |
| 7178 | op <<= 16; |
| 7179 | Value |= op; |
| 7180 | break; |
| 7181 | } |
| 7182 | case AArch64::ADD_ZPmZ_B: |
| 7183 | case AArch64::ADD_ZPmZ_D: |
| 7184 | case AArch64::ADD_ZPmZ_H: |
| 7185 | case AArch64::ADD_ZPmZ_S: |
| 7186 | case AArch64::AND_ZPmZ_B: |
| 7187 | case AArch64::AND_ZPmZ_D: |
| 7188 | case AArch64::AND_ZPmZ_H: |
| 7189 | case AArch64::AND_ZPmZ_S: |
| 7190 | case AArch64::ASRR_ZPmZ_B: |
| 7191 | case AArch64::ASRR_ZPmZ_D: |
| 7192 | case AArch64::ASRR_ZPmZ_H: |
| 7193 | case AArch64::ASRR_ZPmZ_S: |
| 7194 | case AArch64::ASR_WIDE_ZPmZ_B: |
| 7195 | case AArch64::ASR_WIDE_ZPmZ_H: |
| 7196 | case AArch64::ASR_WIDE_ZPmZ_S: |
| 7197 | case AArch64::ASR_ZPmZ_B: |
| 7198 | case AArch64::ASR_ZPmZ_D: |
| 7199 | case AArch64::ASR_ZPmZ_H: |
| 7200 | case AArch64::ASR_ZPmZ_S: |
| 7201 | case AArch64::BIC_ZPmZ_B: |
| 7202 | case AArch64::BIC_ZPmZ_D: |
| 7203 | case AArch64::BIC_ZPmZ_H: |
| 7204 | case AArch64::BIC_ZPmZ_S: |
| 7205 | case AArch64::CLASTA_ZPZ_B: |
| 7206 | case AArch64::CLASTA_ZPZ_D: |
| 7207 | case AArch64::CLASTA_ZPZ_H: |
| 7208 | case AArch64::CLASTA_ZPZ_S: |
| 7209 | case AArch64::CLASTB_ZPZ_B: |
| 7210 | case AArch64::CLASTB_ZPZ_D: |
| 7211 | case AArch64::CLASTB_ZPZ_H: |
| 7212 | case AArch64::CLASTB_ZPZ_S: |
| 7213 | case AArch64::EOR_ZPmZ_B: |
| 7214 | case AArch64::EOR_ZPmZ_D: |
| 7215 | case AArch64::EOR_ZPmZ_H: |
| 7216 | case AArch64::EOR_ZPmZ_S: |
| 7217 | case AArch64::FABD_ZPmZ_D: |
| 7218 | case AArch64::FABD_ZPmZ_H: |
| 7219 | case AArch64::FABD_ZPmZ_S: |
| 7220 | case AArch64::FADD_ZPmZ_D: |
| 7221 | case AArch64::FADD_ZPmZ_H: |
| 7222 | case AArch64::FADD_ZPmZ_S: |
| 7223 | case AArch64::FDIVR_ZPmZ_D: |
| 7224 | case AArch64::FDIVR_ZPmZ_H: |
| 7225 | case AArch64::FDIVR_ZPmZ_S: |
| 7226 | case AArch64::FDIV_ZPmZ_D: |
| 7227 | case AArch64::FDIV_ZPmZ_H: |
| 7228 | case AArch64::FDIV_ZPmZ_S: |
| 7229 | case AArch64::FMAXNM_ZPmZ_D: |
| 7230 | case AArch64::FMAXNM_ZPmZ_H: |
| 7231 | case AArch64::FMAXNM_ZPmZ_S: |
| 7232 | case AArch64::FMAX_ZPmZ_D: |
| 7233 | case AArch64::FMAX_ZPmZ_H: |
| 7234 | case AArch64::FMAX_ZPmZ_S: |
| 7235 | case AArch64::FMINNM_ZPmZ_D: |
| 7236 | case AArch64::FMINNM_ZPmZ_H: |
| 7237 | case AArch64::FMINNM_ZPmZ_S: |
| 7238 | case AArch64::FMIN_ZPmZ_D: |
| 7239 | case AArch64::FMIN_ZPmZ_H: |
| 7240 | case AArch64::FMIN_ZPmZ_S: |
| 7241 | case AArch64::FMULX_ZPmZ_D: |
| 7242 | case AArch64::FMULX_ZPmZ_H: |
| 7243 | case AArch64::FMULX_ZPmZ_S: |
| 7244 | case AArch64::FMUL_ZPmZ_D: |
| 7245 | case AArch64::FMUL_ZPmZ_H: |
| 7246 | case AArch64::FMUL_ZPmZ_S: |
| 7247 | case AArch64::FSCALE_ZPmZ_D: |
| 7248 | case AArch64::FSCALE_ZPmZ_H: |
| 7249 | case AArch64::FSCALE_ZPmZ_S: |
| 7250 | case AArch64::FSUBR_ZPmZ_D: |
| 7251 | case AArch64::FSUBR_ZPmZ_H: |
| 7252 | case AArch64::FSUBR_ZPmZ_S: |
| 7253 | case AArch64::FSUB_ZPmZ_D: |
| 7254 | case AArch64::FSUB_ZPmZ_H: |
| 7255 | case AArch64::FSUB_ZPmZ_S: |
| 7256 | case AArch64::LSLR_ZPmZ_B: |
| 7257 | case AArch64::LSLR_ZPmZ_D: |
| 7258 | case AArch64::LSLR_ZPmZ_H: |
| 7259 | case AArch64::LSLR_ZPmZ_S: |
| 7260 | case AArch64::LSL_WIDE_ZPmZ_B: |
| 7261 | case AArch64::LSL_WIDE_ZPmZ_H: |
| 7262 | case AArch64::LSL_WIDE_ZPmZ_S: |
| 7263 | case AArch64::LSL_ZPmZ_B: |
| 7264 | case AArch64::LSL_ZPmZ_D: |
| 7265 | case AArch64::LSL_ZPmZ_H: |
| 7266 | case AArch64::LSL_ZPmZ_S: |
| 7267 | case AArch64::LSRR_ZPmZ_B: |
| 7268 | case AArch64::LSRR_ZPmZ_D: |
| 7269 | case AArch64::LSRR_ZPmZ_H: |
| 7270 | case AArch64::LSRR_ZPmZ_S: |
| 7271 | case AArch64::LSR_WIDE_ZPmZ_B: |
| 7272 | case AArch64::LSR_WIDE_ZPmZ_H: |
| 7273 | case AArch64::LSR_WIDE_ZPmZ_S: |
| 7274 | case AArch64::LSR_ZPmZ_B: |
| 7275 | case AArch64::LSR_ZPmZ_D: |
| 7276 | case AArch64::LSR_ZPmZ_H: |
| 7277 | case AArch64::LSR_ZPmZ_S: |
| 7278 | case AArch64::MUL_ZPmZ_B: |
| 7279 | case AArch64::MUL_ZPmZ_D: |
| 7280 | case AArch64::MUL_ZPmZ_H: |
| 7281 | case AArch64::MUL_ZPmZ_S: |
| 7282 | case AArch64::ORR_ZPmZ_B: |
| 7283 | case AArch64::ORR_ZPmZ_D: |
| 7284 | case AArch64::ORR_ZPmZ_H: |
| 7285 | case AArch64::ORR_ZPmZ_S: |
| 7286 | case AArch64::SABD_ZPmZ_B: |
| 7287 | case AArch64::SABD_ZPmZ_D: |
| 7288 | case AArch64::SABD_ZPmZ_H: |
| 7289 | case AArch64::SABD_ZPmZ_S: |
| 7290 | case AArch64::SDIVR_ZPmZ_D: |
| 7291 | case AArch64::SDIVR_ZPmZ_S: |
| 7292 | case AArch64::SDIV_ZPmZ_D: |
| 7293 | case AArch64::SDIV_ZPmZ_S: |
| 7294 | case AArch64::SMAX_ZPmZ_B: |
| 7295 | case AArch64::SMAX_ZPmZ_D: |
| 7296 | case AArch64::SMAX_ZPmZ_H: |
| 7297 | case AArch64::SMAX_ZPmZ_S: |
| 7298 | case AArch64::SMIN_ZPmZ_B: |
| 7299 | case AArch64::SMIN_ZPmZ_D: |
| 7300 | case AArch64::SMIN_ZPmZ_H: |
| 7301 | case AArch64::SMIN_ZPmZ_S: |
| 7302 | case AArch64::SMULH_ZPmZ_B: |
| 7303 | case AArch64::SMULH_ZPmZ_D: |
| 7304 | case AArch64::SMULH_ZPmZ_H: |
| 7305 | case AArch64::SMULH_ZPmZ_S: |
| 7306 | case AArch64::SPLICE_ZPZ_B: |
| 7307 | case AArch64::SPLICE_ZPZ_D: |
| 7308 | case AArch64::SPLICE_ZPZ_H: |
| 7309 | case AArch64::SPLICE_ZPZ_S: |
| 7310 | case AArch64::SUBR_ZPmZ_B: |
| 7311 | case AArch64::SUBR_ZPmZ_D: |
| 7312 | case AArch64::SUBR_ZPmZ_H: |
| 7313 | case AArch64::SUBR_ZPmZ_S: |
| 7314 | case AArch64::SUB_ZPmZ_B: |
| 7315 | case AArch64::SUB_ZPmZ_D: |
| 7316 | case AArch64::SUB_ZPmZ_H: |
| 7317 | case AArch64::SUB_ZPmZ_S: |
| 7318 | case AArch64::UABD_ZPmZ_B: |
| 7319 | case AArch64::UABD_ZPmZ_D: |
| 7320 | case AArch64::UABD_ZPmZ_H: |
| 7321 | case AArch64::UABD_ZPmZ_S: |
| 7322 | case AArch64::UDIVR_ZPmZ_D: |
| 7323 | case AArch64::UDIVR_ZPmZ_S: |
| 7324 | case AArch64::UDIV_ZPmZ_D: |
| 7325 | case AArch64::UDIV_ZPmZ_S: |
| 7326 | case AArch64::UMAX_ZPmZ_B: |
| 7327 | case AArch64::UMAX_ZPmZ_D: |
| 7328 | case AArch64::UMAX_ZPmZ_H: |
| 7329 | case AArch64::UMAX_ZPmZ_S: |
| 7330 | case AArch64::UMIN_ZPmZ_B: |
| 7331 | case AArch64::UMIN_ZPmZ_D: |
| 7332 | case AArch64::UMIN_ZPmZ_H: |
| 7333 | case AArch64::UMIN_ZPmZ_S: |
| 7334 | case AArch64::UMULH_ZPmZ_B: |
| 7335 | case AArch64::UMULH_ZPmZ_D: |
| 7336 | case AArch64::UMULH_ZPmZ_H: |
| 7337 | case AArch64::UMULH_ZPmZ_S: { |
| 7338 | // op: Pg |
| 7339 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7340 | op &= UINT64_C(7); |
| 7341 | op <<= 10; |
| 7342 | Value |= op; |
| 7343 | // op: Zdn |
| 7344 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7345 | op &= UINT64_C(31); |
| 7346 | Value |= op; |
| 7347 | // op: Zm |
| 7348 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7349 | op &= UINT64_C(31); |
| 7350 | op <<= 5; |
| 7351 | Value |= op; |
| 7352 | break; |
| 7353 | } |
| 7354 | case AArch64::FADD_ZPmI_D: |
| 7355 | case AArch64::FADD_ZPmI_H: |
| 7356 | case AArch64::FADD_ZPmI_S: |
| 7357 | case AArch64::FMAXNM_ZPmI_D: |
| 7358 | case AArch64::FMAXNM_ZPmI_H: |
| 7359 | case AArch64::FMAXNM_ZPmI_S: |
| 7360 | case AArch64::FMAX_ZPmI_D: |
| 7361 | case AArch64::FMAX_ZPmI_H: |
| 7362 | case AArch64::FMAX_ZPmI_S: |
| 7363 | case AArch64::FMINNM_ZPmI_D: |
| 7364 | case AArch64::FMINNM_ZPmI_H: |
| 7365 | case AArch64::FMINNM_ZPmI_S: |
| 7366 | case AArch64::FMIN_ZPmI_D: |
| 7367 | case AArch64::FMIN_ZPmI_H: |
| 7368 | case AArch64::FMIN_ZPmI_S: |
| 7369 | case AArch64::FMUL_ZPmI_D: |
| 7370 | case AArch64::FMUL_ZPmI_H: |
| 7371 | case AArch64::FMUL_ZPmI_S: |
| 7372 | case AArch64::FSUBR_ZPmI_D: |
| 7373 | case AArch64::FSUBR_ZPmI_H: |
| 7374 | case AArch64::FSUBR_ZPmI_S: |
| 7375 | case AArch64::FSUB_ZPmI_D: |
| 7376 | case AArch64::FSUB_ZPmI_H: |
| 7377 | case AArch64::FSUB_ZPmI_S: { |
| 7378 | // op: Pg |
| 7379 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7380 | op &= UINT64_C(7); |
| 7381 | op <<= 10; |
| 7382 | Value |= op; |
| 7383 | // op: Zdn |
| 7384 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7385 | op &= UINT64_C(31); |
| 7386 | Value |= op; |
| 7387 | // op: i1 |
| 7388 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7389 | op &= UINT64_C(1); |
| 7390 | op <<= 5; |
| 7391 | Value |= op; |
| 7392 | break; |
| 7393 | } |
| 7394 | case AArch64::LSL_ZPmI_H: |
| 7395 | case AArch64::SQSHLU_ZPmI_H: |
| 7396 | case AArch64::SQSHL_ZPmI_H: |
| 7397 | case AArch64::UQSHL_ZPmI_H: { |
| 7398 | // op: Pg |
| 7399 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7400 | op &= UINT64_C(7); |
| 7401 | op <<= 10; |
| 7402 | Value |= op; |
| 7403 | // op: Zdn |
| 7404 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7405 | op &= UINT64_C(31); |
| 7406 | Value |= op; |
| 7407 | // op: imm |
| 7408 | op = getVecShiftL16OpValue(MI, 3, Fixups, STI); |
| 7409 | op &= UINT64_C(15); |
| 7410 | op <<= 5; |
| 7411 | Value |= op; |
| 7412 | break; |
| 7413 | } |
| 7414 | case AArch64::LSL_ZPmI_S: |
| 7415 | case AArch64::SQSHLU_ZPmI_S: |
| 7416 | case AArch64::SQSHL_ZPmI_S: |
| 7417 | case AArch64::UQSHL_ZPmI_S: { |
| 7418 | // op: Pg |
| 7419 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7420 | op &= UINT64_C(7); |
| 7421 | op <<= 10; |
| 7422 | Value |= op; |
| 7423 | // op: Zdn |
| 7424 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7425 | op &= UINT64_C(31); |
| 7426 | Value |= op; |
| 7427 | // op: imm |
| 7428 | op = getVecShiftL32OpValue(MI, 3, Fixups, STI); |
| 7429 | op &= UINT64_C(31); |
| 7430 | op <<= 5; |
| 7431 | Value |= op; |
| 7432 | break; |
| 7433 | } |
| 7434 | case AArch64::LSL_ZPmI_D: |
| 7435 | case AArch64::SQSHLU_ZPmI_D: |
| 7436 | case AArch64::SQSHL_ZPmI_D: |
| 7437 | case AArch64::UQSHL_ZPmI_D: { |
| 7438 | // op: Pg |
| 7439 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7440 | op &= UINT64_C(7); |
| 7441 | op <<= 10; |
| 7442 | Value |= op; |
| 7443 | // op: Zdn |
| 7444 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7445 | op &= UINT64_C(31); |
| 7446 | Value |= op; |
| 7447 | // op: imm |
| 7448 | op = getVecShiftL64OpValue(MI, 3, Fixups, STI); |
| 7449 | Value |= (op & UINT64_C(32)) << 17; |
| 7450 | Value |= (op & UINT64_C(31)) << 5; |
| 7451 | break; |
| 7452 | } |
| 7453 | case AArch64::LSL_ZPmI_B: |
| 7454 | case AArch64::SQSHLU_ZPmI_B: |
| 7455 | case AArch64::SQSHL_ZPmI_B: |
| 7456 | case AArch64::UQSHL_ZPmI_B: { |
| 7457 | // op: Pg |
| 7458 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7459 | op &= UINT64_C(7); |
| 7460 | op <<= 10; |
| 7461 | Value |= op; |
| 7462 | // op: Zdn |
| 7463 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7464 | op &= UINT64_C(31); |
| 7465 | Value |= op; |
| 7466 | // op: imm |
| 7467 | op = getVecShiftL8OpValue(MI, 3, Fixups, STI); |
| 7468 | op &= UINT64_C(7); |
| 7469 | op <<= 5; |
| 7470 | Value |= op; |
| 7471 | break; |
| 7472 | } |
| 7473 | case AArch64::ASRD_ZPmI_H: |
| 7474 | case AArch64::ASR_ZPmI_H: |
| 7475 | case AArch64::LSR_ZPmI_H: |
| 7476 | case AArch64::SRSHR_ZPmI_H: |
| 7477 | case AArch64::URSHR_ZPmI_H: { |
| 7478 | // op: Pg |
| 7479 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7480 | op &= UINT64_C(7); |
| 7481 | op <<= 10; |
| 7482 | Value |= op; |
| 7483 | // op: Zdn |
| 7484 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7485 | op &= UINT64_C(31); |
| 7486 | Value |= op; |
| 7487 | // op: imm |
| 7488 | op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| 7489 | op &= UINT64_C(15); |
| 7490 | op <<= 5; |
| 7491 | Value |= op; |
| 7492 | break; |
| 7493 | } |
| 7494 | case AArch64::ASRD_ZPmI_S: |
| 7495 | case AArch64::ASR_ZPmI_S: |
| 7496 | case AArch64::LSR_ZPmI_S: |
| 7497 | case AArch64::SRSHR_ZPmI_S: |
| 7498 | case AArch64::URSHR_ZPmI_S: { |
| 7499 | // op: Pg |
| 7500 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7501 | op &= UINT64_C(7); |
| 7502 | op <<= 10; |
| 7503 | Value |= op; |
| 7504 | // op: Zdn |
| 7505 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7506 | op &= UINT64_C(31); |
| 7507 | Value |= op; |
| 7508 | // op: imm |
| 7509 | op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| 7510 | op &= UINT64_C(31); |
| 7511 | op <<= 5; |
| 7512 | Value |= op; |
| 7513 | break; |
| 7514 | } |
| 7515 | case AArch64::ASRD_ZPmI_D: |
| 7516 | case AArch64::ASR_ZPmI_D: |
| 7517 | case AArch64::LSR_ZPmI_D: |
| 7518 | case AArch64::SRSHR_ZPmI_D: |
| 7519 | case AArch64::URSHR_ZPmI_D: { |
| 7520 | // op: Pg |
| 7521 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7522 | op &= UINT64_C(7); |
| 7523 | op <<= 10; |
| 7524 | Value |= op; |
| 7525 | // op: Zdn |
| 7526 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7527 | op &= UINT64_C(31); |
| 7528 | Value |= op; |
| 7529 | // op: imm |
| 7530 | op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| 7531 | Value |= (op & UINT64_C(32)) << 17; |
| 7532 | Value |= (op & UINT64_C(31)) << 5; |
| 7533 | break; |
| 7534 | } |
| 7535 | case AArch64::ASRD_ZPmI_B: |
| 7536 | case AArch64::ASR_ZPmI_B: |
| 7537 | case AArch64::LSR_ZPmI_B: |
| 7538 | case AArch64::SRSHR_ZPmI_B: |
| 7539 | case AArch64::URSHR_ZPmI_B: { |
| 7540 | // op: Pg |
| 7541 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7542 | op &= UINT64_C(7); |
| 7543 | op <<= 10; |
| 7544 | Value |= op; |
| 7545 | // op: Zdn |
| 7546 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7547 | op &= UINT64_C(31); |
| 7548 | Value |= op; |
| 7549 | // op: imm |
| 7550 | op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| 7551 | op &= UINT64_C(7); |
| 7552 | op <<= 5; |
| 7553 | Value |= op; |
| 7554 | break; |
| 7555 | } |
| 7556 | case AArch64::ADDP_ZPmZ_B: |
| 7557 | case AArch64::ADDP_ZPmZ_D: |
| 7558 | case AArch64::ADDP_ZPmZ_H: |
| 7559 | case AArch64::ADDP_ZPmZ_S: |
| 7560 | case AArch64::FADDP_ZPmZZ_D: |
| 7561 | case AArch64::FADDP_ZPmZZ_H: |
| 7562 | case AArch64::FADDP_ZPmZZ_S: |
| 7563 | case AArch64::FMAXNMP_ZPmZZ_D: |
| 7564 | case AArch64::FMAXNMP_ZPmZZ_H: |
| 7565 | case AArch64::FMAXNMP_ZPmZZ_S: |
| 7566 | case AArch64::FMAXP_ZPmZZ_D: |
| 7567 | case AArch64::FMAXP_ZPmZZ_H: |
| 7568 | case AArch64::FMAXP_ZPmZZ_S: |
| 7569 | case AArch64::FMINNMP_ZPmZZ_D: |
| 7570 | case AArch64::FMINNMP_ZPmZZ_H: |
| 7571 | case AArch64::FMINNMP_ZPmZZ_S: |
| 7572 | case AArch64::FMINP_ZPmZZ_D: |
| 7573 | case AArch64::FMINP_ZPmZZ_H: |
| 7574 | case AArch64::FMINP_ZPmZZ_S: |
| 7575 | case AArch64::SHADD_ZPmZ_B: |
| 7576 | case AArch64::SHADD_ZPmZ_D: |
| 7577 | case AArch64::SHADD_ZPmZ_H: |
| 7578 | case AArch64::SHADD_ZPmZ_S: |
| 7579 | case AArch64::SHSUBR_ZPmZ_B: |
| 7580 | case AArch64::SHSUBR_ZPmZ_D: |
| 7581 | case AArch64::SHSUBR_ZPmZ_H: |
| 7582 | case AArch64::SHSUBR_ZPmZ_S: |
| 7583 | case AArch64::SHSUB_ZPmZ_B: |
| 7584 | case AArch64::SHSUB_ZPmZ_D: |
| 7585 | case AArch64::SHSUB_ZPmZ_H: |
| 7586 | case AArch64::SHSUB_ZPmZ_S: |
| 7587 | case AArch64::SMAXP_ZPmZ_B: |
| 7588 | case AArch64::SMAXP_ZPmZ_D: |
| 7589 | case AArch64::SMAXP_ZPmZ_H: |
| 7590 | case AArch64::SMAXP_ZPmZ_S: |
| 7591 | case AArch64::SMINP_ZPmZ_B: |
| 7592 | case AArch64::SMINP_ZPmZ_D: |
| 7593 | case AArch64::SMINP_ZPmZ_H: |
| 7594 | case AArch64::SMINP_ZPmZ_S: |
| 7595 | case AArch64::SQADD_ZPmZ_B: |
| 7596 | case AArch64::SQADD_ZPmZ_D: |
| 7597 | case AArch64::SQADD_ZPmZ_H: |
| 7598 | case AArch64::SQADD_ZPmZ_S: |
| 7599 | case AArch64::SQRSHLR_ZPmZ_B: |
| 7600 | case AArch64::SQRSHLR_ZPmZ_D: |
| 7601 | case AArch64::SQRSHLR_ZPmZ_H: |
| 7602 | case AArch64::SQRSHLR_ZPmZ_S: |
| 7603 | case AArch64::SQRSHL_ZPmZ_B: |
| 7604 | case AArch64::SQRSHL_ZPmZ_D: |
| 7605 | case AArch64::SQRSHL_ZPmZ_H: |
| 7606 | case AArch64::SQRSHL_ZPmZ_S: |
| 7607 | case AArch64::SQSHLR_ZPmZ_B: |
| 7608 | case AArch64::SQSHLR_ZPmZ_D: |
| 7609 | case AArch64::SQSHLR_ZPmZ_H: |
| 7610 | case AArch64::SQSHLR_ZPmZ_S: |
| 7611 | case AArch64::SQSHL_ZPmZ_B: |
| 7612 | case AArch64::SQSHL_ZPmZ_D: |
| 7613 | case AArch64::SQSHL_ZPmZ_H: |
| 7614 | case AArch64::SQSHL_ZPmZ_S: |
| 7615 | case AArch64::SQSUBR_ZPmZ_B: |
| 7616 | case AArch64::SQSUBR_ZPmZ_D: |
| 7617 | case AArch64::SQSUBR_ZPmZ_H: |
| 7618 | case AArch64::SQSUBR_ZPmZ_S: |
| 7619 | case AArch64::SQSUB_ZPmZ_B: |
| 7620 | case AArch64::SQSUB_ZPmZ_D: |
| 7621 | case AArch64::SQSUB_ZPmZ_H: |
| 7622 | case AArch64::SQSUB_ZPmZ_S: |
| 7623 | case AArch64::SRHADD_ZPmZ_B: |
| 7624 | case AArch64::SRHADD_ZPmZ_D: |
| 7625 | case AArch64::SRHADD_ZPmZ_H: |
| 7626 | case AArch64::SRHADD_ZPmZ_S: |
| 7627 | case AArch64::SRSHLR_ZPmZ_B: |
| 7628 | case AArch64::SRSHLR_ZPmZ_D: |
| 7629 | case AArch64::SRSHLR_ZPmZ_H: |
| 7630 | case AArch64::SRSHLR_ZPmZ_S: |
| 7631 | case AArch64::SRSHL_ZPmZ_B: |
| 7632 | case AArch64::SRSHL_ZPmZ_D: |
| 7633 | case AArch64::SRSHL_ZPmZ_H: |
| 7634 | case AArch64::SRSHL_ZPmZ_S: |
| 7635 | case AArch64::SUQADD_ZPmZ_B: |
| 7636 | case AArch64::SUQADD_ZPmZ_D: |
| 7637 | case AArch64::SUQADD_ZPmZ_H: |
| 7638 | case AArch64::SUQADD_ZPmZ_S: |
| 7639 | case AArch64::UHADD_ZPmZ_B: |
| 7640 | case AArch64::UHADD_ZPmZ_D: |
| 7641 | case AArch64::UHADD_ZPmZ_H: |
| 7642 | case AArch64::UHADD_ZPmZ_S: |
| 7643 | case AArch64::UHSUBR_ZPmZ_B: |
| 7644 | case AArch64::UHSUBR_ZPmZ_D: |
| 7645 | case AArch64::UHSUBR_ZPmZ_H: |
| 7646 | case AArch64::UHSUBR_ZPmZ_S: |
| 7647 | case AArch64::UHSUB_ZPmZ_B: |
| 7648 | case AArch64::UHSUB_ZPmZ_D: |
| 7649 | case AArch64::UHSUB_ZPmZ_H: |
| 7650 | case AArch64::UHSUB_ZPmZ_S: |
| 7651 | case AArch64::UMAXP_ZPmZ_B: |
| 7652 | case AArch64::UMAXP_ZPmZ_D: |
| 7653 | case AArch64::UMAXP_ZPmZ_H: |
| 7654 | case AArch64::UMAXP_ZPmZ_S: |
| 7655 | case AArch64::UMINP_ZPmZ_B: |
| 7656 | case AArch64::UMINP_ZPmZ_D: |
| 7657 | case AArch64::UMINP_ZPmZ_H: |
| 7658 | case AArch64::UMINP_ZPmZ_S: |
| 7659 | case AArch64::UQADD_ZPmZ_B: |
| 7660 | case AArch64::UQADD_ZPmZ_D: |
| 7661 | case AArch64::UQADD_ZPmZ_H: |
| 7662 | case AArch64::UQADD_ZPmZ_S: |
| 7663 | case AArch64::UQRSHLR_ZPmZ_B: |
| 7664 | case AArch64::UQRSHLR_ZPmZ_D: |
| 7665 | case AArch64::UQRSHLR_ZPmZ_H: |
| 7666 | case AArch64::UQRSHLR_ZPmZ_S: |
| 7667 | case AArch64::UQRSHL_ZPmZ_B: |
| 7668 | case AArch64::UQRSHL_ZPmZ_D: |
| 7669 | case AArch64::UQRSHL_ZPmZ_H: |
| 7670 | case AArch64::UQRSHL_ZPmZ_S: |
| 7671 | case AArch64::UQSHLR_ZPmZ_B: |
| 7672 | case AArch64::UQSHLR_ZPmZ_D: |
| 7673 | case AArch64::UQSHLR_ZPmZ_H: |
| 7674 | case AArch64::UQSHLR_ZPmZ_S: |
| 7675 | case AArch64::UQSHL_ZPmZ_B: |
| 7676 | case AArch64::UQSHL_ZPmZ_D: |
| 7677 | case AArch64::UQSHL_ZPmZ_H: |
| 7678 | case AArch64::UQSHL_ZPmZ_S: |
| 7679 | case AArch64::UQSUBR_ZPmZ_B: |
| 7680 | case AArch64::UQSUBR_ZPmZ_D: |
| 7681 | case AArch64::UQSUBR_ZPmZ_H: |
| 7682 | case AArch64::UQSUBR_ZPmZ_S: |
| 7683 | case AArch64::UQSUB_ZPmZ_B: |
| 7684 | case AArch64::UQSUB_ZPmZ_D: |
| 7685 | case AArch64::UQSUB_ZPmZ_H: |
| 7686 | case AArch64::UQSUB_ZPmZ_S: |
| 7687 | case AArch64::URHADD_ZPmZ_B: |
| 7688 | case AArch64::URHADD_ZPmZ_D: |
| 7689 | case AArch64::URHADD_ZPmZ_H: |
| 7690 | case AArch64::URHADD_ZPmZ_S: |
| 7691 | case AArch64::URSHLR_ZPmZ_B: |
| 7692 | case AArch64::URSHLR_ZPmZ_D: |
| 7693 | case AArch64::URSHLR_ZPmZ_H: |
| 7694 | case AArch64::URSHLR_ZPmZ_S: |
| 7695 | case AArch64::URSHL_ZPmZ_B: |
| 7696 | case AArch64::URSHL_ZPmZ_D: |
| 7697 | case AArch64::URSHL_ZPmZ_H: |
| 7698 | case AArch64::URSHL_ZPmZ_S: |
| 7699 | case AArch64::USQADD_ZPmZ_B: |
| 7700 | case AArch64::USQADD_ZPmZ_D: |
| 7701 | case AArch64::USQADD_ZPmZ_H: |
| 7702 | case AArch64::USQADD_ZPmZ_S: { |
| 7703 | // op: Pg |
| 7704 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7705 | op &= UINT64_C(7); |
| 7706 | op <<= 10; |
| 7707 | Value |= op; |
| 7708 | // op: Zm |
| 7709 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7710 | op &= UINT64_C(31); |
| 7711 | op <<= 5; |
| 7712 | Value |= op; |
| 7713 | // op: Zdn |
| 7714 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7715 | op &= UINT64_C(31); |
| 7716 | Value |= op; |
| 7717 | break; |
| 7718 | } |
| 7719 | case AArch64::SPLICE_ZPZZ_B: |
| 7720 | case AArch64::SPLICE_ZPZZ_D: |
| 7721 | case AArch64::SPLICE_ZPZZ_H: |
| 7722 | case AArch64::SPLICE_ZPZZ_S: { |
| 7723 | // op: Pg |
| 7724 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7725 | op &= UINT64_C(7); |
| 7726 | op <<= 10; |
| 7727 | Value |= op; |
| 7728 | // op: Zn |
| 7729 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7730 | op &= UINT64_C(31); |
| 7731 | op <<= 5; |
| 7732 | Value |= op; |
| 7733 | // op: Zd |
| 7734 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7735 | op &= UINT64_C(31); |
| 7736 | Value |= op; |
| 7737 | break; |
| 7738 | } |
| 7739 | case AArch64::GLD1B_D_IMM_REAL: |
| 7740 | case AArch64::GLD1B_S_IMM_REAL: |
| 7741 | case AArch64::GLD1D_IMM_REAL: |
| 7742 | case AArch64::GLD1H_D_IMM_REAL: |
| 7743 | case AArch64::GLD1H_S_IMM_REAL: |
| 7744 | case AArch64::GLD1SB_D_IMM_REAL: |
| 7745 | case AArch64::GLD1SB_S_IMM_REAL: |
| 7746 | case AArch64::GLD1SH_D_IMM_REAL: |
| 7747 | case AArch64::GLD1SH_S_IMM_REAL: |
| 7748 | case AArch64::GLD1SW_D_IMM_REAL: |
| 7749 | case AArch64::GLD1W_D_IMM_REAL: |
| 7750 | case AArch64::GLD1W_IMM_REAL: |
| 7751 | case AArch64::GLDFF1B_D_IMM_REAL: |
| 7752 | case AArch64::GLDFF1B_S_IMM_REAL: |
| 7753 | case AArch64::GLDFF1D_IMM_REAL: |
| 7754 | case AArch64::GLDFF1H_D_IMM_REAL: |
| 7755 | case AArch64::GLDFF1H_S_IMM_REAL: |
| 7756 | case AArch64::GLDFF1SB_D_IMM_REAL: |
| 7757 | case AArch64::GLDFF1SB_S_IMM_REAL: |
| 7758 | case AArch64::GLDFF1SH_D_IMM_REAL: |
| 7759 | case AArch64::GLDFF1SH_S_IMM_REAL: |
| 7760 | case AArch64::GLDFF1SW_D_IMM_REAL: |
| 7761 | case AArch64::GLDFF1W_D_IMM_REAL: |
| 7762 | case AArch64::GLDFF1W_IMM_REAL: { |
| 7763 | // op: Pg |
| 7764 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7765 | op &= UINT64_C(7); |
| 7766 | op <<= 10; |
| 7767 | Value |= op; |
| 7768 | // op: Zn |
| 7769 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7770 | op &= UINT64_C(31); |
| 7771 | op <<= 5; |
| 7772 | Value |= op; |
| 7773 | // op: Zt |
| 7774 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7775 | op &= UINT64_C(31); |
| 7776 | Value |= op; |
| 7777 | // op: imm5 |
| 7778 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7779 | op &= UINT64_C(31); |
| 7780 | op <<= 16; |
| 7781 | Value |= op; |
| 7782 | break; |
| 7783 | } |
| 7784 | case AArch64::PRFB_D_PZI: |
| 7785 | case AArch64::PRFB_S_PZI: |
| 7786 | case AArch64::PRFD_D_PZI: |
| 7787 | case AArch64::PRFD_S_PZI: |
| 7788 | case AArch64::PRFH_D_PZI: |
| 7789 | case AArch64::PRFH_S_PZI: |
| 7790 | case AArch64::PRFW_D_PZI: |
| 7791 | case AArch64::PRFW_S_PZI: { |
| 7792 | // op: Pg |
| 7793 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7794 | op &= UINT64_C(7); |
| 7795 | op <<= 10; |
| 7796 | Value |= op; |
| 7797 | // op: Zn |
| 7798 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7799 | op &= UINT64_C(31); |
| 7800 | op <<= 5; |
| 7801 | Value |= op; |
| 7802 | // op: imm5 |
| 7803 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7804 | op &= UINT64_C(31); |
| 7805 | op <<= 16; |
| 7806 | Value |= op; |
| 7807 | // op: prfop |
| 7808 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7809 | op &= UINT64_C(15); |
| 7810 | Value |= op; |
| 7811 | break; |
| 7812 | } |
| 7813 | case AArch64::SADALP_ZPmZ_D: |
| 7814 | case AArch64::SADALP_ZPmZ_H: |
| 7815 | case AArch64::SADALP_ZPmZ_S: |
| 7816 | case AArch64::UADALP_ZPmZ_D: |
| 7817 | case AArch64::UADALP_ZPmZ_H: |
| 7818 | case AArch64::UADALP_ZPmZ_S: { |
| 7819 | // op: Pg |
| 7820 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7821 | op &= UINT64_C(7); |
| 7822 | op <<= 10; |
| 7823 | Value |= op; |
| 7824 | // op: Zn |
| 7825 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7826 | op &= UINT64_C(31); |
| 7827 | op <<= 5; |
| 7828 | Value |= op; |
| 7829 | // op: Zda |
| 7830 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7831 | op &= UINT64_C(31); |
| 7832 | Value |= op; |
| 7833 | break; |
| 7834 | } |
| 7835 | case AArch64::SST1B_D_IMM: |
| 7836 | case AArch64::SST1B_S_IMM: |
| 7837 | case AArch64::SST1D_IMM: |
| 7838 | case AArch64::SST1H_D_IMM: |
| 7839 | case AArch64::SST1H_S_IMM: |
| 7840 | case AArch64::SST1W_D_IMM: |
| 7841 | case AArch64::SST1W_IMM: { |
| 7842 | // op: Pg |
| 7843 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 7844 | op &= UINT64_C(7); |
| 7845 | op <<= 10; |
| 7846 | Value |= op; |
| 7847 | // op: imm5 |
| 7848 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7849 | op &= UINT64_C(31); |
| 7850 | op <<= 16; |
| 7851 | Value |= op; |
| 7852 | // op: Zn |
| 7853 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7854 | op &= UINT64_C(31); |
| 7855 | op <<= 5; |
| 7856 | Value |= op; |
| 7857 | // op: Zt |
| 7858 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7859 | op &= UINT64_C(31); |
| 7860 | Value |= op; |
| 7861 | break; |
| 7862 | } |
| 7863 | case AArch64::FCPY_ZPmI_D: |
| 7864 | case AArch64::FCPY_ZPmI_H: |
| 7865 | case AArch64::FCPY_ZPmI_S: { |
| 7866 | // op: Pg |
| 7867 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7868 | op &= UINT64_C(15); |
| 7869 | op <<= 16; |
| 7870 | Value |= op; |
| 7871 | // op: Zd |
| 7872 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7873 | op &= UINT64_C(31); |
| 7874 | Value |= op; |
| 7875 | // op: imm8 |
| 7876 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7877 | op &= UINT64_C(255); |
| 7878 | op <<= 5; |
| 7879 | Value |= op; |
| 7880 | break; |
| 7881 | } |
| 7882 | case AArch64::CPY_ZPmR_B: |
| 7883 | case AArch64::CPY_ZPmR_D: |
| 7884 | case AArch64::CPY_ZPmR_H: |
| 7885 | case AArch64::CPY_ZPmR_S: { |
| 7886 | // op: Pg |
| 7887 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7888 | op &= UINT64_C(7); |
| 7889 | op <<= 10; |
| 7890 | Value |= op; |
| 7891 | // op: Rn |
| 7892 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7893 | op &= UINT64_C(31); |
| 7894 | op <<= 5; |
| 7895 | Value |= op; |
| 7896 | // op: Zd |
| 7897 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7898 | op &= UINT64_C(31); |
| 7899 | Value |= op; |
| 7900 | break; |
| 7901 | } |
| 7902 | case AArch64::CPY_ZPmV_B: |
| 7903 | case AArch64::CPY_ZPmV_D: |
| 7904 | case AArch64::CPY_ZPmV_H: |
| 7905 | case AArch64::CPY_ZPmV_S: { |
| 7906 | // op: Pg |
| 7907 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 7908 | op &= UINT64_C(7); |
| 7909 | op <<= 10; |
| 7910 | Value |= op; |
| 7911 | // op: Vn |
| 7912 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 7913 | op &= UINT64_C(31); |
| 7914 | op <<= 5; |
| 7915 | Value |= op; |
| 7916 | // op: Zd |
| 7917 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 7918 | op &= UINT64_C(31); |
| 7919 | Value |= op; |
| 7920 | break; |
| 7921 | } |
| 7922 | case AArch64::ABS_ZPmZ_B: |
| 7923 | case AArch64::ABS_ZPmZ_D: |
| 7924 | case AArch64::ABS_ZPmZ_H: |
| 7925 | case AArch64::ABS_ZPmZ_S: |
| 7926 | case AArch64::CLS_ZPmZ_B: |
| 7927 | case AArch64::CLS_ZPmZ_D: |
| 7928 | case AArch64::CLS_ZPmZ_H: |
| 7929 | case AArch64::CLS_ZPmZ_S: |
| 7930 | case AArch64::CLZ_ZPmZ_B: |
| 7931 | case AArch64::CLZ_ZPmZ_D: |
| 7932 | case AArch64::CLZ_ZPmZ_H: |
| 7933 | case AArch64::CLZ_ZPmZ_S: |
| 7934 | case AArch64::CNOT_ZPmZ_B: |
| 7935 | case AArch64::CNOT_ZPmZ_D: |
| 7936 | case AArch64::CNOT_ZPmZ_H: |
| 7937 | case AArch64::CNOT_ZPmZ_S: |
| 7938 | case AArch64::CNT_ZPmZ_B: |
| 7939 | case AArch64::CNT_ZPmZ_D: |
| 7940 | case AArch64::CNT_ZPmZ_H: |
| 7941 | case AArch64::CNT_ZPmZ_S: |
| 7942 | case AArch64::FABS_ZPmZ_D: |
| 7943 | case AArch64::FABS_ZPmZ_H: |
| 7944 | case AArch64::FABS_ZPmZ_S: |
| 7945 | case AArch64::FCVTX_ZPmZ_DtoS: |
| 7946 | case AArch64::FCVTZS_ZPmZ_DtoD: |
| 7947 | case AArch64::FCVTZS_ZPmZ_DtoS: |
| 7948 | case AArch64::FCVTZS_ZPmZ_HtoD: |
| 7949 | case AArch64::FCVTZS_ZPmZ_HtoH: |
| 7950 | case AArch64::FCVTZS_ZPmZ_HtoS: |
| 7951 | case AArch64::FCVTZS_ZPmZ_StoD: |
| 7952 | case AArch64::FCVTZS_ZPmZ_StoS: |
| 7953 | case AArch64::FCVTZU_ZPmZ_DtoD: |
| 7954 | case AArch64::FCVTZU_ZPmZ_DtoS: |
| 7955 | case AArch64::FCVTZU_ZPmZ_HtoD: |
| 7956 | case AArch64::FCVTZU_ZPmZ_HtoH: |
| 7957 | case AArch64::FCVTZU_ZPmZ_HtoS: |
| 7958 | case AArch64::FCVTZU_ZPmZ_StoD: |
| 7959 | case AArch64::FCVTZU_ZPmZ_StoS: |
| 7960 | case AArch64::FCVT_ZPmZ_DtoH: |
| 7961 | case AArch64::FCVT_ZPmZ_DtoS: |
| 7962 | case AArch64::FCVT_ZPmZ_HtoD: |
| 7963 | case AArch64::FCVT_ZPmZ_HtoS: |
| 7964 | case AArch64::FCVT_ZPmZ_StoD: |
| 7965 | case AArch64::FCVT_ZPmZ_StoH: |
| 7966 | case AArch64::FLOGB_ZPmZ_D: |
| 7967 | case AArch64::FLOGB_ZPmZ_H: |
| 7968 | case AArch64::FLOGB_ZPmZ_S: |
| 7969 | case AArch64::FNEG_ZPmZ_D: |
| 7970 | case AArch64::FNEG_ZPmZ_H: |
| 7971 | case AArch64::FNEG_ZPmZ_S: |
| 7972 | case AArch64::FRECPX_ZPmZ_D: |
| 7973 | case AArch64::FRECPX_ZPmZ_H: |
| 7974 | case AArch64::FRECPX_ZPmZ_S: |
| 7975 | case AArch64::FRINTA_ZPmZ_D: |
| 7976 | case AArch64::FRINTA_ZPmZ_H: |
| 7977 | case AArch64::FRINTA_ZPmZ_S: |
| 7978 | case AArch64::FRINTI_ZPmZ_D: |
| 7979 | case AArch64::FRINTI_ZPmZ_H: |
| 7980 | case AArch64::FRINTI_ZPmZ_S: |
| 7981 | case AArch64::FRINTM_ZPmZ_D: |
| 7982 | case AArch64::FRINTM_ZPmZ_H: |
| 7983 | case AArch64::FRINTM_ZPmZ_S: |
| 7984 | case AArch64::FRINTN_ZPmZ_D: |
| 7985 | case AArch64::FRINTN_ZPmZ_H: |
| 7986 | case AArch64::FRINTN_ZPmZ_S: |
| 7987 | case AArch64::FRINTP_ZPmZ_D: |
| 7988 | case AArch64::FRINTP_ZPmZ_H: |
| 7989 | case AArch64::FRINTP_ZPmZ_S: |
| 7990 | case AArch64::FRINTX_ZPmZ_D: |
| 7991 | case AArch64::FRINTX_ZPmZ_H: |
| 7992 | case AArch64::FRINTX_ZPmZ_S: |
| 7993 | case AArch64::FRINTZ_ZPmZ_D: |
| 7994 | case AArch64::FRINTZ_ZPmZ_H: |
| 7995 | case AArch64::FRINTZ_ZPmZ_S: |
| 7996 | case AArch64::FSQRT_ZPmZ_D: |
| 7997 | case AArch64::FSQRT_ZPmZ_H: |
| 7998 | case AArch64::FSQRT_ZPmZ_S: |
| 7999 | case AArch64::MOVPRFX_ZPmZ_B: |
| 8000 | case AArch64::MOVPRFX_ZPmZ_D: |
| 8001 | case AArch64::MOVPRFX_ZPmZ_H: |
| 8002 | case AArch64::MOVPRFX_ZPmZ_S: |
| 8003 | case AArch64::NEG_ZPmZ_B: |
| 8004 | case AArch64::NEG_ZPmZ_D: |
| 8005 | case AArch64::NEG_ZPmZ_H: |
| 8006 | case AArch64::NEG_ZPmZ_S: |
| 8007 | case AArch64::NOT_ZPmZ_B: |
| 8008 | case AArch64::NOT_ZPmZ_D: |
| 8009 | case AArch64::NOT_ZPmZ_H: |
| 8010 | case AArch64::NOT_ZPmZ_S: |
| 8011 | case AArch64::SCVTF_ZPmZ_DtoD: |
| 8012 | case AArch64::SCVTF_ZPmZ_DtoH: |
| 8013 | case AArch64::SCVTF_ZPmZ_DtoS: |
| 8014 | case AArch64::SCVTF_ZPmZ_HtoH: |
| 8015 | case AArch64::SCVTF_ZPmZ_StoD: |
| 8016 | case AArch64::SCVTF_ZPmZ_StoH: |
| 8017 | case AArch64::SCVTF_ZPmZ_StoS: |
| 8018 | case AArch64::SQABS_ZPmZ_B: |
| 8019 | case AArch64::SQABS_ZPmZ_D: |
| 8020 | case AArch64::SQABS_ZPmZ_H: |
| 8021 | case AArch64::SQABS_ZPmZ_S: |
| 8022 | case AArch64::SQNEG_ZPmZ_B: |
| 8023 | case AArch64::SQNEG_ZPmZ_D: |
| 8024 | case AArch64::SQNEG_ZPmZ_H: |
| 8025 | case AArch64::SQNEG_ZPmZ_S: |
| 8026 | case AArch64::SXTB_ZPmZ_D: |
| 8027 | case AArch64::SXTB_ZPmZ_H: |
| 8028 | case AArch64::SXTB_ZPmZ_S: |
| 8029 | case AArch64::SXTH_ZPmZ_D: |
| 8030 | case AArch64::SXTH_ZPmZ_S: |
| 8031 | case AArch64::SXTW_ZPmZ_D: |
| 8032 | case AArch64::UCVTF_ZPmZ_DtoD: |
| 8033 | case AArch64::UCVTF_ZPmZ_DtoH: |
| 8034 | case AArch64::UCVTF_ZPmZ_DtoS: |
| 8035 | case AArch64::UCVTF_ZPmZ_HtoH: |
| 8036 | case AArch64::UCVTF_ZPmZ_StoD: |
| 8037 | case AArch64::UCVTF_ZPmZ_StoH: |
| 8038 | case AArch64::UCVTF_ZPmZ_StoS: |
| 8039 | case AArch64::URECPE_ZPmZ_S: |
| 8040 | case AArch64::URSQRTE_ZPmZ_S: |
| 8041 | case AArch64::UXTB_ZPmZ_D: |
| 8042 | case AArch64::UXTB_ZPmZ_H: |
| 8043 | case AArch64::UXTB_ZPmZ_S: |
| 8044 | case AArch64::UXTH_ZPmZ_D: |
| 8045 | case AArch64::UXTH_ZPmZ_S: |
| 8046 | case AArch64::UXTW_ZPmZ_D: { |
| 8047 | // op: Pg |
| 8048 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 8049 | op &= UINT64_C(7); |
| 8050 | op <<= 10; |
| 8051 | Value |= op; |
| 8052 | // op: Zd |
| 8053 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 8054 | op &= UINT64_C(31); |
| 8055 | Value |= op; |
| 8056 | // op: Zn |
| 8057 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 8058 | op &= UINT64_C(31); |
| 8059 | op <<= 5; |
| 8060 | Value |= op; |
| 8061 | break; |
| 8062 | } |
| 8063 | case AArch64::DECP_ZP_D: |
| 8064 | case AArch64::DECP_ZP_H: |
| 8065 | case AArch64::DECP_ZP_S: |
| 8066 | case AArch64::INCP_ZP_D: |
| 8067 | case AArch64::INCP_ZP_H: |
| 8068 | case AArch64::INCP_ZP_S: |
| 8069 | case AArch64::SQDECP_ZP_D: |
| 8070 | case AArch64::SQDECP_ZP_H: |
| 8071 | case AArch64::SQDECP_ZP_S: |
| 8072 | case AArch64::SQINCP_ZP_D: |
| 8073 | case AArch64::SQINCP_ZP_H: |
| 8074 | case AArch64::SQINCP_ZP_S: |
| 8075 | case AArch64::UQDECP_ZP_D: |
| 8076 | case AArch64::UQDECP_ZP_H: |
| 8077 | case AArch64::UQDECP_ZP_S: |
| 8078 | case AArch64::UQINCP_ZP_D: |
| 8079 | case AArch64::UQINCP_ZP_H: |
| 8080 | case AArch64::UQINCP_ZP_S: { |
| 8081 | // op: Pm |
| 8082 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 8083 | op &= UINT64_C(15); |
| 8084 | op <<= 5; |
| 8085 | Value |= op; |
| 8086 | // op: Zdn |
| 8087 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 8088 | op &= UINT64_C(31); |
| 8089 | Value |= op; |
| 8090 | break; |
| 8091 | } |
| 8092 | case AArch64::WRFFR: { |
| 8093 | // op: Pn |
| 8094 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 8095 | op &= UINT64_C(15); |
| 8096 | op <<= 5; |
| 8097 | Value |= op; |
| 8098 | break; |
| 8099 | } |
| 8100 | case AArch64::LDR_PXI: |
| 8101 | case AArch64::STR_PXI: { |
| 8102 | // op: Pt |
| 8103 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 8104 | op &= UINT64_C(15); |
| 8105 | Value |= op; |
| 8106 | // op: Rn |
| 8107 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 8108 | op &= UINT64_C(31); |
| 8109 | op <<= 5; |
| 8110 | Value |= op; |
| 8111 | // op: imm9 |
| 8112 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 8113 | Value |= (op & UINT64_C(504)) << 13; |
| 8114 | Value |= (op & UINT64_C(7)) << 10; |
| 8115 | break; |
| 8116 | } |
| 8117 | case AArch64::AUTDZA: |
| 8118 | case AArch64::AUTDZB: |
| 8119 | case AArch64::AUTIZA: |
| 8120 | case AArch64::AUTIZB: |
| 8121 | case AArch64::PACDZA: |
| 8122 | case AArch64::PACDZB: |
| 8123 | case AArch64::PACIZA: |
| 8124 | case AArch64::PACIZB: |
| 8125 | case AArch64::XPACD: |
| 8126 | case AArch64::XPACI: { |
| 8127 | // op: Rd |
| 8128 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 8129 | op &= UINT64_C(31); |
| 8130 | Value |= op; |
| 8131 | break; |
| 8132 | } |
| 8133 | case AArch64::ADDPL_XXI: |
| 8134 | case AArch64::ADDVL_XXI: { |
| 8135 | // op: Rd |
| 8136 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 8137 | op &= UINT64_C(31); |
| 8138 | Value |= op; |
| 8139 | // op: Rn |
| 8140 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 8141 | op &= UINT64_C(31); |
| 8142 | op <<= 16; |
| 8143 | Value |= op; |
| 8144 | // op: imm6 |
| 8145 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 8146 | op &= UINT64_C(63); |
| 8147 | op <<= 5; |
| 8148 | Value |= op; |
| 8149 | break; |
| 8150 | } |
| 8151 | case AArch64::ABSv16i8: |
| 8152 | case AArch64::ABSv1i64: |
| 8153 | case AArch64::ABSv2i32: |
| 8154 | case AArch64::ABSv2i64: |
| 8155 | case AArch64::ABSv4i16: |
| 8156 | case AArch64::ABSv4i32: |
| 8157 | case AArch64::ABSv8i16: |
| 8158 | case AArch64::ABSv8i8: |
| 8159 | case AArch64::ADDPv2i64p: |
| 8160 | case AArch64::ADDVv16i8v: |
| 8161 | case AArch64::ADDVv4i16v: |
| 8162 | case AArch64::ADDVv4i32v: |
| 8163 | case AArch64::ADDVv8i16v: |
| 8164 | case AArch64::ADDVv8i8v: |
| 8165 | case AArch64::AESIMCrr: |
| 8166 | case AArch64::AESMCrr: |
| 8167 | case AArch64::AUTDA: |
| 8168 | case AArch64::AUTDB: |
| 8169 | case AArch64::AUTIA: |
| 8170 | case AArch64::AUTIB: |
| 8171 | case AArch64::BFCVT: |
| 8172 | case AArch64::BFCVTN: |
| 8173 | case AArch64::CLSWr: |
| 8174 | case AArch64::CLSXr: |
| 8175 | case AArch64::CLSv16i8: |
| 8176 | case AArch64::CLSv2i32: |
| 8177 | case AArch64::CLSv4i16: |
| 8178 | case AArch64::CLSv4i32: |
| 8179 | case AArch64::CLSv8i16: |
| 8180 | case AArch64::CLSv8i8: |
| 8181 | case AArch64::CLZWr: |
| 8182 | case AArch64::CLZXr: |
| 8183 | case AArch64::CLZv16i8: |
| 8184 | case AArch64::CLZv2i32: |
| 8185 | case AArch64::CLZv4i16: |
| 8186 | case AArch64::CLZv4i32: |
| 8187 | case AArch64::CLZv8i16: |
| 8188 | case AArch64::CLZv8i8: |
| 8189 | case AArch64::CMEQv16i8rz: |
| 8190 | case AArch64::CMEQv1i64rz: |
| 8191 | case AArch64::CMEQv2i32rz: |
| 8192 | case AArch64::CMEQv2i64rz: |
| 8193 | case AArch64::CMEQv4i16rz: |
| 8194 | case AArch64::CMEQv4i32rz: |
| 8195 | case AArch64::CMEQv8i16rz: |
| 8196 | case AArch64::CMEQv8i8rz: |
| 8197 | case AArch64::CMGEv16i8rz: |
| 8198 | case AArch64::CMGEv1i64rz: |
| 8199 | case AArch64::CMGEv2i32rz: |
| 8200 | case AArch64::CMGEv2i64rz: |
| 8201 | case AArch64::CMGEv4i16rz: |
| 8202 | case AArch64::CMGEv4i32rz: |
| 8203 | case AArch64::CMGEv8i16rz: |
| 8204 | case AArch64::CMGEv8i8rz: |
| 8205 | case AArch64::CMGTv16i8rz: |
| 8206 | case AArch64::CMGTv1i64rz: |
| 8207 | case AArch64::CMGTv2i32rz: |
| 8208 | case AArch64::CMGTv2i64rz: |
| 8209 | case AArch64::CMGTv4i16rz: |
| 8210 | case AArch64::CMGTv4i32rz: |
| 8211 | case AArch64::CMGTv8i16rz: |
| 8212 | case AArch64::CMGTv8i8rz: |
| 8213 | case AArch64::CMLEv16i8rz: |
| 8214 | case AArch64::CMLEv1i64rz: |
| 8215 | case AArch64::CMLEv2i32rz: |
| 8216 | case AArch64::CMLEv2i64rz: |
| 8217 | case AArch64::CMLEv4i16rz: |
| 8218 | case AArch64::CMLEv4i32rz: |
| 8219 | case AArch64::CMLEv8i16rz: |
| 8220 | case AArch64::CMLEv8i8rz: |
| 8221 | case AArch64::CMLTv16i8rz: |
| 8222 | case AArch64::CMLTv1i64rz: |
| 8223 | case AArch64::CMLTv2i32rz: |
| 8224 | case AArch64::CMLTv2i64rz: |
| 8225 | case AArch64::CMLTv4i16rz: |
| 8226 | case AArch64::CMLTv4i32rz: |
| 8227 | case AArch64::CMLTv8i16rz: |
| 8228 | case AArch64::CMLTv8i8rz: |
| 8229 | case AArch64::CNTv16i8: |
| 8230 | case AArch64::CNTv8i8: |
| 8231 | case AArch64::DUPv16i8gpr: |
| 8232 | case AArch64::DUPv2i32gpr: |
| 8233 | case AArch64::DUPv2i64gpr: |
| 8234 | case AArch64::DUPv4i16gpr: |
| 8235 | case AArch64::DUPv4i32gpr: |
| 8236 | case AArch64::DUPv8i16gpr: |
| 8237 | case AArch64::DUPv8i8gpr: |
| 8238 | case AArch64::FABSDr: |
| 8239 | case AArch64::FABSHr: |
| 8240 | case AArch64::FABSSr: |
| 8241 | case AArch64::FABSv2f32: |
| 8242 | case AArch64::FABSv2f64: |
| 8243 | case AArch64::FABSv4f16: |
| 8244 | case AArch64::FABSv4f32: |
| 8245 | case AArch64::FABSv8f16: |
| 8246 | case AArch64::FADDPv2i16p: |
| 8247 | case AArch64::FADDPv2i32p: |
| 8248 | case AArch64::FADDPv2i64p: |
| 8249 | case AArch64::FCMEQv1i16rz: |
| 8250 | case AArch64::FCMEQv1i32rz: |
| 8251 | case AArch64::FCMEQv1i64rz: |
| 8252 | case AArch64::FCMEQv2i32rz: |
| 8253 | case AArch64::FCMEQv2i64rz: |
| 8254 | case AArch64::FCMEQv4i16rz: |
| 8255 | case AArch64::FCMEQv4i32rz: |
| 8256 | case AArch64::FCMEQv8i16rz: |
| 8257 | case AArch64::FCMGEv1i16rz: |
| 8258 | case AArch64::FCMGEv1i32rz: |
| 8259 | case AArch64::FCMGEv1i64rz: |
| 8260 | case AArch64::FCMGEv2i32rz: |
| 8261 | case AArch64::FCMGEv2i64rz: |
| 8262 | case AArch64::FCMGEv4i16rz: |
| 8263 | case AArch64::FCMGEv4i32rz: |
| 8264 | case AArch64::FCMGEv8i16rz: |
| 8265 | case AArch64::FCMGTv1i16rz: |
| 8266 | case AArch64::FCMGTv1i32rz: |
| 8267 | case AArch64::FCMGTv1i64rz: |
| 8268 | case AArch64::FCMGTv2i32rz: |
| 8269 | case AArch64::FCMGTv2i64rz: |
| 8270 | case AArch64::FCMGTv4i16rz: |
| 8271 | case AArch64::FCMGTv4i32rz: |
| 8272 | case AArch64::FCMGTv8i16rz: |
| 8273 | case AArch64::FCMLEv1i16rz: |
| 8274 | case AArch64::FCMLEv1i32rz: |
| 8275 | case AArch64::FCMLEv1i64rz: |
| 8276 | case AArch64::FCMLEv2i32rz: |
| 8277 | case AArch64::FCMLEv2i64rz: |
| 8278 | case AArch64::FCMLEv4i16rz: |
| 8279 | case AArch64::FCMLEv4i32rz: |
| 8280 | case AArch64::FCMLEv8i16rz: |
| 8281 | case AArch64::FCMLTv1i16rz: |
| 8282 | case AArch64::FCMLTv1i32rz: |
| 8283 | case AArch64::FCMLTv1i64rz: |
| 8284 | case AArch64::FCMLTv2i32rz: |
| 8285 | case AArch64::FCMLTv2i64rz: |
| 8286 | case AArch64::FCMLTv4i16rz: |
| 8287 | case AArch64::FCMLTv4i32rz: |
| 8288 | case AArch64::FCMLTv8i16rz: |
| 8289 | case AArch64::FCVTASUWDr: |
| 8290 | case AArch64::FCVTASUWHr: |
| 8291 | case AArch64::FCVTASUWSr: |
| 8292 | case AArch64::FCVTASUXDr: |
| 8293 | case AArch64::FCVTASUXHr: |
| 8294 | case AArch64::FCVTASUXSr: |
| 8295 | case AArch64::FCVTASv1f16: |
| 8296 | case AArch64::FCVTASv1i32: |
| 8297 | case AArch64::FCVTASv1i64: |
| 8298 | case AArch64::FCVTASv2f32: |
| 8299 | case AArch64::FCVTASv2f64: |
| 8300 | case AArch64::FCVTASv4f16: |
| 8301 | case AArch64::FCVTASv4f32: |
| 8302 | case AArch64::FCVTASv8f16: |
| 8303 | case AArch64::FCVTAUUWDr: |
| 8304 | case AArch64::FCVTAUUWHr: |
| 8305 | case AArch64::FCVTAUUWSr: |
| 8306 | case AArch64::FCVTAUUXDr: |
| 8307 | case AArch64::FCVTAUUXHr: |
| 8308 | case AArch64::FCVTAUUXSr: |
| 8309 | case AArch64::FCVTAUv1f16: |
| 8310 | case AArch64::FCVTAUv1i32: |
| 8311 | case AArch64::FCVTAUv1i64: |
| 8312 | case AArch64::FCVTAUv2f32: |
| 8313 | case AArch64::FCVTAUv2f64: |
| 8314 | case AArch64::FCVTAUv4f16: |
| 8315 | case AArch64::FCVTAUv4f32: |
| 8316 | case AArch64::FCVTAUv8f16: |
| 8317 | case AArch64::FCVTDHr: |
| 8318 | case AArch64::FCVTDSr: |
| 8319 | case AArch64::FCVTHDr: |
| 8320 | case AArch64::FCVTHSr: |
| 8321 | case AArch64::FCVTLv2i32: |
| 8322 | case AArch64::FCVTLv4i16: |
| 8323 | case AArch64::FCVTLv4i32: |
| 8324 | case AArch64::FCVTLv8i16: |
| 8325 | case AArch64::FCVTMSUWDr: |
| 8326 | case AArch64::FCVTMSUWHr: |
| 8327 | case AArch64::FCVTMSUWSr: |
| 8328 | case AArch64::FCVTMSUXDr: |
| 8329 | case AArch64::FCVTMSUXHr: |
| 8330 | case AArch64::FCVTMSUXSr: |
| 8331 | case AArch64::FCVTMSv1f16: |
| 8332 | case AArch64::FCVTMSv1i32: |
| 8333 | case AArch64::FCVTMSv1i64: |
| 8334 | case AArch64::FCVTMSv2f32: |
| 8335 | case AArch64::FCVTMSv2f64: |
| 8336 | case AArch64::FCVTMSv4f16: |
| 8337 | case AArch64::FCVTMSv4f32: |
| 8338 | case AArch64::FCVTMSv8f16: |
| 8339 | case AArch64::FCVTMUUWDr: |
| 8340 | case AArch64::FCVTMUUWHr: |
| 8341 | case AArch64::FCVTMUUWSr: |
| 8342 | case AArch64::FCVTMUUXDr: |
| 8343 | case AArch64::FCVTMUUXHr: |
| 8344 | case AArch64::FCVTMUUXSr: |
| 8345 | case AArch64::FCVTMUv1f16: |
| 8346 | case AArch64::FCVTMUv1i32: |
| 8347 | case AArch64::FCVTMUv1i64: |
| 8348 | case AArch64::FCVTMUv2f32: |
| 8349 | case AArch64::FCVTMUv2f64: |
| 8350 | case AArch64::FCVTMUv4f16: |
| 8351 | case AArch64::FCVTMUv4f32: |
| 8352 | case AArch64::FCVTMUv8f16: |
| 8353 | case AArch64::FCVTNSUWDr: |
| 8354 | case AArch64::FCVTNSUWHr: |
| 8355 | case AArch64::FCVTNSUWSr: |
| 8356 | case AArch64::FCVTNSUXDr: |
| 8357 | case AArch64::FCVTNSUXHr: |
| 8358 | case AArch64::FCVTNSUXSr: |
| 8359 | case AArch64::FCVTNSv1f16: |
| 8360 | case AArch64::FCVTNSv1i32: |
| 8361 | case AArch64::FCVTNSv1i64: |
| 8362 | case AArch64::FCVTNSv2f32: |
| 8363 | case AArch64::FCVTNSv2f64: |
| 8364 | case AArch64::FCVTNSv4f16: |
| 8365 | case AArch64::FCVTNSv4f32: |
| 8366 | case AArch64::FCVTNSv8f16: |
| 8367 | case AArch64::FCVTNUUWDr: |
| 8368 | case AArch64::FCVTNUUWHr: |
| 8369 | case AArch64::FCVTNUUWSr: |
| 8370 | case AArch64::FCVTNUUXDr: |
| 8371 | case AArch64::FCVTNUUXHr: |
| 8372 | case AArch64::FCVTNUUXSr: |
| 8373 | case AArch64::FCVTNUv1f16: |
| 8374 | case AArch64::FCVTNUv1i32: |
| 8375 | case AArch64::FCVTNUv1i64: |
| 8376 | case AArch64::FCVTNUv2f32: |
| 8377 | case AArch64::FCVTNUv2f64: |
| 8378 | case AArch64::FCVTNUv4f16: |
| 8379 | case AArch64::FCVTNUv4f32: |
| 8380 | case AArch64::FCVTNUv8f16: |
| 8381 | case AArch64::FCVTNv2i32: |
| 8382 | case AArch64::FCVTNv4i16: |
| 8383 | case AArch64::FCVTPSUWDr: |
| 8384 | case AArch64::FCVTPSUWHr: |
| 8385 | case AArch64::FCVTPSUWSr: |
| 8386 | case AArch64::FCVTPSUXDr: |
| 8387 | case AArch64::FCVTPSUXHr: |
| 8388 | case AArch64::FCVTPSUXSr: |
| 8389 | case AArch64::FCVTPSv1f16: |
| 8390 | case AArch64::FCVTPSv1i32: |
| 8391 | case AArch64::FCVTPSv1i64: |
| 8392 | case AArch64::FCVTPSv2f32: |
| 8393 | case AArch64::FCVTPSv2f64: |
| 8394 | case AArch64::FCVTPSv4f16: |
| 8395 | case AArch64::FCVTPSv4f32: |
| 8396 | case AArch64::FCVTPSv8f16: |
| 8397 | case AArch64::FCVTPUUWDr: |
| 8398 | case AArch64::FCVTPUUWHr: |
| 8399 | case AArch64::FCVTPUUWSr: |
| 8400 | case AArch64::FCVTPUUXDr: |
| 8401 | case AArch64::FCVTPUUXHr: |
| 8402 | case AArch64::FCVTPUUXSr: |
| 8403 | case AArch64::FCVTPUv1f16: |
| 8404 | case AArch64::FCVTPUv1i32: |
| 8405 | case AArch64::FCVTPUv1i64: |
| 8406 | case AArch64::FCVTPUv2f32: |
| 8407 | case AArch64::FCVTPUv2f64: |
| 8408 | case AArch64::FCVTPUv4f16: |
| 8409 | case AArch64::FCVTPUv4f32: |
| 8410 | case AArch64::FCVTPUv8f16: |
| 8411 | case AArch64::FCVTSDr: |
| 8412 | case AArch64::FCVTSHr: |
| 8413 | case AArch64::FCVTXNv1i64: |
| 8414 | case AArch64::FCVTXNv2f32: |
| 8415 | case AArch64::FCVTZSUWDr: |
| 8416 | case AArch64::FCVTZSUWHr: |
| 8417 | case AArch64::FCVTZSUWSr: |
| 8418 | case AArch64::FCVTZSUXDr: |
| 8419 | case AArch64::FCVTZSUXHr: |
| 8420 | case AArch64::FCVTZSUXSr: |
| 8421 | case AArch64::FCVTZSv1f16: |
| 8422 | case AArch64::FCVTZSv1i32: |
| 8423 | case AArch64::FCVTZSv1i64: |
| 8424 | case AArch64::FCVTZSv2f32: |
| 8425 | case AArch64::FCVTZSv2f64: |
| 8426 | case AArch64::FCVTZSv4f16: |
| 8427 | case AArch64::FCVTZSv4f32: |
| 8428 | case AArch64::FCVTZSv8f16: |
| 8429 | case AArch64::FCVTZUUWDr: |
| 8430 | case AArch64::FCVTZUUWHr: |
| 8431 | case AArch64::FCVTZUUWSr: |
| 8432 | case AArch64::FCVTZUUXDr: |
| 8433 | case AArch64::FCVTZUUXHr: |
| 8434 | case AArch64::FCVTZUUXSr: |
| 8435 | case AArch64::FCVTZUv1f16: |
| 8436 | case AArch64::FCVTZUv1i32: |
| 8437 | case AArch64::FCVTZUv1i64: |
| 8438 | case AArch64::FCVTZUv2f32: |
| 8439 | case AArch64::FCVTZUv2f64: |
| 8440 | case AArch64::FCVTZUv4f16: |
| 8441 | case AArch64::FCVTZUv4f32: |
| 8442 | case AArch64::FCVTZUv8f16: |
| 8443 | case AArch64::FJCVTZS: |
| 8444 | case AArch64::FMAXNMPv2i16p: |
| 8445 | case AArch64::FMAXNMPv2i32p: |
| 8446 | case AArch64::FMAXNMPv2i64p: |
| 8447 | case AArch64::FMAXNMVv4i16v: |
| 8448 | case AArch64::FMAXNMVv4i32v: |
| 8449 | case AArch64::FMAXNMVv8i16v: |
| 8450 | case AArch64::FMAXPv2i16p: |
| 8451 | case AArch64::FMAXPv2i32p: |
| 8452 | case AArch64::FMAXPv2i64p: |
| 8453 | case AArch64::FMAXVv4i16v: |
| 8454 | case AArch64::FMAXVv4i32v: |
| 8455 | case AArch64::FMAXVv8i16v: |
| 8456 | case AArch64::FMINNMPv2i16p: |
| 8457 | case AArch64::FMINNMPv2i32p: |
| 8458 | case AArch64::FMINNMPv2i64p: |
| 8459 | case AArch64::FMINNMVv4i16v: |
| 8460 | case AArch64::FMINNMVv4i32v: |
| 8461 | case AArch64::FMINNMVv8i16v: |
| 8462 | case AArch64::FMINPv2i16p: |
| 8463 | case AArch64::FMINPv2i32p: |
| 8464 | case AArch64::FMINPv2i64p: |
| 8465 | case AArch64::FMINVv4i16v: |
| 8466 | case AArch64::FMINVv4i32v: |
| 8467 | case AArch64::FMINVv8i16v: |
| 8468 | case AArch64::FMOVDXHighr: |
| 8469 | case AArch64::FMOVDXr: |
| 8470 | case AArch64::FMOVDr: |
| 8471 | case AArch64::FMOVHWr: |
| 8472 | case AArch64::FMOVHXr: |
| 8473 | case AArch64::FMOVHr: |
| 8474 | case AArch64::FMOVSWr: |
| 8475 | case AArch64::FMOVSr: |
| 8476 | case AArch64::FMOVWHr: |
| 8477 | case AArch64::FMOVWSr: |
| 8478 | case AArch64::FMOVXDHighr: |
| 8479 | case AArch64::FMOVXDr: |
| 8480 | case AArch64::FMOVXHr: |
| 8481 | case AArch64::FNEGDr: |
| 8482 | case AArch64::FNEGHr: |
| 8483 | case AArch64::FNEGSr: |
| 8484 | case AArch64::FNEGv2f32: |
| 8485 | case AArch64::FNEGv2f64: |
| 8486 | case AArch64::FNEGv4f16: |
| 8487 | case AArch64::FNEGv4f32: |
| 8488 | case AArch64::FNEGv8f16: |
| 8489 | case AArch64::FRECPEv1f16: |
| 8490 | case AArch64::FRECPEv1i32: |
| 8491 | case AArch64::FRECPEv1i64: |
| 8492 | case AArch64::FRECPEv2f32: |
| 8493 | case AArch64::FRECPEv2f64: |
| 8494 | case AArch64::FRECPEv4f16: |
| 8495 | case AArch64::FRECPEv4f32: |
| 8496 | case AArch64::FRECPEv8f16: |
| 8497 | case AArch64::FRECPXv1f16: |
| 8498 | case AArch64::FRECPXv1i32: |
| 8499 | case AArch64::FRECPXv1i64: |
| 8500 | case AArch64::FRINT32XDr: |
| 8501 | case AArch64::FRINT32XSr: |
| 8502 | case AArch64::FRINT32Xv2f32: |
| 8503 | case AArch64::FRINT32Xv2f64: |
| 8504 | case AArch64::FRINT32Xv4f32: |
| 8505 | case AArch64::FRINT32ZDr: |
| 8506 | case AArch64::FRINT32ZSr: |
| 8507 | case AArch64::FRINT32Zv2f32: |
| 8508 | case AArch64::FRINT32Zv2f64: |
| 8509 | case AArch64::FRINT32Zv4f32: |
| 8510 | case AArch64::FRINT64XDr: |
| 8511 | case AArch64::FRINT64XSr: |
| 8512 | case AArch64::FRINT64Xv2f32: |
| 8513 | case AArch64::FRINT64Xv2f64: |
| 8514 | case AArch64::FRINT64Xv4f32: |
| 8515 | case AArch64::FRINT64ZDr: |
| 8516 | case AArch64::FRINT64ZSr: |
| 8517 | case AArch64::FRINT64Zv2f32: |
| 8518 | case AArch64::FRINT64Zv2f64: |
| 8519 | case AArch64::FRINT64Zv4f32: |
| 8520 | case AArch64::FRINTADr: |
| 8521 | case AArch64::FRINTAHr: |
| 8522 | case AArch64::FRINTASr: |
| 8523 | case AArch64::FRINTAv2f32: |
| 8524 | case AArch64::FRINTAv2f64: |
| 8525 | case AArch64::FRINTAv4f16: |
| 8526 | case AArch64::FRINTAv4f32: |
| 8527 | case AArch64::FRINTAv8f16: |
| 8528 | case AArch64::FRINTIDr: |
| 8529 | case AArch64::FRINTIHr: |
| 8530 | case AArch64::FRINTISr: |
| 8531 | case AArch64::FRINTIv2f32: |
| 8532 | case AArch64::FRINTIv2f64: |
| 8533 | case AArch64::FRINTIv4f16: |
| 8534 | case AArch64::FRINTIv4f32: |
| 8535 | case AArch64::FRINTIv8f16: |
| 8536 | case AArch64::FRINTMDr: |
| 8537 | case AArch64::FRINTMHr: |
| 8538 | case AArch64::FRINTMSr: |
| 8539 | case AArch64::FRINTMv2f32: |
| 8540 | case AArch64::FRINTMv2f64: |
| 8541 | case AArch64::FRINTMv4f16: |
| 8542 | case AArch64::FRINTMv4f32: |
| 8543 | case AArch64::FRINTMv8f16: |
| 8544 | case AArch64::FRINTNDr: |
| 8545 | case AArch64::FRINTNHr: |
| 8546 | case AArch64::FRINTNSr: |
| 8547 | case AArch64::FRINTNv2f32: |
| 8548 | case AArch64::FRINTNv2f64: |
| 8549 | case AArch64::FRINTNv4f16: |
| 8550 | case AArch64::FRINTNv4f32: |
| 8551 | case AArch64::FRINTNv8f16: |
| 8552 | case AArch64::FRINTPDr: |
| 8553 | case AArch64::FRINTPHr: |
| 8554 | case AArch64::FRINTPSr: |
| 8555 | case AArch64::FRINTPv2f32: |
| 8556 | case AArch64::FRINTPv2f64: |
| 8557 | case AArch64::FRINTPv4f16: |
| 8558 | case AArch64::FRINTPv4f32: |
| 8559 | case AArch64::FRINTPv8f16: |
| 8560 | case AArch64::FRINTXDr: |
| 8561 | case AArch64::FRINTXHr: |
| 8562 | case AArch64::FRINTXSr: |
| 8563 | case AArch64::FRINTXv2f32: |
| 8564 | case AArch64::FRINTXv2f64: |
| 8565 | case AArch64::FRINTXv4f16: |
| 8566 | case AArch64::FRINTXv4f32: |
| 8567 | case AArch64::FRINTXv8f16: |
| 8568 | case AArch64::FRINTZDr: |
| 8569 | case AArch64::FRINTZHr: |
| 8570 | case AArch64::FRINTZSr: |
| 8571 | case AArch64::FRINTZv2f32: |
| 8572 | case AArch64::FRINTZv2f64: |
| 8573 | case AArch64::FRINTZv4f16: |
| 8574 | case AArch64::FRINTZv4f32: |
| 8575 | case AArch64::FRINTZv8f16: |
| 8576 | case AArch64::FRSQRTEv1f16: |
| 8577 | case AArch64::FRSQRTEv1i32: |
| 8578 | case AArch64::FRSQRTEv1i64: |
| 8579 | case AArch64::FRSQRTEv2f32: |
| 8580 | case AArch64::FRSQRTEv2f64: |
| 8581 | case AArch64::FRSQRTEv4f16: |
| 8582 | case AArch64::FRSQRTEv4f32: |
| 8583 | case AArch64::FRSQRTEv8f16: |
| 8584 | case AArch64::FSQRTDr: |
| 8585 | case AArch64::FSQRTHr: |
| 8586 | case AArch64::FSQRTSr: |
| 8587 | case AArch64::FSQRTv2f32: |
| 8588 | case AArch64::FSQRTv2f64: |
| 8589 | case AArch64::FSQRTv4f16: |
| 8590 | case AArch64::FSQRTv4f32: |
| 8591 | case AArch64::FSQRTv8f16: |
| 8592 | case AArch64::NEGv16i8: |
| 8593 | case AArch64::NEGv1i64: |
| 8594 | case AArch64::NEGv2i32: |
| 8595 | case AArch64::NEGv2i64: |
| 8596 | case AArch64::NEGv4i16: |
| 8597 | case AArch64::NEGv4i32: |
| 8598 | case AArch64::NEGv8i16: |
| 8599 | case AArch64::NEGv8i8: |
| 8600 | case AArch64::NOTv16i8: |
| 8601 | case AArch64::NOTv8i8: |
| 8602 | case AArch64::PACDA: |
| 8603 | case AArch64::PACDB: |
| 8604 | case AArch64::PACIA: |
| 8605 | case AArch64::PACIB: |
| 8606 | case AArch64::RBITWr: |
| 8607 | case AArch64::RBITXr: |
| 8608 | case AArch64::RBITv16i8: |
| 8609 | case AArch64::RBITv8i8: |
| 8610 | case AArch64::REV16Wr: |
| 8611 | case AArch64::REV16Xr: |
| 8612 | case AArch64::REV16v16i8: |
| 8613 | case AArch64::REV16v8i8: |
| 8614 | case AArch64::REV32Xr: |
| 8615 | case AArch64::REV32v16i8: |
| 8616 | case AArch64::REV32v4i16: |
| 8617 | case AArch64::REV32v8i16: |
| 8618 | case AArch64::REV32v8i8: |
| 8619 | case AArch64::REV64v16i8: |
| 8620 | case AArch64::REV64v2i32: |
| 8621 | case AArch64::REV64v4i16: |
| 8622 | case AArch64::REV64v4i32: |
| 8623 | case AArch64::REV64v8i16: |
| 8624 | case AArch64::REV64v8i8: |
| 8625 | case AArch64::REVWr: |
| 8626 | case AArch64::REVXr: |
| 8627 | case AArch64::SADDLPv16i8_v8i16: |
| 8628 | case AArch64::SADDLPv2i32_v1i64: |
| 8629 | case AArch64::SADDLPv4i16_v2i32: |
| 8630 | case AArch64::SADDLPv4i32_v2i64: |
| 8631 | case AArch64::SADDLPv8i16_v4i32: |
| 8632 | case AArch64::SADDLPv8i8_v4i16: |
| 8633 | case AArch64::SADDLVv16i8v: |
| 8634 | case AArch64::SADDLVv4i16v: |
| 8635 | case AArch64::SADDLVv4i32v: |
| 8636 | case AArch64::SADDLVv8i16v: |
| 8637 | case AArch64::SADDLVv8i8v: |
| 8638 | case AArch64::SCVTFUWDri: |
| 8639 | case AArch64::SCVTFUWHri: |
| 8640 | case AArch64::SCVTFUWSri: |
| 8641 | case AArch64::SCVTFUXDri: |
| 8642 | case AArch64::SCVTFUXHri: |
| 8643 | case AArch64::SCVTFUXSri: |
| 8644 | case AArch64::SCVTFv1i16: |
| 8645 | case AArch64::SCVTFv1i32: |
| 8646 | case AArch64::SCVTFv1i64: |
| 8647 | case AArch64::SCVTFv2f32: |
| 8648 | case AArch64::SCVTFv2f64: |
| 8649 | case AArch64::SCVTFv4f16: |
| 8650 | case AArch64::SCVTFv4f32: |
| 8651 | case AArch64::SCVTFv8f16: |
| 8652 | case AArch64::SHA1Hrr: |
| 8653 | case AArch64::SHLLv16i8: |
| 8654 | case AArch64::SHLLv2i32: |
| 8655 | case AArch64::SHLLv4i16: |
| 8656 | case AArch64::SHLLv4i32: |
| 8657 | case AArch64::SHLLv8i16: |
| 8658 | case AArch64::SHLLv8i8: |
| 8659 | case AArch64::SMAXVv16i8v: |
| 8660 | case AArch64::SMAXVv4i16v: |
| 8661 | case AArch64::SMAXVv4i32v: |
| 8662 | case AArch64::SMAXVv8i16v: |
| 8663 | case AArch64::SMAXVv8i8v: |
| 8664 | case AArch64::SMINVv16i8v: |
| 8665 | case AArch64::SMINVv4i16v: |
| 8666 | case AArch64::SMINVv4i32v: |
| 8667 | case AArch64::SMINVv8i16v: |
| 8668 | case AArch64::SMINVv8i8v: |
| 8669 | case AArch64::SQABSv16i8: |
| 8670 | case AArch64::SQABSv1i16: |
| 8671 | case AArch64::SQABSv1i32: |
| 8672 | case AArch64::SQABSv1i64: |
| 8673 | case AArch64::SQABSv1i8: |
| 8674 | case AArch64::SQABSv2i32: |
| 8675 | case AArch64::SQABSv2i64: |
| 8676 | case AArch64::SQABSv4i16: |
| 8677 | case AArch64::SQABSv4i32: |
| 8678 | case AArch64::SQABSv8i16: |
| 8679 | case AArch64::SQABSv8i8: |
| 8680 | case AArch64::SQNEGv16i8: |
| 8681 | case AArch64::SQNEGv1i16: |
| 8682 | case AArch64::SQNEGv1i32: |
| 8683 | case AArch64::SQNEGv1i64: |
| 8684 | case AArch64::SQNEGv1i8: |
| 8685 | case AArch64::SQNEGv2i32: |
| 8686 | case AArch64::SQNEGv2i64: |
| 8687 | case AArch64::SQNEGv4i16: |
| 8688 | case AArch64::SQNEGv4i32: |
| 8689 | case AArch64::SQNEGv8i16: |
| 8690 | case AArch64::SQNEGv8i8: |
| 8691 | case AArch64::SQXTNv1i16: |
| 8692 | case AArch64::SQXTNv1i32: |
| 8693 | case AArch64::SQXTNv1i8: |
| 8694 | case AArch64::SQXTNv2i32: |
| 8695 | case AArch64::SQXTNv4i16: |
| 8696 | case AArch64::SQXTNv8i8: |
| 8697 | case AArch64::SQXTUNv1i16: |
| 8698 | case AArch64::SQXTUNv1i32: |
| 8699 | case AArch64::SQXTUNv1i8: |
| 8700 | case AArch64::SQXTUNv2i32: |
| 8701 | case AArch64::SQXTUNv4i16: |
| 8702 | case AArch64::SQXTUNv8i8: |
| 8703 | case AArch64::UADDLPv16i8_v8i16: |
| 8704 | case AArch64::UADDLPv2i32_v1i64: |
| 8705 | case AArch64::UADDLPv4i16_v2i32: |
| 8706 | case AArch64::UADDLPv4i32_v2i64: |
| 8707 | case AArch64::UADDLPv8i16_v4i32: |
| 8708 | case AArch64::UADDLPv8i8_v4i16: |
| 8709 | case AArch64::UADDLVv16i8v: |
| 8710 | case AArch64::UADDLVv4i16v: |
| 8711 | case AArch64::UADDLVv4i32v: |
| 8712 | case AArch64::UADDLVv8i16v: |
| 8713 | case AArch64::UADDLVv8i8v: |
| 8714 | case AArch64::UCVTFUWDri: |
| 8715 | case AArch64::UCVTFUWHri: |
| 8716 | case AArch64::UCVTFUWSri: |
| 8717 | case AArch64::UCVTFUXDri: |
| 8718 | case AArch64::UCVTFUXHri: |
| 8719 | case AArch64::UCVTFUXSri: |
| 8720 | case AArch64::UCVTFv1i16: |
| 8721 | case AArch64::UCVTFv1i32: |
| 8722 | case AArch64::UCVTFv1i64: |
| 8723 | case AArch64::UCVTFv2f32: |
| 8724 | case AArch64::UCVTFv2f64: |
| 8725 | case AArch64::UCVTFv4f16: |
| 8726 | case AArch64::UCVTFv4f32: |
| 8727 | case AArch64::UCVTFv8f16: |
| 8728 | case AArch64::UMAXVv16i8v: |
| 8729 | case AArch64::UMAXVv4i16v: |
| 8730 | case AArch64::UMAXVv4i32v: |
| 8731 | case AArch64::UMAXVv8i16v: |
| 8732 | case AArch64::UMAXVv8i8v: |
| 8733 | case AArch64::UMINVv16i8v: |
| 8734 | case AArch64::UMINVv4i16v: |
| 8735 | case AArch64::UMINVv4i32v: |
| 8736 | case AArch64::UMINVv8i16v: |
| 8737 | case AArch64::UMINVv8i8v: |
| 8738 | case AArch64::UQXTNv1i16: |
| 8739 | case AArch64::UQXTNv1i32: |
| 8740 | case AArch64::UQXTNv1i8: |
| 8741 | case AArch64::UQXTNv2i32: |
| 8742 | case AArch64::UQXTNv4i16: |
| 8743 | case AArch64::UQXTNv8i8: |
| 8744 | case AArch64::URECPEv2i32: |
| 8745 | case AArch64::URECPEv4i32: |
| 8746 | case AArch64::URSQRTEv2i32: |
| 8747 | case AArch64::URSQRTEv4i32: |
| 8748 | case AArch64::XTNv2i32: |
| 8749 | case AArch64::XTNv4i16: |
| 8750 | case AArch64::XTNv8i8: { |
| 8751 | // op: Rd |
| 8752 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 8753 | op &= UINT64_C(31); |
| 8754 | Value |= op; |
| 8755 | // op: Rn |
| 8756 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 8757 | op &= UINT64_C(31); |
| 8758 | op <<= 5; |
| 8759 | Value |= op; |
| 8760 | break; |
| 8761 | } |
| 8762 | case AArch64::FMULXv1i16_indexed: |
| 8763 | case AArch64::FMULXv4i16_indexed: |
| 8764 | case AArch64::FMULXv8i16_indexed: |
| 8765 | case AArch64::FMULv1i16_indexed: |
| 8766 | case AArch64::FMULv4i16_indexed: |
| 8767 | case AArch64::FMULv8i16_indexed: |
| 8768 | case AArch64::MULv4i16_indexed: |
| 8769 | case AArch64::MULv8i16_indexed: |
| 8770 | case AArch64::SMULLv4i16_indexed: |
| 8771 | case AArch64::SMULLv8i16_indexed: |
| 8772 | case AArch64::SQDMULHv1i16_indexed: |
| 8773 | case AArch64::SQDMULHv4i16_indexed: |
| 8774 | case AArch64::SQDMULHv8i16_indexed: |
| 8775 | case AArch64::SQDMULLv1i32_indexed: |
| 8776 | case AArch64::SQDMULLv4i16_indexed: |
| 8777 | case AArch64::SQDMULLv8i16_indexed: |
| 8778 | case AArch64::SQRDMULHv1i16_indexed: |
| 8779 | case AArch64::SQRDMULHv4i16_indexed: |
| 8780 | case AArch64::SQRDMULHv8i16_indexed: |
| 8781 | case AArch64::UMULLv4i16_indexed: |
| 8782 | case AArch64::UMULLv8i16_indexed: { |
| 8783 | // op: Rd |
| 8784 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 8785 | op &= UINT64_C(31); |
| 8786 | Value |= op; |
| 8787 | // op: Rn |
| 8788 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 8789 | op &= UINT64_C(31); |
| 8790 | op <<= 5; |
| 8791 | Value |= op; |
| 8792 | // op: Rm |
| 8793 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 8794 | op &= UINT64_C(15); |
| 8795 | op <<= 16; |
| 8796 | Value |= op; |
| 8797 | // op: idx |
| 8798 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 8799 | Value |= (op & UINT64_C(3)) << 20; |
| 8800 | Value |= (op & UINT64_C(4)) << 9; |
| 8801 | break; |
| 8802 | } |
| 8803 | case AArch64::ADCSWr: |
| 8804 | case AArch64::ADCSXr: |
| 8805 | case AArch64::ADCWr: |
| 8806 | case AArch64::ADCXr: |
| 8807 | case AArch64::ADDHNv2i64_v2i32: |
| 8808 | case AArch64::ADDHNv4i32_v4i16: |
| 8809 | case AArch64::ADDHNv8i16_v8i8: |
| 8810 | case AArch64::ADDPv16i8: |
| 8811 | case AArch64::ADDPv2i32: |
| 8812 | case AArch64::ADDPv2i64: |
| 8813 | case AArch64::ADDPv4i16: |
| 8814 | case AArch64::ADDPv4i32: |
| 8815 | case AArch64::ADDPv8i16: |
| 8816 | case AArch64::ADDPv8i8: |
| 8817 | case AArch64::ADDv16i8: |
| 8818 | case AArch64::ADDv1i64: |
| 8819 | case AArch64::ADDv2i32: |
| 8820 | case AArch64::ADDv2i64: |
| 8821 | case AArch64::ADDv4i16: |
| 8822 | case AArch64::ADDv4i32: |
| 8823 | case AArch64::ADDv8i16: |
| 8824 | case AArch64::ADDv8i8: |
| 8825 | case AArch64::ANDv16i8: |
| 8826 | case AArch64::ANDv8i8: |
| 8827 | case AArch64::ASRVWr: |
| 8828 | case AArch64::ASRVXr: |
| 8829 | case AArch64::BICv16i8: |
| 8830 | case AArch64::BICv8i8: |
| 8831 | case AArch64::CMEQv16i8: |
| 8832 | case AArch64::CMEQv1i64: |
| 8833 | case AArch64::CMEQv2i32: |
| 8834 | case AArch64::CMEQv2i64: |
| 8835 | case AArch64::CMEQv4i16: |
| 8836 | case AArch64::CMEQv4i32: |
| 8837 | case AArch64::CMEQv8i16: |
| 8838 | case AArch64::CMEQv8i8: |
| 8839 | case AArch64::CMGEv16i8: |
| 8840 | case AArch64::CMGEv1i64: |
| 8841 | case AArch64::CMGEv2i32: |
| 8842 | case AArch64::CMGEv2i64: |
| 8843 | case AArch64::CMGEv4i16: |
| 8844 | case AArch64::CMGEv4i32: |
| 8845 | case AArch64::CMGEv8i16: |
| 8846 | case AArch64::CMGEv8i8: |
| 8847 | case AArch64::CMGTv16i8: |
| 8848 | case AArch64::CMGTv1i64: |
| 8849 | case AArch64::CMGTv2i32: |
| 8850 | case AArch64::CMGTv2i64: |
| 8851 | case AArch64::CMGTv4i16: |
| 8852 | case AArch64::CMGTv4i32: |
| 8853 | case AArch64::CMGTv8i16: |
| 8854 | case AArch64::CMGTv8i8: |
| 8855 | case AArch64::CMHIv16i8: |
| 8856 | case AArch64::CMHIv1i64: |
| 8857 | case AArch64::CMHIv2i32: |
| 8858 | case AArch64::CMHIv2i64: |
| 8859 | case AArch64::CMHIv4i16: |
| 8860 | case AArch64::CMHIv4i32: |
| 8861 | case AArch64::CMHIv8i16: |
| 8862 | case AArch64::CMHIv8i8: |
| 8863 | case AArch64::CMHSv16i8: |
| 8864 | case AArch64::CMHSv1i64: |
| 8865 | case AArch64::CMHSv2i32: |
| 8866 | case AArch64::CMHSv2i64: |
| 8867 | case AArch64::CMHSv4i16: |
| 8868 | case AArch64::CMHSv4i32: |
| 8869 | case AArch64::CMHSv8i16: |
| 8870 | case AArch64::CMHSv8i8: |
| 8871 | case AArch64::CMTSTv16i8: |
| 8872 | case AArch64::CMTSTv1i64: |
| 8873 | case AArch64::CMTSTv2i32: |
| 8874 | case AArch64::CMTSTv2i64: |
| 8875 | case AArch64::CMTSTv4i16: |
| 8876 | case AArch64::CMTSTv4i32: |
| 8877 | case AArch64::CMTSTv8i16: |
| 8878 | case AArch64::CMTSTv8i8: |
| 8879 | case AArch64::CRC32Brr: |
| 8880 | case AArch64::CRC32CBrr: |
| 8881 | case AArch64::CRC32CHrr: |
| 8882 | case AArch64::CRC32CWrr: |
| 8883 | case AArch64::CRC32CXrr: |
| 8884 | case AArch64::CRC32Hrr: |
| 8885 | case AArch64::CRC32Wrr: |
| 8886 | case AArch64::CRC32Xrr: |
| 8887 | case AArch64::EORv16i8: |
| 8888 | case AArch64::EORv8i8: |
| 8889 | case AArch64::FABD16: |
| 8890 | case AArch64::FABD32: |
| 8891 | case AArch64::FABD64: |
| 8892 | case AArch64::FABDv2f32: |
| 8893 | case AArch64::FABDv2f64: |
| 8894 | case AArch64::FABDv4f16: |
| 8895 | case AArch64::FABDv4f32: |
| 8896 | case AArch64::FABDv8f16: |
| 8897 | case AArch64::FACGE16: |
| 8898 | case AArch64::FACGE32: |
| 8899 | case AArch64::FACGE64: |
| 8900 | case AArch64::FACGEv2f32: |
| 8901 | case AArch64::FACGEv2f64: |
| 8902 | case AArch64::FACGEv4f16: |
| 8903 | case AArch64::FACGEv4f32: |
| 8904 | case AArch64::FACGEv8f16: |
| 8905 | case AArch64::FACGT16: |
| 8906 | case AArch64::FACGT32: |
| 8907 | case AArch64::FACGT64: |
| 8908 | case AArch64::FACGTv2f32: |
| 8909 | case AArch64::FACGTv2f64: |
| 8910 | case AArch64::FACGTv4f16: |
| 8911 | case AArch64::FACGTv4f32: |
| 8912 | case AArch64::FACGTv8f16: |
| 8913 | case AArch64::FADDDrr: |
| 8914 | case AArch64::FADDHrr: |
| 8915 | case AArch64::FADDPv2f32: |
| 8916 | case AArch64::FADDPv2f64: |
| 8917 | case AArch64::FADDPv4f16: |
| 8918 | case AArch64::FADDPv4f32: |
| 8919 | case AArch64::FADDPv8f16: |
| 8920 | case AArch64::FADDSrr: |
| 8921 | case AArch64::FADDv2f32: |
| 8922 | case AArch64::FADDv2f64: |
| 8923 | case AArch64::FADDv4f16: |
| 8924 | case AArch64::FADDv4f32: |
| 8925 | case AArch64::FADDv8f16: |
| 8926 | case AArch64::FCMEQ16: |
| 8927 | case AArch64::FCMEQ32: |
| 8928 | case AArch64::FCMEQ64: |
| 8929 | case AArch64::FCMEQv2f32: |
| 8930 | case AArch64::FCMEQv2f64: |
| 8931 | case AArch64::FCMEQv4f16: |
| 8932 | case AArch64::FCMEQv4f32: |
| 8933 | case AArch64::FCMEQv8f16: |
| 8934 | case AArch64::FCMGE16: |
| 8935 | case AArch64::FCMGE32: |
| 8936 | case AArch64::FCMGE64: |
| 8937 | case AArch64::FCMGEv2f32: |
| 8938 | case AArch64::FCMGEv2f64: |
| 8939 | case AArch64::FCMGEv4f16: |
| 8940 | case AArch64::FCMGEv4f32: |
| 8941 | case AArch64::FCMGEv8f16: |
| 8942 | case AArch64::FCMGT16: |
| 8943 | case AArch64::FCMGT32: |
| 8944 | case AArch64::FCMGT64: |
| 8945 | case AArch64::FCMGTv2f32: |
| 8946 | case AArch64::FCMGTv2f64: |
| 8947 | case AArch64::FCMGTv4f16: |
| 8948 | case AArch64::FCMGTv4f32: |
| 8949 | case AArch64::FCMGTv8f16: |
| 8950 | case AArch64::FDIVDrr: |
| 8951 | case AArch64::FDIVHrr: |
| 8952 | case AArch64::FDIVSrr: |
| 8953 | case AArch64::FDIVv2f32: |
| 8954 | case AArch64::FDIVv2f64: |
| 8955 | case AArch64::FDIVv4f16: |
| 8956 | case AArch64::FDIVv4f32: |
| 8957 | case AArch64::FDIVv8f16: |
| 8958 | case AArch64::FMAXDrr: |
| 8959 | case AArch64::FMAXHrr: |
| 8960 | case AArch64::FMAXNMDrr: |
| 8961 | case AArch64::FMAXNMHrr: |
| 8962 | case AArch64::FMAXNMPv2f32: |
| 8963 | case AArch64::FMAXNMPv2f64: |
| 8964 | case AArch64::FMAXNMPv4f16: |
| 8965 | case AArch64::FMAXNMPv4f32: |
| 8966 | case AArch64::FMAXNMPv8f16: |
| 8967 | case AArch64::FMAXNMSrr: |
| 8968 | case AArch64::FMAXNMv2f32: |
| 8969 | case AArch64::FMAXNMv2f64: |
| 8970 | case AArch64::FMAXNMv4f16: |
| 8971 | case AArch64::FMAXNMv4f32: |
| 8972 | case AArch64::FMAXNMv8f16: |
| 8973 | case AArch64::FMAXPv2f32: |
| 8974 | case AArch64::FMAXPv2f64: |
| 8975 | case AArch64::FMAXPv4f16: |
| 8976 | case AArch64::FMAXPv4f32: |
| 8977 | case AArch64::FMAXPv8f16: |
| 8978 | case AArch64::FMAXSrr: |
| 8979 | case AArch64::FMAXv2f32: |
| 8980 | case AArch64::FMAXv2f64: |
| 8981 | case AArch64::FMAXv4f16: |
| 8982 | case AArch64::FMAXv4f32: |
| 8983 | case AArch64::FMAXv8f16: |
| 8984 | case AArch64::FMINDrr: |
| 8985 | case AArch64::FMINHrr: |
| 8986 | case AArch64::FMINNMDrr: |
| 8987 | case AArch64::FMINNMHrr: |
| 8988 | case AArch64::FMINNMPv2f32: |
| 8989 | case AArch64::FMINNMPv2f64: |
| 8990 | case AArch64::FMINNMPv4f16: |
| 8991 | case AArch64::FMINNMPv4f32: |
| 8992 | case AArch64::FMINNMPv8f16: |
| 8993 | case AArch64::FMINNMSrr: |
| 8994 | case AArch64::FMINNMv2f32: |
| 8995 | case AArch64::FMINNMv2f64: |
| 8996 | case AArch64::FMINNMv4f16: |
| 8997 | case AArch64::FMINNMv4f32: |
| 8998 | case AArch64::FMINNMv8f16: |
| 8999 | case AArch64::FMINPv2f32: |
| 9000 | case AArch64::FMINPv2f64: |
| 9001 | case AArch64::FMINPv4f16: |
| 9002 | case AArch64::FMINPv4f32: |
| 9003 | case AArch64::FMINPv8f16: |
| 9004 | case AArch64::FMINSrr: |
| 9005 | case AArch64::FMINv2f32: |
| 9006 | case AArch64::FMINv2f64: |
| 9007 | case AArch64::FMINv4f16: |
| 9008 | case AArch64::FMINv4f32: |
| 9009 | case AArch64::FMINv8f16: |
| 9010 | case AArch64::FMULDrr: |
| 9011 | case AArch64::FMULHrr: |
| 9012 | case AArch64::FMULSrr: |
| 9013 | case AArch64::FMULX16: |
| 9014 | case AArch64::FMULX32: |
| 9015 | case AArch64::FMULX64: |
| 9016 | case AArch64::FMULXv2f32: |
| 9017 | case AArch64::FMULXv2f64: |
| 9018 | case AArch64::FMULXv4f16: |
| 9019 | case AArch64::FMULXv4f32: |
| 9020 | case AArch64::FMULXv8f16: |
| 9021 | case AArch64::FMULv2f32: |
| 9022 | case AArch64::FMULv2f64: |
| 9023 | case AArch64::FMULv4f16: |
| 9024 | case AArch64::FMULv4f32: |
| 9025 | case AArch64::FMULv8f16: |
| 9026 | case AArch64::FNMULDrr: |
| 9027 | case AArch64::FNMULHrr: |
| 9028 | case AArch64::FNMULSrr: |
| 9029 | case AArch64::FRECPS16: |
| 9030 | case AArch64::FRECPS32: |
| 9031 | case AArch64::FRECPS64: |
| 9032 | case AArch64::FRECPSv2f32: |
| 9033 | case AArch64::FRECPSv2f64: |
| 9034 | case AArch64::FRECPSv4f16: |
| 9035 | case AArch64::FRECPSv4f32: |
| 9036 | case AArch64::FRECPSv8f16: |
| 9037 | case AArch64::FRSQRTS16: |
| 9038 | case AArch64::FRSQRTS32: |
| 9039 | case AArch64::FRSQRTS64: |
| 9040 | case AArch64::FRSQRTSv2f32: |
| 9041 | case AArch64::FRSQRTSv2f64: |
| 9042 | case AArch64::FRSQRTSv4f16: |
| 9043 | case AArch64::FRSQRTSv4f32: |
| 9044 | case AArch64::FRSQRTSv8f16: |
| 9045 | case AArch64::FSUBDrr: |
| 9046 | case AArch64::FSUBHrr: |
| 9047 | case AArch64::FSUBSrr: |
| 9048 | case AArch64::FSUBv2f32: |
| 9049 | case AArch64::FSUBv2f64: |
| 9050 | case AArch64::FSUBv4f16: |
| 9051 | case AArch64::FSUBv4f32: |
| 9052 | case AArch64::FSUBv8f16: |
| 9053 | case AArch64::GMI: |
| 9054 | case AArch64::IRG: |
| 9055 | case AArch64::LSLVWr: |
| 9056 | case AArch64::LSLVXr: |
| 9057 | case AArch64::LSRVWr: |
| 9058 | case AArch64::LSRVXr: |
| 9059 | case AArch64::MULv16i8: |
| 9060 | case AArch64::MULv2i32: |
| 9061 | case AArch64::MULv4i16: |
| 9062 | case AArch64::MULv4i32: |
| 9063 | case AArch64::MULv8i16: |
| 9064 | case AArch64::MULv8i8: |
| 9065 | case AArch64::ORNv16i8: |
| 9066 | case AArch64::ORNv8i8: |
| 9067 | case AArch64::ORRv16i8: |
| 9068 | case AArch64::ORRv8i8: |
| 9069 | case AArch64::PACGA: |
| 9070 | case AArch64::PMULLv16i8: |
| 9071 | case AArch64::PMULLv1i64: |
| 9072 | case AArch64::PMULLv2i64: |
| 9073 | case AArch64::PMULLv8i8: |
| 9074 | case AArch64::PMULv16i8: |
| 9075 | case AArch64::PMULv8i8: |
| 9076 | case AArch64::RADDHNv2i64_v2i32: |
| 9077 | case AArch64::RADDHNv4i32_v4i16: |
| 9078 | case AArch64::RADDHNv8i16_v8i8: |
| 9079 | case AArch64::RORVWr: |
| 9080 | case AArch64::RORVXr: |
| 9081 | case AArch64::RSUBHNv2i64_v2i32: |
| 9082 | case AArch64::RSUBHNv4i32_v4i16: |
| 9083 | case AArch64::RSUBHNv8i16_v8i8: |
| 9084 | case AArch64::SABDLv16i8_v8i16: |
| 9085 | case AArch64::SABDLv2i32_v2i64: |
| 9086 | case AArch64::SABDLv4i16_v4i32: |
| 9087 | case AArch64::SABDLv4i32_v2i64: |
| 9088 | case AArch64::SABDLv8i16_v4i32: |
| 9089 | case AArch64::SABDLv8i8_v8i16: |
| 9090 | case AArch64::SABDv16i8: |
| 9091 | case AArch64::SABDv2i32: |
| 9092 | case AArch64::SABDv4i16: |
| 9093 | case AArch64::SABDv4i32: |
| 9094 | case AArch64::SABDv8i16: |
| 9095 | case AArch64::SABDv8i8: |
| 9096 | case AArch64::SADDLv16i8_v8i16: |
| 9097 | case AArch64::SADDLv2i32_v2i64: |
| 9098 | case AArch64::SADDLv4i16_v4i32: |
| 9099 | case AArch64::SADDLv4i32_v2i64: |
| 9100 | case AArch64::SADDLv8i16_v4i32: |
| 9101 | case AArch64::SADDLv8i8_v8i16: |
| 9102 | case AArch64::SADDWv16i8_v8i16: |
| 9103 | case AArch64::SADDWv2i32_v2i64: |
| 9104 | case AArch64::SADDWv4i16_v4i32: |
| 9105 | case AArch64::SADDWv4i32_v2i64: |
| 9106 | case AArch64::SADDWv8i16_v4i32: |
| 9107 | case AArch64::SADDWv8i8_v8i16: |
| 9108 | case AArch64::SBCSWr: |
| 9109 | case AArch64::SBCSXr: |
| 9110 | case AArch64::SBCWr: |
| 9111 | case AArch64::SBCXr: |
| 9112 | case AArch64::SDIVWr: |
| 9113 | case AArch64::SDIVXr: |
| 9114 | case AArch64::SHADDv16i8: |
| 9115 | case AArch64::SHADDv2i32: |
| 9116 | case AArch64::SHADDv4i16: |
| 9117 | case AArch64::SHADDv4i32: |
| 9118 | case AArch64::SHADDv8i16: |
| 9119 | case AArch64::SHADDv8i8: |
| 9120 | case AArch64::SHSUBv16i8: |
| 9121 | case AArch64::SHSUBv2i32: |
| 9122 | case AArch64::SHSUBv4i16: |
| 9123 | case AArch64::SHSUBv4i32: |
| 9124 | case AArch64::SHSUBv8i16: |
| 9125 | case AArch64::SHSUBv8i8: |
| 9126 | case AArch64::SMAXPv16i8: |
| 9127 | case AArch64::SMAXPv2i32: |
| 9128 | case AArch64::SMAXPv4i16: |
| 9129 | case AArch64::SMAXPv4i32: |
| 9130 | case AArch64::SMAXPv8i16: |
| 9131 | case AArch64::SMAXPv8i8: |
| 9132 | case AArch64::SMAXv16i8: |
| 9133 | case AArch64::SMAXv2i32: |
| 9134 | case AArch64::SMAXv4i16: |
| 9135 | case AArch64::SMAXv4i32: |
| 9136 | case AArch64::SMAXv8i16: |
| 9137 | case AArch64::SMAXv8i8: |
| 9138 | case AArch64::SMINPv16i8: |
| 9139 | case AArch64::SMINPv2i32: |
| 9140 | case AArch64::SMINPv4i16: |
| 9141 | case AArch64::SMINPv4i32: |
| 9142 | case AArch64::SMINPv8i16: |
| 9143 | case AArch64::SMINPv8i8: |
| 9144 | case AArch64::SMINv16i8: |
| 9145 | case AArch64::SMINv2i32: |
| 9146 | case AArch64::SMINv4i16: |
| 9147 | case AArch64::SMINv4i32: |
| 9148 | case AArch64::SMINv8i16: |
| 9149 | case AArch64::SMINv8i8: |
| 9150 | case AArch64::SMULLv16i8_v8i16: |
| 9151 | case AArch64::SMULLv2i32_v2i64: |
| 9152 | case AArch64::SMULLv4i16_v4i32: |
| 9153 | case AArch64::SMULLv4i32_v2i64: |
| 9154 | case AArch64::SMULLv8i16_v4i32: |
| 9155 | case AArch64::SMULLv8i8_v8i16: |
| 9156 | case AArch64::SQADDv16i8: |
| 9157 | case AArch64::SQADDv1i16: |
| 9158 | case AArch64::SQADDv1i32: |
| 9159 | case AArch64::SQADDv1i64: |
| 9160 | case AArch64::SQADDv1i8: |
| 9161 | case AArch64::SQADDv2i32: |
| 9162 | case AArch64::SQADDv2i64: |
| 9163 | case AArch64::SQADDv4i16: |
| 9164 | case AArch64::SQADDv4i32: |
| 9165 | case AArch64::SQADDv8i16: |
| 9166 | case AArch64::SQADDv8i8: |
| 9167 | case AArch64::SQDMULHv1i16: |
| 9168 | case AArch64::SQDMULHv1i32: |
| 9169 | case AArch64::SQDMULHv2i32: |
| 9170 | case AArch64::SQDMULHv4i16: |
| 9171 | case AArch64::SQDMULHv4i32: |
| 9172 | case AArch64::SQDMULHv8i16: |
| 9173 | case AArch64::SQDMULLi16: |
| 9174 | case AArch64::SQDMULLi32: |
| 9175 | case AArch64::SQDMULLv2i32_v2i64: |
| 9176 | case AArch64::SQDMULLv4i16_v4i32: |
| 9177 | case AArch64::SQDMULLv4i32_v2i64: |
| 9178 | case AArch64::SQDMULLv8i16_v4i32: |
| 9179 | case AArch64::SQRDMULHv1i16: |
| 9180 | case AArch64::SQRDMULHv1i32: |
| 9181 | case AArch64::SQRDMULHv2i32: |
| 9182 | case AArch64::SQRDMULHv4i16: |
| 9183 | case AArch64::SQRDMULHv4i32: |
| 9184 | case AArch64::SQRDMULHv8i16: |
| 9185 | case AArch64::SQRSHLv16i8: |
| 9186 | case AArch64::SQRSHLv1i16: |
| 9187 | case AArch64::SQRSHLv1i32: |
| 9188 | case AArch64::SQRSHLv1i64: |
| 9189 | case AArch64::SQRSHLv1i8: |
| 9190 | case AArch64::SQRSHLv2i32: |
| 9191 | case AArch64::SQRSHLv2i64: |
| 9192 | case AArch64::SQRSHLv4i16: |
| 9193 | case AArch64::SQRSHLv4i32: |
| 9194 | case AArch64::SQRSHLv8i16: |
| 9195 | case AArch64::SQRSHLv8i8: |
| 9196 | case AArch64::SQSHLv16i8: |
| 9197 | case AArch64::SQSHLv1i16: |
| 9198 | case AArch64::SQSHLv1i32: |
| 9199 | case AArch64::SQSHLv1i64: |
| 9200 | case AArch64::SQSHLv1i8: |
| 9201 | case AArch64::SQSHLv2i32: |
| 9202 | case AArch64::SQSHLv2i64: |
| 9203 | case AArch64::SQSHLv4i16: |
| 9204 | case AArch64::SQSHLv4i32: |
| 9205 | case AArch64::SQSHLv8i16: |
| 9206 | case AArch64::SQSHLv8i8: |
| 9207 | case AArch64::SQSUBv16i8: |
| 9208 | case AArch64::SQSUBv1i16: |
| 9209 | case AArch64::SQSUBv1i32: |
| 9210 | case AArch64::SQSUBv1i64: |
| 9211 | case AArch64::SQSUBv1i8: |
| 9212 | case AArch64::SQSUBv2i32: |
| 9213 | case AArch64::SQSUBv2i64: |
| 9214 | case AArch64::SQSUBv4i16: |
| 9215 | case AArch64::SQSUBv4i32: |
| 9216 | case AArch64::SQSUBv8i16: |
| 9217 | case AArch64::SQSUBv8i8: |
| 9218 | case AArch64::SRHADDv16i8: |
| 9219 | case AArch64::SRHADDv2i32: |
| 9220 | case AArch64::SRHADDv4i16: |
| 9221 | case AArch64::SRHADDv4i32: |
| 9222 | case AArch64::SRHADDv8i16: |
| 9223 | case AArch64::SRHADDv8i8: |
| 9224 | case AArch64::SRSHLv16i8: |
| 9225 | case AArch64::SRSHLv1i64: |
| 9226 | case AArch64::SRSHLv2i32: |
| 9227 | case AArch64::SRSHLv2i64: |
| 9228 | case AArch64::SRSHLv4i16: |
| 9229 | case AArch64::SRSHLv4i32: |
| 9230 | case AArch64::SRSHLv8i16: |
| 9231 | case AArch64::SRSHLv8i8: |
| 9232 | case AArch64::SSHLv16i8: |
| 9233 | case AArch64::SSHLv1i64: |
| 9234 | case AArch64::SSHLv2i32: |
| 9235 | case AArch64::SSHLv2i64: |
| 9236 | case AArch64::SSHLv4i16: |
| 9237 | case AArch64::SSHLv4i32: |
| 9238 | case AArch64::SSHLv8i16: |
| 9239 | case AArch64::SSHLv8i8: |
| 9240 | case AArch64::SSUBLv16i8_v8i16: |
| 9241 | case AArch64::SSUBLv2i32_v2i64: |
| 9242 | case AArch64::SSUBLv4i16_v4i32: |
| 9243 | case AArch64::SSUBLv4i32_v2i64: |
| 9244 | case AArch64::SSUBLv8i16_v4i32: |
| 9245 | case AArch64::SSUBLv8i8_v8i16: |
| 9246 | case AArch64::SSUBWv16i8_v8i16: |
| 9247 | case AArch64::SSUBWv2i32_v2i64: |
| 9248 | case AArch64::SSUBWv4i16_v4i32: |
| 9249 | case AArch64::SSUBWv4i32_v2i64: |
| 9250 | case AArch64::SSUBWv8i16_v4i32: |
| 9251 | case AArch64::SSUBWv8i8_v8i16: |
| 9252 | case AArch64::SUBHNv2i64_v2i32: |
| 9253 | case AArch64::SUBHNv4i32_v4i16: |
| 9254 | case AArch64::SUBHNv8i16_v8i8: |
| 9255 | case AArch64::SUBP: |
| 9256 | case AArch64::SUBPS: |
| 9257 | case AArch64::SUBv16i8: |
| 9258 | case AArch64::SUBv1i64: |
| 9259 | case AArch64::SUBv2i32: |
| 9260 | case AArch64::SUBv2i64: |
| 9261 | case AArch64::SUBv4i16: |
| 9262 | case AArch64::SUBv4i32: |
| 9263 | case AArch64::SUBv8i16: |
| 9264 | case AArch64::SUBv8i8: |
| 9265 | case AArch64::TRN1v16i8: |
| 9266 | case AArch64::TRN1v2i32: |
| 9267 | case AArch64::TRN1v2i64: |
| 9268 | case AArch64::TRN1v4i16: |
| 9269 | case AArch64::TRN1v4i32: |
| 9270 | case AArch64::TRN1v8i16: |
| 9271 | case AArch64::TRN1v8i8: |
| 9272 | case AArch64::TRN2v16i8: |
| 9273 | case AArch64::TRN2v2i32: |
| 9274 | case AArch64::TRN2v2i64: |
| 9275 | case AArch64::TRN2v4i16: |
| 9276 | case AArch64::TRN2v4i32: |
| 9277 | case AArch64::TRN2v8i16: |
| 9278 | case AArch64::TRN2v8i8: |
| 9279 | case AArch64::UABDLv16i8_v8i16: |
| 9280 | case AArch64::UABDLv2i32_v2i64: |
| 9281 | case AArch64::UABDLv4i16_v4i32: |
| 9282 | case AArch64::UABDLv4i32_v2i64: |
| 9283 | case AArch64::UABDLv8i16_v4i32: |
| 9284 | case AArch64::UABDLv8i8_v8i16: |
| 9285 | case AArch64::UABDv16i8: |
| 9286 | case AArch64::UABDv2i32: |
| 9287 | case AArch64::UABDv4i16: |
| 9288 | case AArch64::UABDv4i32: |
| 9289 | case AArch64::UABDv8i16: |
| 9290 | case AArch64::UABDv8i8: |
| 9291 | case AArch64::UADDLv16i8_v8i16: |
| 9292 | case AArch64::UADDLv2i32_v2i64: |
| 9293 | case AArch64::UADDLv4i16_v4i32: |
| 9294 | case AArch64::UADDLv4i32_v2i64: |
| 9295 | case AArch64::UADDLv8i16_v4i32: |
| 9296 | case AArch64::UADDLv8i8_v8i16: |
| 9297 | case AArch64::UADDWv16i8_v8i16: |
| 9298 | case AArch64::UADDWv2i32_v2i64: |
| 9299 | case AArch64::UADDWv4i16_v4i32: |
| 9300 | case AArch64::UADDWv4i32_v2i64: |
| 9301 | case AArch64::UADDWv8i16_v4i32: |
| 9302 | case AArch64::UADDWv8i8_v8i16: |
| 9303 | case AArch64::UDIVWr: |
| 9304 | case AArch64::UDIVXr: |
| 9305 | case AArch64::UHADDv16i8: |
| 9306 | case AArch64::UHADDv2i32: |
| 9307 | case AArch64::UHADDv4i16: |
| 9308 | case AArch64::UHADDv4i32: |
| 9309 | case AArch64::UHADDv8i16: |
| 9310 | case AArch64::UHADDv8i8: |
| 9311 | case AArch64::UHSUBv16i8: |
| 9312 | case AArch64::UHSUBv2i32: |
| 9313 | case AArch64::UHSUBv4i16: |
| 9314 | case AArch64::UHSUBv4i32: |
| 9315 | case AArch64::UHSUBv8i16: |
| 9316 | case AArch64::UHSUBv8i8: |
| 9317 | case AArch64::UMAXPv16i8: |
| 9318 | case AArch64::UMAXPv2i32: |
| 9319 | case AArch64::UMAXPv4i16: |
| 9320 | case AArch64::UMAXPv4i32: |
| 9321 | case AArch64::UMAXPv8i16: |
| 9322 | case AArch64::UMAXPv8i8: |
| 9323 | case AArch64::UMAXv16i8: |
| 9324 | case AArch64::UMAXv2i32: |
| 9325 | case AArch64::UMAXv4i16: |
| 9326 | case AArch64::UMAXv4i32: |
| 9327 | case AArch64::UMAXv8i16: |
| 9328 | case AArch64::UMAXv8i8: |
| 9329 | case AArch64::UMINPv16i8: |
| 9330 | case AArch64::UMINPv2i32: |
| 9331 | case AArch64::UMINPv4i16: |
| 9332 | case AArch64::UMINPv4i32: |
| 9333 | case AArch64::UMINPv8i16: |
| 9334 | case AArch64::UMINPv8i8: |
| 9335 | case AArch64::UMINv16i8: |
| 9336 | case AArch64::UMINv2i32: |
| 9337 | case AArch64::UMINv4i16: |
| 9338 | case AArch64::UMINv4i32: |
| 9339 | case AArch64::UMINv8i16: |
| 9340 | case AArch64::UMINv8i8: |
| 9341 | case AArch64::UMULLv16i8_v8i16: |
| 9342 | case AArch64::UMULLv2i32_v2i64: |
| 9343 | case AArch64::UMULLv4i16_v4i32: |
| 9344 | case AArch64::UMULLv4i32_v2i64: |
| 9345 | case AArch64::UMULLv8i16_v4i32: |
| 9346 | case AArch64::UMULLv8i8_v8i16: |
| 9347 | case AArch64::UQADDv16i8: |
| 9348 | case AArch64::UQADDv1i16: |
| 9349 | case AArch64::UQADDv1i32: |
| 9350 | case AArch64::UQADDv1i64: |
| 9351 | case AArch64::UQADDv1i8: |
| 9352 | case AArch64::UQADDv2i32: |
| 9353 | case AArch64::UQADDv2i64: |
| 9354 | case AArch64::UQADDv4i16: |
| 9355 | case AArch64::UQADDv4i32: |
| 9356 | case AArch64::UQADDv8i16: |
| 9357 | case AArch64::UQADDv8i8: |
| 9358 | case AArch64::UQRSHLv16i8: |
| 9359 | case AArch64::UQRSHLv1i16: |
| 9360 | case AArch64::UQRSHLv1i32: |
| 9361 | case AArch64::UQRSHLv1i64: |
| 9362 | case AArch64::UQRSHLv1i8: |
| 9363 | case AArch64::UQRSHLv2i32: |
| 9364 | case AArch64::UQRSHLv2i64: |
| 9365 | case AArch64::UQRSHLv4i16: |
| 9366 | case AArch64::UQRSHLv4i32: |
| 9367 | case AArch64::UQRSHLv8i16: |
| 9368 | case AArch64::UQRSHLv8i8: |
| 9369 | case AArch64::UQSHLv16i8: |
| 9370 | case AArch64::UQSHLv1i16: |
| 9371 | case AArch64::UQSHLv1i32: |
| 9372 | case AArch64::UQSHLv1i64: |
| 9373 | case AArch64::UQSHLv1i8: |
| 9374 | case AArch64::UQSHLv2i32: |
| 9375 | case AArch64::UQSHLv2i64: |
| 9376 | case AArch64::UQSHLv4i16: |
| 9377 | case AArch64::UQSHLv4i32: |
| 9378 | case AArch64::UQSHLv8i16: |
| 9379 | case AArch64::UQSHLv8i8: |
| 9380 | case AArch64::UQSUBv16i8: |
| 9381 | case AArch64::UQSUBv1i16: |
| 9382 | case AArch64::UQSUBv1i32: |
| 9383 | case AArch64::UQSUBv1i64: |
| 9384 | case AArch64::UQSUBv1i8: |
| 9385 | case AArch64::UQSUBv2i32: |
| 9386 | case AArch64::UQSUBv2i64: |
| 9387 | case AArch64::UQSUBv4i16: |
| 9388 | case AArch64::UQSUBv4i32: |
| 9389 | case AArch64::UQSUBv8i16: |
| 9390 | case AArch64::UQSUBv8i8: |
| 9391 | case AArch64::URHADDv16i8: |
| 9392 | case AArch64::URHADDv2i32: |
| 9393 | case AArch64::URHADDv4i16: |
| 9394 | case AArch64::URHADDv4i32: |
| 9395 | case AArch64::URHADDv8i16: |
| 9396 | case AArch64::URHADDv8i8: |
| 9397 | case AArch64::URSHLv16i8: |
| 9398 | case AArch64::URSHLv1i64: |
| 9399 | case AArch64::URSHLv2i32: |
| 9400 | case AArch64::URSHLv2i64: |
| 9401 | case AArch64::URSHLv4i16: |
| 9402 | case AArch64::URSHLv4i32: |
| 9403 | case AArch64::URSHLv8i16: |
| 9404 | case AArch64::URSHLv8i8: |
| 9405 | case AArch64::USHLv16i8: |
| 9406 | case AArch64::USHLv1i64: |
| 9407 | case AArch64::USHLv2i32: |
| 9408 | case AArch64::USHLv2i64: |
| 9409 | case AArch64::USHLv4i16: |
| 9410 | case AArch64::USHLv4i32: |
| 9411 | case AArch64::USHLv8i16: |
| 9412 | case AArch64::USHLv8i8: |
| 9413 | case AArch64::USUBLv16i8_v8i16: |
| 9414 | case AArch64::USUBLv2i32_v2i64: |
| 9415 | case AArch64::USUBLv4i16_v4i32: |
| 9416 | case AArch64::USUBLv4i32_v2i64: |
| 9417 | case AArch64::USUBLv8i16_v4i32: |
| 9418 | case AArch64::USUBLv8i8_v8i16: |
| 9419 | case AArch64::USUBWv16i8_v8i16: |
| 9420 | case AArch64::USUBWv2i32_v2i64: |
| 9421 | case AArch64::USUBWv4i16_v4i32: |
| 9422 | case AArch64::USUBWv4i32_v2i64: |
| 9423 | case AArch64::USUBWv8i16_v4i32: |
| 9424 | case AArch64::USUBWv8i8_v8i16: |
| 9425 | case AArch64::UZP1v16i8: |
| 9426 | case AArch64::UZP1v2i32: |
| 9427 | case AArch64::UZP1v2i64: |
| 9428 | case AArch64::UZP1v4i16: |
| 9429 | case AArch64::UZP1v4i32: |
| 9430 | case AArch64::UZP1v8i16: |
| 9431 | case AArch64::UZP1v8i8: |
| 9432 | case AArch64::UZP2v16i8: |
| 9433 | case AArch64::UZP2v2i32: |
| 9434 | case AArch64::UZP2v2i64: |
| 9435 | case AArch64::UZP2v4i16: |
| 9436 | case AArch64::UZP2v4i32: |
| 9437 | case AArch64::UZP2v8i16: |
| 9438 | case AArch64::UZP2v8i8: |
| 9439 | case AArch64::ZIP1v16i8: |
| 9440 | case AArch64::ZIP1v2i32: |
| 9441 | case AArch64::ZIP1v2i64: |
| 9442 | case AArch64::ZIP1v4i16: |
| 9443 | case AArch64::ZIP1v4i32: |
| 9444 | case AArch64::ZIP1v8i16: |
| 9445 | case AArch64::ZIP1v8i8: |
| 9446 | case AArch64::ZIP2v16i8: |
| 9447 | case AArch64::ZIP2v2i32: |
| 9448 | case AArch64::ZIP2v2i64: |
| 9449 | case AArch64::ZIP2v4i16: |
| 9450 | case AArch64::ZIP2v4i32: |
| 9451 | case AArch64::ZIP2v8i16: |
| 9452 | case AArch64::ZIP2v8i8: { |
| 9453 | // op: Rd |
| 9454 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9455 | op &= UINT64_C(31); |
| 9456 | Value |= op; |
| 9457 | // op: Rn |
| 9458 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9459 | op &= UINT64_C(31); |
| 9460 | op <<= 5; |
| 9461 | Value |= op; |
| 9462 | // op: Rm |
| 9463 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9464 | op &= UINT64_C(31); |
| 9465 | op <<= 16; |
| 9466 | Value |= op; |
| 9467 | break; |
| 9468 | } |
| 9469 | case AArch64::FMADDDrrr: |
| 9470 | case AArch64::FMADDHrrr: |
| 9471 | case AArch64::FMADDSrrr: |
| 9472 | case AArch64::FMSUBDrrr: |
| 9473 | case AArch64::FMSUBHrrr: |
| 9474 | case AArch64::FMSUBSrrr: |
| 9475 | case AArch64::FNMADDDrrr: |
| 9476 | case AArch64::FNMADDHrrr: |
| 9477 | case AArch64::FNMADDSrrr: |
| 9478 | case AArch64::FNMSUBDrrr: |
| 9479 | case AArch64::FNMSUBHrrr: |
| 9480 | case AArch64::FNMSUBSrrr: |
| 9481 | case AArch64::MADDWrrr: |
| 9482 | case AArch64::MADDXrrr: |
| 9483 | case AArch64::MSUBWrrr: |
| 9484 | case AArch64::MSUBXrrr: |
| 9485 | case AArch64::SMADDLrrr: |
| 9486 | case AArch64::SMSUBLrrr: |
| 9487 | case AArch64::UMADDLrrr: |
| 9488 | case AArch64::UMSUBLrrr: { |
| 9489 | // op: Rd |
| 9490 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9491 | op &= UINT64_C(31); |
| 9492 | Value |= op; |
| 9493 | // op: Rn |
| 9494 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9495 | op &= UINT64_C(31); |
| 9496 | op <<= 5; |
| 9497 | Value |= op; |
| 9498 | // op: Rm |
| 9499 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9500 | op &= UINT64_C(31); |
| 9501 | op <<= 16; |
| 9502 | Value |= op; |
| 9503 | // op: Ra |
| 9504 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9505 | op &= UINT64_C(31); |
| 9506 | op <<= 10; |
| 9507 | Value |= op; |
| 9508 | break; |
| 9509 | } |
| 9510 | case AArch64::CSELWr: |
| 9511 | case AArch64::CSELXr: |
| 9512 | case AArch64::CSINCWr: |
| 9513 | case AArch64::CSINCXr: |
| 9514 | case AArch64::CSINVWr: |
| 9515 | case AArch64::CSINVXr: |
| 9516 | case AArch64::CSNEGWr: |
| 9517 | case AArch64::CSNEGXr: |
| 9518 | case AArch64::FCSELDrrr: |
| 9519 | case AArch64::FCSELHrrr: |
| 9520 | case AArch64::FCSELSrrr: { |
| 9521 | // op: Rd |
| 9522 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9523 | op &= UINT64_C(31); |
| 9524 | Value |= op; |
| 9525 | // op: Rn |
| 9526 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9527 | op &= UINT64_C(31); |
| 9528 | op <<= 5; |
| 9529 | Value |= op; |
| 9530 | // op: Rm |
| 9531 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9532 | op &= UINT64_C(31); |
| 9533 | op <<= 16; |
| 9534 | Value |= op; |
| 9535 | // op: cond |
| 9536 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9537 | op &= UINT64_C(15); |
| 9538 | op <<= 12; |
| 9539 | Value |= op; |
| 9540 | break; |
| 9541 | } |
| 9542 | case AArch64::ADDSXrx64: |
| 9543 | case AArch64::ADDXrx64: |
| 9544 | case AArch64::SUBSXrx64: |
| 9545 | case AArch64::SUBXrx64: { |
| 9546 | // op: Rd |
| 9547 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9548 | op &= UINT64_C(31); |
| 9549 | Value |= op; |
| 9550 | // op: Rn |
| 9551 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9552 | op &= UINT64_C(31); |
| 9553 | op <<= 5; |
| 9554 | Value |= op; |
| 9555 | // op: Rm |
| 9556 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9557 | op &= UINT64_C(31); |
| 9558 | op <<= 16; |
| 9559 | Value |= op; |
| 9560 | // op: ext |
| 9561 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9562 | Value |= (op & UINT64_C(32)) << 10; |
| 9563 | Value |= (op & UINT64_C(7)) << 10; |
| 9564 | break; |
| 9565 | } |
| 9566 | case AArch64::ADDSWrx: |
| 9567 | case AArch64::ADDSXrx: |
| 9568 | case AArch64::ADDWrx: |
| 9569 | case AArch64::ADDXrx: |
| 9570 | case AArch64::SUBSWrx: |
| 9571 | case AArch64::SUBSXrx: |
| 9572 | case AArch64::SUBWrx: |
| 9573 | case AArch64::SUBXrx: { |
| 9574 | // op: Rd |
| 9575 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9576 | op &= UINT64_C(31); |
| 9577 | Value |= op; |
| 9578 | // op: Rn |
| 9579 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9580 | op &= UINT64_C(31); |
| 9581 | op <<= 5; |
| 9582 | Value |= op; |
| 9583 | // op: Rm |
| 9584 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9585 | op &= UINT64_C(31); |
| 9586 | op <<= 16; |
| 9587 | Value |= op; |
| 9588 | // op: ext |
| 9589 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9590 | op &= UINT64_C(63); |
| 9591 | op <<= 10; |
| 9592 | Value |= op; |
| 9593 | break; |
| 9594 | } |
| 9595 | case AArch64::FMULXv1i32_indexed: |
| 9596 | case AArch64::FMULXv2i32_indexed: |
| 9597 | case AArch64::FMULXv4i32_indexed: |
| 9598 | case AArch64::FMULv1i32_indexed: |
| 9599 | case AArch64::FMULv2i32_indexed: |
| 9600 | case AArch64::FMULv4i32_indexed: |
| 9601 | case AArch64::MULv2i32_indexed: |
| 9602 | case AArch64::MULv4i32_indexed: |
| 9603 | case AArch64::SMULLv2i32_indexed: |
| 9604 | case AArch64::SMULLv4i32_indexed: |
| 9605 | case AArch64::SQDMULHv1i32_indexed: |
| 9606 | case AArch64::SQDMULHv2i32_indexed: |
| 9607 | case AArch64::SQDMULHv4i32_indexed: |
| 9608 | case AArch64::SQDMULLv1i64_indexed: |
| 9609 | case AArch64::SQDMULLv2i32_indexed: |
| 9610 | case AArch64::SQDMULLv4i32_indexed: |
| 9611 | case AArch64::SQRDMULHv1i32_indexed: |
| 9612 | case AArch64::SQRDMULHv2i32_indexed: |
| 9613 | case AArch64::SQRDMULHv4i32_indexed: |
| 9614 | case AArch64::UMULLv2i32_indexed: |
| 9615 | case AArch64::UMULLv4i32_indexed: { |
| 9616 | // op: Rd |
| 9617 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9618 | op &= UINT64_C(31); |
| 9619 | Value |= op; |
| 9620 | // op: Rn |
| 9621 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9622 | op &= UINT64_C(31); |
| 9623 | op <<= 5; |
| 9624 | Value |= op; |
| 9625 | // op: Rm |
| 9626 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9627 | op &= UINT64_C(31); |
| 9628 | op <<= 16; |
| 9629 | Value |= op; |
| 9630 | // op: idx |
| 9631 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9632 | Value |= (op & UINT64_C(1)) << 21; |
| 9633 | Value |= (op & UINT64_C(2)) << 10; |
| 9634 | break; |
| 9635 | } |
| 9636 | case AArch64::FMULXv1i64_indexed: |
| 9637 | case AArch64::FMULXv2i64_indexed: |
| 9638 | case AArch64::FMULv1i64_indexed: |
| 9639 | case AArch64::FMULv2i64_indexed: { |
| 9640 | // op: Rd |
| 9641 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9642 | op &= UINT64_C(31); |
| 9643 | Value |= op; |
| 9644 | // op: Rn |
| 9645 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9646 | op &= UINT64_C(31); |
| 9647 | op <<= 5; |
| 9648 | Value |= op; |
| 9649 | // op: Rm |
| 9650 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9651 | op &= UINT64_C(31); |
| 9652 | op <<= 16; |
| 9653 | Value |= op; |
| 9654 | // op: idx |
| 9655 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9656 | op &= UINT64_C(1); |
| 9657 | op <<= 11; |
| 9658 | Value |= op; |
| 9659 | break; |
| 9660 | } |
| 9661 | case AArch64::EXTv16i8: { |
| 9662 | // op: Rd |
| 9663 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9664 | op &= UINT64_C(31); |
| 9665 | Value |= op; |
| 9666 | // op: Rn |
| 9667 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9668 | op &= UINT64_C(31); |
| 9669 | op <<= 5; |
| 9670 | Value |= op; |
| 9671 | // op: Rm |
| 9672 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9673 | op &= UINT64_C(31); |
| 9674 | op <<= 16; |
| 9675 | Value |= op; |
| 9676 | // op: imm |
| 9677 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9678 | op &= UINT64_C(15); |
| 9679 | op <<= 11; |
| 9680 | Value |= op; |
| 9681 | break; |
| 9682 | } |
| 9683 | case AArch64::EXTRWrri: { |
| 9684 | // op: Rd |
| 9685 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9686 | op &= UINT64_C(31); |
| 9687 | Value |= op; |
| 9688 | // op: Rn |
| 9689 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9690 | op &= UINT64_C(31); |
| 9691 | op <<= 5; |
| 9692 | Value |= op; |
| 9693 | // op: Rm |
| 9694 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9695 | op &= UINT64_C(31); |
| 9696 | op <<= 16; |
| 9697 | Value |= op; |
| 9698 | // op: imm |
| 9699 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9700 | op &= UINT64_C(31); |
| 9701 | op <<= 10; |
| 9702 | Value |= op; |
| 9703 | break; |
| 9704 | } |
| 9705 | case AArch64::EXTRXrri: { |
| 9706 | // op: Rd |
| 9707 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9708 | op &= UINT64_C(31); |
| 9709 | Value |= op; |
| 9710 | // op: Rn |
| 9711 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9712 | op &= UINT64_C(31); |
| 9713 | op <<= 5; |
| 9714 | Value |= op; |
| 9715 | // op: Rm |
| 9716 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9717 | op &= UINT64_C(31); |
| 9718 | op <<= 16; |
| 9719 | Value |= op; |
| 9720 | // op: imm |
| 9721 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9722 | op &= UINT64_C(63); |
| 9723 | op <<= 10; |
| 9724 | Value |= op; |
| 9725 | break; |
| 9726 | } |
| 9727 | case AArch64::EXTv8i8: { |
| 9728 | // op: Rd |
| 9729 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9730 | op &= UINT64_C(31); |
| 9731 | Value |= op; |
| 9732 | // op: Rn |
| 9733 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9734 | op &= UINT64_C(31); |
| 9735 | op <<= 5; |
| 9736 | Value |= op; |
| 9737 | // op: Rm |
| 9738 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9739 | op &= UINT64_C(31); |
| 9740 | op <<= 16; |
| 9741 | Value |= op; |
| 9742 | // op: imm |
| 9743 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9744 | op &= UINT64_C(7); |
| 9745 | op <<= 11; |
| 9746 | Value |= op; |
| 9747 | break; |
| 9748 | } |
| 9749 | case AArch64::FCADDv2f32: |
| 9750 | case AArch64::FCADDv2f64: |
| 9751 | case AArch64::FCADDv4f16: |
| 9752 | case AArch64::FCADDv4f32: |
| 9753 | case AArch64::FCADDv8f16: { |
| 9754 | // op: Rd |
| 9755 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9756 | op &= UINT64_C(31); |
| 9757 | Value |= op; |
| 9758 | // op: Rn |
| 9759 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9760 | op &= UINT64_C(31); |
| 9761 | op <<= 5; |
| 9762 | Value |= op; |
| 9763 | // op: Rm |
| 9764 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9765 | op &= UINT64_C(31); |
| 9766 | op <<= 16; |
| 9767 | Value |= op; |
| 9768 | // op: rot |
| 9769 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 9770 | op &= UINT64_C(1); |
| 9771 | op <<= 12; |
| 9772 | Value |= op; |
| 9773 | break; |
| 9774 | } |
| 9775 | case AArch64::SMULHrr: |
| 9776 | case AArch64::UMULHrr: { |
| 9777 | // op: Rd |
| 9778 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9779 | op &= UINT64_C(31); |
| 9780 | Value |= op; |
| 9781 | // op: Rn |
| 9782 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9783 | op &= UINT64_C(31); |
| 9784 | op <<= 5; |
| 9785 | Value |= op; |
| 9786 | // op: Rm |
| 9787 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9788 | op &= UINT64_C(31); |
| 9789 | op <<= 16; |
| 9790 | Value |= op; |
| 9791 | Value = fixMulHigh(MI, Value, STI); |
| 9792 | break; |
| 9793 | } |
| 9794 | case AArch64::DUPv2i64lane: |
| 9795 | case AArch64::UMOVvi64: { |
| 9796 | // op: Rd |
| 9797 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9798 | op &= UINT64_C(31); |
| 9799 | Value |= op; |
| 9800 | // op: Rn |
| 9801 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9802 | op &= UINT64_C(31); |
| 9803 | op <<= 5; |
| 9804 | Value |= op; |
| 9805 | // op: idx |
| 9806 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9807 | op &= UINT64_C(1); |
| 9808 | op <<= 20; |
| 9809 | Value |= op; |
| 9810 | break; |
| 9811 | } |
| 9812 | case AArch64::DUPv16i8lane: |
| 9813 | case AArch64::DUPv8i8lane: |
| 9814 | case AArch64::SMOVvi8to32: |
| 9815 | case AArch64::SMOVvi8to64: |
| 9816 | case AArch64::UMOVvi8: { |
| 9817 | // op: Rd |
| 9818 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9819 | op &= UINT64_C(31); |
| 9820 | Value |= op; |
| 9821 | // op: Rn |
| 9822 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9823 | op &= UINT64_C(31); |
| 9824 | op <<= 5; |
| 9825 | Value |= op; |
| 9826 | // op: idx |
| 9827 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9828 | op &= UINT64_C(15); |
| 9829 | op <<= 17; |
| 9830 | Value |= op; |
| 9831 | break; |
| 9832 | } |
| 9833 | case AArch64::DUPv2i32lane: |
| 9834 | case AArch64::DUPv4i32lane: |
| 9835 | case AArch64::SMOVvi32to64: |
| 9836 | case AArch64::UMOVvi32: { |
| 9837 | // op: Rd |
| 9838 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9839 | op &= UINT64_C(31); |
| 9840 | Value |= op; |
| 9841 | // op: Rn |
| 9842 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9843 | op &= UINT64_C(31); |
| 9844 | op <<= 5; |
| 9845 | Value |= op; |
| 9846 | // op: idx |
| 9847 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9848 | op &= UINT64_C(3); |
| 9849 | op <<= 19; |
| 9850 | Value |= op; |
| 9851 | break; |
| 9852 | } |
| 9853 | case AArch64::DUPv4i16lane: |
| 9854 | case AArch64::DUPv8i16lane: |
| 9855 | case AArch64::SMOVvi16to32: |
| 9856 | case AArch64::SMOVvi16to64: |
| 9857 | case AArch64::UMOVvi16: { |
| 9858 | // op: Rd |
| 9859 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9860 | op &= UINT64_C(31); |
| 9861 | Value |= op; |
| 9862 | // op: Rn |
| 9863 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9864 | op &= UINT64_C(31); |
| 9865 | op <<= 5; |
| 9866 | Value |= op; |
| 9867 | // op: idx |
| 9868 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9869 | op &= UINT64_C(7); |
| 9870 | op <<= 18; |
| 9871 | Value |= op; |
| 9872 | break; |
| 9873 | } |
| 9874 | case AArch64::ADDSWri: |
| 9875 | case AArch64::ADDSXri: |
| 9876 | case AArch64::ADDWri: |
| 9877 | case AArch64::ADDXri: |
| 9878 | case AArch64::SUBSWri: |
| 9879 | case AArch64::SUBSXri: |
| 9880 | case AArch64::SUBWri: |
| 9881 | case AArch64::SUBXri: { |
| 9882 | // op: Rd |
| 9883 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9884 | op &= UINT64_C(31); |
| 9885 | Value |= op; |
| 9886 | // op: Rn |
| 9887 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9888 | op &= UINT64_C(31); |
| 9889 | op <<= 5; |
| 9890 | Value |= op; |
| 9891 | // op: imm |
| 9892 | op = getAddSubImmOpValue(MI, 2, Fixups, STI); |
| 9893 | op &= UINT64_C(16383); |
| 9894 | op <<= 10; |
| 9895 | Value |= op; |
| 9896 | break; |
| 9897 | } |
| 9898 | case AArch64::ANDSWri: |
| 9899 | case AArch64::ANDWri: |
| 9900 | case AArch64::EORWri: |
| 9901 | case AArch64::ORRWri: { |
| 9902 | // op: Rd |
| 9903 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9904 | op &= UINT64_C(31); |
| 9905 | Value |= op; |
| 9906 | // op: Rn |
| 9907 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9908 | op &= UINT64_C(31); |
| 9909 | op <<= 5; |
| 9910 | Value |= op; |
| 9911 | // op: imm |
| 9912 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9913 | op &= UINT64_C(4095); |
| 9914 | op <<= 10; |
| 9915 | Value |= op; |
| 9916 | break; |
| 9917 | } |
| 9918 | case AArch64::ANDSXri: |
| 9919 | case AArch64::ANDXri: |
| 9920 | case AArch64::EORXri: |
| 9921 | case AArch64::ORRXri: { |
| 9922 | // op: Rd |
| 9923 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9924 | op &= UINT64_C(31); |
| 9925 | Value |= op; |
| 9926 | // op: Rn |
| 9927 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9928 | op &= UINT64_C(31); |
| 9929 | op <<= 5; |
| 9930 | Value |= op; |
| 9931 | // op: imm |
| 9932 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 9933 | op &= UINT64_C(8191); |
| 9934 | op <<= 10; |
| 9935 | Value |= op; |
| 9936 | break; |
| 9937 | } |
| 9938 | case AArch64::SHLv4i16_shift: |
| 9939 | case AArch64::SHLv8i16_shift: |
| 9940 | case AArch64::SQSHLUh: |
| 9941 | case AArch64::SQSHLUv4i16_shift: |
| 9942 | case AArch64::SQSHLUv8i16_shift: |
| 9943 | case AArch64::SQSHLh: |
| 9944 | case AArch64::SQSHLv4i16_shift: |
| 9945 | case AArch64::SQSHLv8i16_shift: |
| 9946 | case AArch64::SSHLLv4i16_shift: |
| 9947 | case AArch64::SSHLLv8i16_shift: |
| 9948 | case AArch64::UQSHLh: |
| 9949 | case AArch64::UQSHLv4i16_shift: |
| 9950 | case AArch64::UQSHLv8i16_shift: |
| 9951 | case AArch64::USHLLv4i16_shift: |
| 9952 | case AArch64::USHLLv8i16_shift: { |
| 9953 | // op: Rd |
| 9954 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9955 | op &= UINT64_C(31); |
| 9956 | Value |= op; |
| 9957 | // op: Rn |
| 9958 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9959 | op &= UINT64_C(31); |
| 9960 | op <<= 5; |
| 9961 | Value |= op; |
| 9962 | // op: imm |
| 9963 | op = getVecShiftL16OpValue(MI, 2, Fixups, STI); |
| 9964 | op &= UINT64_C(15); |
| 9965 | op <<= 16; |
| 9966 | Value |= op; |
| 9967 | break; |
| 9968 | } |
| 9969 | case AArch64::SHLv2i32_shift: |
| 9970 | case AArch64::SHLv4i32_shift: |
| 9971 | case AArch64::SQSHLUs: |
| 9972 | case AArch64::SQSHLUv2i32_shift: |
| 9973 | case AArch64::SQSHLUv4i32_shift: |
| 9974 | case AArch64::SQSHLs: |
| 9975 | case AArch64::SQSHLv2i32_shift: |
| 9976 | case AArch64::SQSHLv4i32_shift: |
| 9977 | case AArch64::SSHLLv2i32_shift: |
| 9978 | case AArch64::SSHLLv4i32_shift: |
| 9979 | case AArch64::UQSHLs: |
| 9980 | case AArch64::UQSHLv2i32_shift: |
| 9981 | case AArch64::UQSHLv4i32_shift: |
| 9982 | case AArch64::USHLLv2i32_shift: |
| 9983 | case AArch64::USHLLv4i32_shift: { |
| 9984 | // op: Rd |
| 9985 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 9986 | op &= UINT64_C(31); |
| 9987 | Value |= op; |
| 9988 | // op: Rn |
| 9989 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 9990 | op &= UINT64_C(31); |
| 9991 | op <<= 5; |
| 9992 | Value |= op; |
| 9993 | // op: imm |
| 9994 | op = getVecShiftL32OpValue(MI, 2, Fixups, STI); |
| 9995 | op &= UINT64_C(31); |
| 9996 | op <<= 16; |
| 9997 | Value |= op; |
| 9998 | break; |
| 9999 | } |
| 10000 | case AArch64::SHLd: |
| 10001 | case AArch64::SHLv2i64_shift: |
| 10002 | case AArch64::SQSHLUd: |
| 10003 | case AArch64::SQSHLUv2i64_shift: |
| 10004 | case AArch64::SQSHLd: |
| 10005 | case AArch64::SQSHLv2i64_shift: |
| 10006 | case AArch64::UQSHLd: |
| 10007 | case AArch64::UQSHLv2i64_shift: { |
| 10008 | // op: Rd |
| 10009 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10010 | op &= UINT64_C(31); |
| 10011 | Value |= op; |
| 10012 | // op: Rn |
| 10013 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10014 | op &= UINT64_C(31); |
| 10015 | op <<= 5; |
| 10016 | Value |= op; |
| 10017 | // op: imm |
| 10018 | op = getVecShiftL64OpValue(MI, 2, Fixups, STI); |
| 10019 | op &= UINT64_C(63); |
| 10020 | op <<= 16; |
| 10021 | Value |= op; |
| 10022 | break; |
| 10023 | } |
| 10024 | case AArch64::SHLv16i8_shift: |
| 10025 | case AArch64::SHLv8i8_shift: |
| 10026 | case AArch64::SQSHLUb: |
| 10027 | case AArch64::SQSHLUv16i8_shift: |
| 10028 | case AArch64::SQSHLUv8i8_shift: |
| 10029 | case AArch64::SQSHLb: |
| 10030 | case AArch64::SQSHLv16i8_shift: |
| 10031 | case AArch64::SQSHLv8i8_shift: |
| 10032 | case AArch64::SSHLLv16i8_shift: |
| 10033 | case AArch64::SSHLLv8i8_shift: |
| 10034 | case AArch64::UQSHLb: |
| 10035 | case AArch64::UQSHLv16i8_shift: |
| 10036 | case AArch64::UQSHLv8i8_shift: |
| 10037 | case AArch64::USHLLv16i8_shift: |
| 10038 | case AArch64::USHLLv8i8_shift: { |
| 10039 | // op: Rd |
| 10040 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10041 | op &= UINT64_C(31); |
| 10042 | Value |= op; |
| 10043 | // op: Rn |
| 10044 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10045 | op &= UINT64_C(31); |
| 10046 | op <<= 5; |
| 10047 | Value |= op; |
| 10048 | // op: imm |
| 10049 | op = getVecShiftL8OpValue(MI, 2, Fixups, STI); |
| 10050 | op &= UINT64_C(7); |
| 10051 | op <<= 16; |
| 10052 | Value |= op; |
| 10053 | break; |
| 10054 | } |
| 10055 | case AArch64::FCVTZSh: |
| 10056 | case AArch64::FCVTZSv4i16_shift: |
| 10057 | case AArch64::FCVTZSv8i16_shift: |
| 10058 | case AArch64::FCVTZUh: |
| 10059 | case AArch64::FCVTZUv4i16_shift: |
| 10060 | case AArch64::FCVTZUv8i16_shift: |
| 10061 | case AArch64::SCVTFh: |
| 10062 | case AArch64::SCVTFv4i16_shift: |
| 10063 | case AArch64::SCVTFv8i16_shift: |
| 10064 | case AArch64::SQRSHRNh: |
| 10065 | case AArch64::SQRSHRUNh: |
| 10066 | case AArch64::SQSHRNh: |
| 10067 | case AArch64::SQSHRUNh: |
| 10068 | case AArch64::SRSHRv4i16_shift: |
| 10069 | case AArch64::SRSHRv8i16_shift: |
| 10070 | case AArch64::SSHRv4i16_shift: |
| 10071 | case AArch64::SSHRv8i16_shift: |
| 10072 | case AArch64::UCVTFh: |
| 10073 | case AArch64::UCVTFv4i16_shift: |
| 10074 | case AArch64::UCVTFv8i16_shift: |
| 10075 | case AArch64::UQRSHRNh: |
| 10076 | case AArch64::UQSHRNh: |
| 10077 | case AArch64::URSHRv4i16_shift: |
| 10078 | case AArch64::URSHRv8i16_shift: |
| 10079 | case AArch64::USHRv4i16_shift: |
| 10080 | case AArch64::USHRv8i16_shift: { |
| 10081 | // op: Rd |
| 10082 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10083 | op &= UINT64_C(31); |
| 10084 | Value |= op; |
| 10085 | // op: Rn |
| 10086 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10087 | op &= UINT64_C(31); |
| 10088 | op <<= 5; |
| 10089 | Value |= op; |
| 10090 | // op: imm |
| 10091 | op = getVecShiftR16OpValue(MI, 2, Fixups, STI); |
| 10092 | op &= UINT64_C(15); |
| 10093 | op <<= 16; |
| 10094 | Value |= op; |
| 10095 | break; |
| 10096 | } |
| 10097 | case AArch64::RSHRNv8i8_shift: |
| 10098 | case AArch64::SHRNv8i8_shift: |
| 10099 | case AArch64::SQRSHRNv8i8_shift: |
| 10100 | case AArch64::SQRSHRUNv8i8_shift: |
| 10101 | case AArch64::SQSHRNv8i8_shift: |
| 10102 | case AArch64::SQSHRUNv8i8_shift: |
| 10103 | case AArch64::UQRSHRNv8i8_shift: |
| 10104 | case AArch64::UQSHRNv8i8_shift: { |
| 10105 | // op: Rd |
| 10106 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10107 | op &= UINT64_C(31); |
| 10108 | Value |= op; |
| 10109 | // op: Rn |
| 10110 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10111 | op &= UINT64_C(31); |
| 10112 | op <<= 5; |
| 10113 | Value |= op; |
| 10114 | // op: imm |
| 10115 | op = getVecShiftR16OpValue(MI, 2, Fixups, STI); |
| 10116 | op &= UINT64_C(7); |
| 10117 | op <<= 16; |
| 10118 | Value |= op; |
| 10119 | break; |
| 10120 | } |
| 10121 | case AArch64::RSHRNv4i16_shift: |
| 10122 | case AArch64::SHRNv4i16_shift: |
| 10123 | case AArch64::SQRSHRNv4i16_shift: |
| 10124 | case AArch64::SQRSHRUNv4i16_shift: |
| 10125 | case AArch64::SQSHRNv4i16_shift: |
| 10126 | case AArch64::SQSHRUNv4i16_shift: |
| 10127 | case AArch64::UQRSHRNv4i16_shift: |
| 10128 | case AArch64::UQSHRNv4i16_shift: { |
| 10129 | // op: Rd |
| 10130 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10131 | op &= UINT64_C(31); |
| 10132 | Value |= op; |
| 10133 | // op: Rn |
| 10134 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10135 | op &= UINT64_C(31); |
| 10136 | op <<= 5; |
| 10137 | Value |= op; |
| 10138 | // op: imm |
| 10139 | op = getVecShiftR32OpValue(MI, 2, Fixups, STI); |
| 10140 | op &= UINT64_C(15); |
| 10141 | op <<= 16; |
| 10142 | Value |= op; |
| 10143 | break; |
| 10144 | } |
| 10145 | case AArch64::FCVTZSs: |
| 10146 | case AArch64::FCVTZSv2i32_shift: |
| 10147 | case AArch64::FCVTZSv4i32_shift: |
| 10148 | case AArch64::FCVTZUs: |
| 10149 | case AArch64::FCVTZUv2i32_shift: |
| 10150 | case AArch64::FCVTZUv4i32_shift: |
| 10151 | case AArch64::SCVTFs: |
| 10152 | case AArch64::SCVTFv2i32_shift: |
| 10153 | case AArch64::SCVTFv4i32_shift: |
| 10154 | case AArch64::SQRSHRNs: |
| 10155 | case AArch64::SQRSHRUNs: |
| 10156 | case AArch64::SQSHRNs: |
| 10157 | case AArch64::SQSHRUNs: |
| 10158 | case AArch64::SRSHRv2i32_shift: |
| 10159 | case AArch64::SRSHRv4i32_shift: |
| 10160 | case AArch64::SSHRv2i32_shift: |
| 10161 | case AArch64::SSHRv4i32_shift: |
| 10162 | case AArch64::UCVTFs: |
| 10163 | case AArch64::UCVTFv2i32_shift: |
| 10164 | case AArch64::UCVTFv4i32_shift: |
| 10165 | case AArch64::UQRSHRNs: |
| 10166 | case AArch64::UQSHRNs: |
| 10167 | case AArch64::URSHRv2i32_shift: |
| 10168 | case AArch64::URSHRv4i32_shift: |
| 10169 | case AArch64::USHRv2i32_shift: |
| 10170 | case AArch64::USHRv4i32_shift: { |
| 10171 | // op: Rd |
| 10172 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10173 | op &= UINT64_C(31); |
| 10174 | Value |= op; |
| 10175 | // op: Rn |
| 10176 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10177 | op &= UINT64_C(31); |
| 10178 | op <<= 5; |
| 10179 | Value |= op; |
| 10180 | // op: imm |
| 10181 | op = getVecShiftR32OpValue(MI, 2, Fixups, STI); |
| 10182 | op &= UINT64_C(31); |
| 10183 | op <<= 16; |
| 10184 | Value |= op; |
| 10185 | break; |
| 10186 | } |
| 10187 | case AArch64::RSHRNv2i32_shift: |
| 10188 | case AArch64::SHRNv2i32_shift: |
| 10189 | case AArch64::SQRSHRNv2i32_shift: |
| 10190 | case AArch64::SQRSHRUNv2i32_shift: |
| 10191 | case AArch64::SQSHRNv2i32_shift: |
| 10192 | case AArch64::SQSHRUNv2i32_shift: |
| 10193 | case AArch64::UQRSHRNv2i32_shift: |
| 10194 | case AArch64::UQSHRNv2i32_shift: { |
| 10195 | // op: Rd |
| 10196 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10197 | op &= UINT64_C(31); |
| 10198 | Value |= op; |
| 10199 | // op: Rn |
| 10200 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10201 | op &= UINT64_C(31); |
| 10202 | op <<= 5; |
| 10203 | Value |= op; |
| 10204 | // op: imm |
| 10205 | op = getVecShiftR64OpValue(MI, 2, Fixups, STI); |
| 10206 | op &= UINT64_C(31); |
| 10207 | op <<= 16; |
| 10208 | Value |= op; |
| 10209 | break; |
| 10210 | } |
| 10211 | case AArch64::FCVTZSd: |
| 10212 | case AArch64::FCVTZSv2i64_shift: |
| 10213 | case AArch64::FCVTZUd: |
| 10214 | case AArch64::FCVTZUv2i64_shift: |
| 10215 | case AArch64::SCVTFd: |
| 10216 | case AArch64::SCVTFv2i64_shift: |
| 10217 | case AArch64::SRSHRd: |
| 10218 | case AArch64::SRSHRv2i64_shift: |
| 10219 | case AArch64::SSHRd: |
| 10220 | case AArch64::SSHRv2i64_shift: |
| 10221 | case AArch64::UCVTFd: |
| 10222 | case AArch64::UCVTFv2i64_shift: |
| 10223 | case AArch64::URSHRd: |
| 10224 | case AArch64::URSHRv2i64_shift: |
| 10225 | case AArch64::USHRd: |
| 10226 | case AArch64::USHRv2i64_shift: { |
| 10227 | // op: Rd |
| 10228 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10229 | op &= UINT64_C(31); |
| 10230 | Value |= op; |
| 10231 | // op: Rn |
| 10232 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10233 | op &= UINT64_C(31); |
| 10234 | op <<= 5; |
| 10235 | Value |= op; |
| 10236 | // op: imm |
| 10237 | op = getVecShiftR64OpValue(MI, 2, Fixups, STI); |
| 10238 | op &= UINT64_C(63); |
| 10239 | op <<= 16; |
| 10240 | Value |= op; |
| 10241 | break; |
| 10242 | } |
| 10243 | case AArch64::SQRSHRNb: |
| 10244 | case AArch64::SQRSHRUNb: |
| 10245 | case AArch64::SQSHRNb: |
| 10246 | case AArch64::SQSHRUNb: |
| 10247 | case AArch64::SRSHRv16i8_shift: |
| 10248 | case AArch64::SRSHRv8i8_shift: |
| 10249 | case AArch64::SSHRv16i8_shift: |
| 10250 | case AArch64::SSHRv8i8_shift: |
| 10251 | case AArch64::UQRSHRNb: |
| 10252 | case AArch64::UQSHRNb: |
| 10253 | case AArch64::URSHRv16i8_shift: |
| 10254 | case AArch64::URSHRv8i8_shift: |
| 10255 | case AArch64::USHRv16i8_shift: |
| 10256 | case AArch64::USHRv8i8_shift: { |
| 10257 | // op: Rd |
| 10258 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10259 | op &= UINT64_C(31); |
| 10260 | Value |= op; |
| 10261 | // op: Rn |
| 10262 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10263 | op &= UINT64_C(31); |
| 10264 | op <<= 5; |
| 10265 | Value |= op; |
| 10266 | // op: imm |
| 10267 | op = getVecShiftR8OpValue(MI, 2, Fixups, STI); |
| 10268 | op &= UINT64_C(7); |
| 10269 | op <<= 16; |
| 10270 | Value |= op; |
| 10271 | break; |
| 10272 | } |
| 10273 | case AArch64::ADDG: |
| 10274 | case AArch64::SUBG: { |
| 10275 | // op: Rd |
| 10276 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10277 | op &= UINT64_C(31); |
| 10278 | Value |= op; |
| 10279 | // op: Rn |
| 10280 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10281 | op &= UINT64_C(31); |
| 10282 | op <<= 5; |
| 10283 | Value |= op; |
| 10284 | // op: imm6 |
| 10285 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10286 | op &= UINT64_C(63); |
| 10287 | op <<= 16; |
| 10288 | Value |= op; |
| 10289 | // op: imm4 |
| 10290 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10291 | op &= UINT64_C(15); |
| 10292 | op <<= 10; |
| 10293 | Value |= op; |
| 10294 | break; |
| 10295 | } |
| 10296 | case AArch64::SBFMWri: |
| 10297 | case AArch64::UBFMWri: { |
| 10298 | // op: Rd |
| 10299 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10300 | op &= UINT64_C(31); |
| 10301 | Value |= op; |
| 10302 | // op: Rn |
| 10303 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10304 | op &= UINT64_C(31); |
| 10305 | op <<= 5; |
| 10306 | Value |= op; |
| 10307 | // op: immr |
| 10308 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10309 | op &= UINT64_C(31); |
| 10310 | op <<= 16; |
| 10311 | Value |= op; |
| 10312 | // op: imms |
| 10313 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10314 | op &= UINT64_C(31); |
| 10315 | op <<= 10; |
| 10316 | Value |= op; |
| 10317 | break; |
| 10318 | } |
| 10319 | case AArch64::SBFMXri: |
| 10320 | case AArch64::UBFMXri: { |
| 10321 | // op: Rd |
| 10322 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10323 | op &= UINT64_C(31); |
| 10324 | Value |= op; |
| 10325 | // op: Rn |
| 10326 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10327 | op &= UINT64_C(31); |
| 10328 | op <<= 5; |
| 10329 | Value |= op; |
| 10330 | // op: immr |
| 10331 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10332 | op &= UINT64_C(63); |
| 10333 | op <<= 16; |
| 10334 | Value |= op; |
| 10335 | // op: imms |
| 10336 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10337 | op &= UINT64_C(63); |
| 10338 | op <<= 10; |
| 10339 | Value |= op; |
| 10340 | break; |
| 10341 | } |
| 10342 | case AArch64::FCVTZSSWDri: |
| 10343 | case AArch64::FCVTZSSWHri: |
| 10344 | case AArch64::FCVTZSSWSri: |
| 10345 | case AArch64::FCVTZUSWDri: |
| 10346 | case AArch64::FCVTZUSWHri: |
| 10347 | case AArch64::FCVTZUSWSri: |
| 10348 | case AArch64::SCVTFSWDri: |
| 10349 | case AArch64::SCVTFSWHri: |
| 10350 | case AArch64::SCVTFSWSri: |
| 10351 | case AArch64::UCVTFSWDri: |
| 10352 | case AArch64::UCVTFSWHri: |
| 10353 | case AArch64::UCVTFSWSri: { |
| 10354 | // op: Rd |
| 10355 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10356 | op &= UINT64_C(31); |
| 10357 | Value |= op; |
| 10358 | // op: Rn |
| 10359 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10360 | op &= UINT64_C(31); |
| 10361 | op <<= 5; |
| 10362 | Value |= op; |
| 10363 | // op: scale |
| 10364 | op = getFixedPointScaleOpValue(MI, 2, Fixups, STI); |
| 10365 | op &= UINT64_C(31); |
| 10366 | op <<= 10; |
| 10367 | Value |= op; |
| 10368 | break; |
| 10369 | } |
| 10370 | case AArch64::FCVTZSSXDri: |
| 10371 | case AArch64::FCVTZSSXHri: |
| 10372 | case AArch64::FCVTZSSXSri: |
| 10373 | case AArch64::FCVTZUSXDri: |
| 10374 | case AArch64::FCVTZUSXHri: |
| 10375 | case AArch64::FCVTZUSXSri: |
| 10376 | case AArch64::SCVTFSXDri: |
| 10377 | case AArch64::SCVTFSXHri: |
| 10378 | case AArch64::SCVTFSXSri: |
| 10379 | case AArch64::UCVTFSXDri: |
| 10380 | case AArch64::UCVTFSXHri: |
| 10381 | case AArch64::UCVTFSXSri: { |
| 10382 | // op: Rd |
| 10383 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10384 | op &= UINT64_C(31); |
| 10385 | Value |= op; |
| 10386 | // op: Rn |
| 10387 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10388 | op &= UINT64_C(31); |
| 10389 | op <<= 5; |
| 10390 | Value |= op; |
| 10391 | // op: scale |
| 10392 | op = getFixedPointScaleOpValue(MI, 2, Fixups, STI); |
| 10393 | op &= UINT64_C(63); |
| 10394 | op <<= 10; |
| 10395 | Value |= op; |
| 10396 | break; |
| 10397 | } |
| 10398 | case AArch64::BFMWri: { |
| 10399 | // op: Rd |
| 10400 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10401 | op &= UINT64_C(31); |
| 10402 | Value |= op; |
| 10403 | // op: Rn |
| 10404 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10405 | op &= UINT64_C(31); |
| 10406 | op <<= 5; |
| 10407 | Value |= op; |
| 10408 | // op: immr |
| 10409 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10410 | op &= UINT64_C(31); |
| 10411 | op <<= 16; |
| 10412 | Value |= op; |
| 10413 | // op: imms |
| 10414 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 10415 | op &= UINT64_C(31); |
| 10416 | op <<= 10; |
| 10417 | Value |= op; |
| 10418 | break; |
| 10419 | } |
| 10420 | case AArch64::BFMXri: { |
| 10421 | // op: Rd |
| 10422 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10423 | op &= UINT64_C(31); |
| 10424 | Value |= op; |
| 10425 | // op: Rn |
| 10426 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10427 | op &= UINT64_C(31); |
| 10428 | op <<= 5; |
| 10429 | Value |= op; |
| 10430 | // op: immr |
| 10431 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10432 | op &= UINT64_C(63); |
| 10433 | op <<= 16; |
| 10434 | Value |= op; |
| 10435 | // op: imms |
| 10436 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 10437 | op &= UINT64_C(63); |
| 10438 | op <<= 10; |
| 10439 | Value |= op; |
| 10440 | break; |
| 10441 | } |
| 10442 | case AArch64::FMOVDi: |
| 10443 | case AArch64::FMOVHi: |
| 10444 | case AArch64::FMOVSi: { |
| 10445 | // op: Rd |
| 10446 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10447 | op &= UINT64_C(31); |
| 10448 | Value |= op; |
| 10449 | // op: imm |
| 10450 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10451 | op &= UINT64_C(255); |
| 10452 | op <<= 13; |
| 10453 | Value |= op; |
| 10454 | break; |
| 10455 | } |
| 10456 | case AArch64::MOVNWi: |
| 10457 | case AArch64::MOVNXi: { |
| 10458 | // op: Rd |
| 10459 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10460 | op &= UINT64_C(31); |
| 10461 | Value |= op; |
| 10462 | // op: imm |
| 10463 | op = getMoveWideImmOpValue(MI, 1, Fixups, STI); |
| 10464 | op &= UINT64_C(65535); |
| 10465 | op <<= 5; |
| 10466 | Value |= op; |
| 10467 | // op: shift |
| 10468 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10469 | op &= UINT64_C(48); |
| 10470 | op <<= 17; |
| 10471 | Value |= op; |
| 10472 | break; |
| 10473 | } |
| 10474 | case AArch64::MOVZWi: |
| 10475 | case AArch64::MOVZXi: { |
| 10476 | // op: Rd |
| 10477 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10478 | op &= UINT64_C(31); |
| 10479 | Value |= op; |
| 10480 | // op: imm |
| 10481 | op = getMoveWideImmOpValue(MI, 1, Fixups, STI); |
| 10482 | op &= UINT64_C(65535); |
| 10483 | op <<= 5; |
| 10484 | Value |= op; |
| 10485 | // op: shift |
| 10486 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10487 | op &= UINT64_C(48); |
| 10488 | op <<= 17; |
| 10489 | Value |= op; |
| 10490 | Value = fixMOVZ(MI, Value, STI); |
| 10491 | break; |
| 10492 | } |
| 10493 | case AArch64::MOVKWi: |
| 10494 | case AArch64::MOVKXi: { |
| 10495 | // op: Rd |
| 10496 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10497 | op &= UINT64_C(31); |
| 10498 | Value |= op; |
| 10499 | // op: imm |
| 10500 | op = getMoveWideImmOpValue(MI, 2, Fixups, STI); |
| 10501 | op &= UINT64_C(65535); |
| 10502 | op <<= 5; |
| 10503 | Value |= op; |
| 10504 | // op: shift |
| 10505 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10506 | op &= UINT64_C(48); |
| 10507 | op <<= 17; |
| 10508 | Value |= op; |
| 10509 | break; |
| 10510 | } |
| 10511 | case AArch64::CNTB_XPiI: |
| 10512 | case AArch64::CNTD_XPiI: |
| 10513 | case AArch64::CNTH_XPiI: |
| 10514 | case AArch64::CNTW_XPiI: { |
| 10515 | // op: Rd |
| 10516 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10517 | op &= UINT64_C(31); |
| 10518 | Value |= op; |
| 10519 | // op: imm4 |
| 10520 | op = getSVEIncDecImm(MI, 2, Fixups, STI); |
| 10521 | op &= UINT64_C(15); |
| 10522 | op <<= 16; |
| 10523 | Value |= op; |
| 10524 | // op: pattern |
| 10525 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10526 | op &= UINT64_C(31); |
| 10527 | op <<= 5; |
| 10528 | Value |= op; |
| 10529 | break; |
| 10530 | } |
| 10531 | case AArch64::RDVLI_XI: { |
| 10532 | // op: Rd |
| 10533 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10534 | op &= UINT64_C(31); |
| 10535 | Value |= op; |
| 10536 | // op: imm6 |
| 10537 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10538 | op &= UINT64_C(63); |
| 10539 | op <<= 5; |
| 10540 | Value |= op; |
| 10541 | break; |
| 10542 | } |
| 10543 | case AArch64::FMOVv2f32_ns: |
| 10544 | case AArch64::FMOVv2f64_ns: |
| 10545 | case AArch64::FMOVv4f16_ns: |
| 10546 | case AArch64::FMOVv4f32_ns: |
| 10547 | case AArch64::FMOVv8f16_ns: |
| 10548 | case AArch64::MOVID: |
| 10549 | case AArch64::MOVIv16b_ns: |
| 10550 | case AArch64::MOVIv2d_ns: |
| 10551 | case AArch64::MOVIv8b_ns: { |
| 10552 | // op: Rd |
| 10553 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10554 | op &= UINT64_C(31); |
| 10555 | Value |= op; |
| 10556 | // op: imm8 |
| 10557 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10558 | Value |= (op & UINT64_C(224)) << 11; |
| 10559 | Value |= (op & UINT64_C(31)) << 5; |
| 10560 | break; |
| 10561 | } |
| 10562 | case AArch64::MOVIv2s_msl: |
| 10563 | case AArch64::MOVIv4s_msl: |
| 10564 | case AArch64::MVNIv2s_msl: |
| 10565 | case AArch64::MVNIv4s_msl: { |
| 10566 | // op: Rd |
| 10567 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10568 | op &= UINT64_C(31); |
| 10569 | Value |= op; |
| 10570 | // op: imm8 |
| 10571 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10572 | Value |= (op & UINT64_C(224)) << 11; |
| 10573 | Value |= (op & UINT64_C(31)) << 5; |
| 10574 | // op: shift |
| 10575 | op = getMoveVecShifterOpValue(MI, 2, Fixups, STI); |
| 10576 | op &= UINT64_C(1); |
| 10577 | op <<= 12; |
| 10578 | Value |= op; |
| 10579 | break; |
| 10580 | } |
| 10581 | case AArch64::MOVIv4i16: |
| 10582 | case AArch64::MOVIv8i16: |
| 10583 | case AArch64::MVNIv4i16: |
| 10584 | case AArch64::MVNIv8i16: { |
| 10585 | // op: Rd |
| 10586 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10587 | op &= UINT64_C(31); |
| 10588 | Value |= op; |
| 10589 | // op: imm8 |
| 10590 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10591 | Value |= (op & UINT64_C(224)) << 11; |
| 10592 | Value |= (op & UINT64_C(31)) << 5; |
| 10593 | // op: shift |
| 10594 | op = getVecShifterOpValue(MI, 2, Fixups, STI); |
| 10595 | op &= UINT64_C(1); |
| 10596 | op <<= 13; |
| 10597 | Value |= op; |
| 10598 | break; |
| 10599 | } |
| 10600 | case AArch64::MOVIv2i32: |
| 10601 | case AArch64::MOVIv4i32: |
| 10602 | case AArch64::MVNIv2i32: |
| 10603 | case AArch64::MVNIv4i32: { |
| 10604 | // op: Rd |
| 10605 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 10606 | op &= UINT64_C(31); |
| 10607 | Value |= op; |
| 10608 | // op: imm8 |
| 10609 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10610 | Value |= (op & UINT64_C(224)) << 11; |
| 10611 | Value |= (op & UINT64_C(31)) << 5; |
| 10612 | // op: shift |
| 10613 | op = getVecShifterOpValue(MI, 2, Fixups, STI); |
| 10614 | op &= UINT64_C(3); |
| 10615 | op <<= 13; |
| 10616 | Value |= op; |
| 10617 | break; |
| 10618 | } |
| 10619 | case AArch64::AESDrr: |
| 10620 | case AArch64::AESErr: |
| 10621 | case AArch64::BFCVTN2: |
| 10622 | case AArch64::FCVTNv4i32: |
| 10623 | case AArch64::FCVTNv8i16: |
| 10624 | case AArch64::FCVTXNv4f32: |
| 10625 | case AArch64::SADALPv16i8_v8i16: |
| 10626 | case AArch64::SADALPv2i32_v1i64: |
| 10627 | case AArch64::SADALPv4i16_v2i32: |
| 10628 | case AArch64::SADALPv4i32_v2i64: |
| 10629 | case AArch64::SADALPv8i16_v4i32: |
| 10630 | case AArch64::SADALPv8i8_v4i16: |
| 10631 | case AArch64::SHA1SU1rr: |
| 10632 | case AArch64::SHA256SU0rr: |
| 10633 | case AArch64::SQXTNv16i8: |
| 10634 | case AArch64::SQXTNv4i32: |
| 10635 | case AArch64::SQXTNv8i16: |
| 10636 | case AArch64::SQXTUNv16i8: |
| 10637 | case AArch64::SQXTUNv4i32: |
| 10638 | case AArch64::SQXTUNv8i16: |
| 10639 | case AArch64::SUQADDv16i8: |
| 10640 | case AArch64::SUQADDv1i16: |
| 10641 | case AArch64::SUQADDv1i32: |
| 10642 | case AArch64::SUQADDv1i64: |
| 10643 | case AArch64::SUQADDv1i8: |
| 10644 | case AArch64::SUQADDv2i32: |
| 10645 | case AArch64::SUQADDv2i64: |
| 10646 | case AArch64::SUQADDv4i16: |
| 10647 | case AArch64::SUQADDv4i32: |
| 10648 | case AArch64::SUQADDv8i16: |
| 10649 | case AArch64::SUQADDv8i8: |
| 10650 | case AArch64::UADALPv16i8_v8i16: |
| 10651 | case AArch64::UADALPv2i32_v1i64: |
| 10652 | case AArch64::UADALPv4i16_v2i32: |
| 10653 | case AArch64::UADALPv4i32_v2i64: |
| 10654 | case AArch64::UADALPv8i16_v4i32: |
| 10655 | case AArch64::UADALPv8i8_v4i16: |
| 10656 | case AArch64::UQXTNv16i8: |
| 10657 | case AArch64::UQXTNv4i32: |
| 10658 | case AArch64::UQXTNv8i16: |
| 10659 | case AArch64::USQADDv16i8: |
| 10660 | case AArch64::USQADDv1i16: |
| 10661 | case AArch64::USQADDv1i32: |
| 10662 | case AArch64::USQADDv1i64: |
| 10663 | case AArch64::USQADDv1i8: |
| 10664 | case AArch64::USQADDv2i32: |
| 10665 | case AArch64::USQADDv2i64: |
| 10666 | case AArch64::USQADDv4i16: |
| 10667 | case AArch64::USQADDv4i32: |
| 10668 | case AArch64::USQADDv8i16: |
| 10669 | case AArch64::USQADDv8i8: |
| 10670 | case AArch64::XTNv16i8: |
| 10671 | case AArch64::XTNv4i32: |
| 10672 | case AArch64::XTNv8i16: { |
| 10673 | // op: Rd |
| 10674 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10675 | op &= UINT64_C(31); |
| 10676 | Value |= op; |
| 10677 | // op: Rn |
| 10678 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10679 | op &= UINT64_C(31); |
| 10680 | op <<= 5; |
| 10681 | Value |= op; |
| 10682 | break; |
| 10683 | } |
| 10684 | case AArch64::BFMLALBIdx: |
| 10685 | case AArch64::BFMLALTIdx: |
| 10686 | case AArch64::FMLAL2lanev4f16: |
| 10687 | case AArch64::FMLAL2lanev8f16: |
| 10688 | case AArch64::FMLALlanev4f16: |
| 10689 | case AArch64::FMLALlanev8f16: |
| 10690 | case AArch64::FMLAv1i16_indexed: |
| 10691 | case AArch64::FMLAv4i16_indexed: |
| 10692 | case AArch64::FMLAv8i16_indexed: |
| 10693 | case AArch64::FMLSL2lanev4f16: |
| 10694 | case AArch64::FMLSL2lanev8f16: |
| 10695 | case AArch64::FMLSLlanev4f16: |
| 10696 | case AArch64::FMLSLlanev8f16: |
| 10697 | case AArch64::FMLSv1i16_indexed: |
| 10698 | case AArch64::FMLSv4i16_indexed: |
| 10699 | case AArch64::FMLSv8i16_indexed: |
| 10700 | case AArch64::MLAv4i16_indexed: |
| 10701 | case AArch64::MLAv8i16_indexed: |
| 10702 | case AArch64::MLSv4i16_indexed: |
| 10703 | case AArch64::MLSv8i16_indexed: |
| 10704 | case AArch64::SMLALv4i16_indexed: |
| 10705 | case AArch64::SMLALv8i16_indexed: |
| 10706 | case AArch64::SMLSLv4i16_indexed: |
| 10707 | case AArch64::SMLSLv8i16_indexed: |
| 10708 | case AArch64::SQDMLALv1i32_indexed: |
| 10709 | case AArch64::SQDMLALv4i16_indexed: |
| 10710 | case AArch64::SQDMLALv8i16_indexed: |
| 10711 | case AArch64::SQDMLSLv1i32_indexed: |
| 10712 | case AArch64::SQDMLSLv4i16_indexed: |
| 10713 | case AArch64::SQDMLSLv8i16_indexed: |
| 10714 | case AArch64::SQRDMLAHi16_indexed: |
| 10715 | case AArch64::SQRDMLAHv4i16_indexed: |
| 10716 | case AArch64::SQRDMLAHv8i16_indexed: |
| 10717 | case AArch64::SQRDMLSHi16_indexed: |
| 10718 | case AArch64::SQRDMLSHv4i16_indexed: |
| 10719 | case AArch64::SQRDMLSHv8i16_indexed: |
| 10720 | case AArch64::UMLALv4i16_indexed: |
| 10721 | case AArch64::UMLALv8i16_indexed: |
| 10722 | case AArch64::UMLSLv4i16_indexed: |
| 10723 | case AArch64::UMLSLv8i16_indexed: { |
| 10724 | // op: Rd |
| 10725 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10726 | op &= UINT64_C(31); |
| 10727 | Value |= op; |
| 10728 | // op: Rn |
| 10729 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10730 | op &= UINT64_C(31); |
| 10731 | op <<= 5; |
| 10732 | Value |= op; |
| 10733 | // op: Rm |
| 10734 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10735 | op &= UINT64_C(15); |
| 10736 | op <<= 16; |
| 10737 | Value |= op; |
| 10738 | // op: idx |
| 10739 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 10740 | Value |= (op & UINT64_C(3)) << 20; |
| 10741 | Value |= (op & UINT64_C(4)) << 9; |
| 10742 | break; |
| 10743 | } |
| 10744 | case AArch64::ADDHNv2i64_v4i32: |
| 10745 | case AArch64::ADDHNv4i32_v8i16: |
| 10746 | case AArch64::ADDHNv8i16_v16i8: |
| 10747 | case AArch64::BFDOTv4bf16: |
| 10748 | case AArch64::BFDOTv8bf16: |
| 10749 | case AArch64::BFMLALB: |
| 10750 | case AArch64::BFMLALT: |
| 10751 | case AArch64::BFMMLA: |
| 10752 | case AArch64::BIFv16i8: |
| 10753 | case AArch64::BIFv8i8: |
| 10754 | case AArch64::BITv16i8: |
| 10755 | case AArch64::BITv8i8: |
| 10756 | case AArch64::BSLv16i8: |
| 10757 | case AArch64::BSLv8i8: |
| 10758 | case AArch64::FMLAL2v4f16: |
| 10759 | case AArch64::FMLAL2v8f16: |
| 10760 | case AArch64::FMLALv4f16: |
| 10761 | case AArch64::FMLALv8f16: |
| 10762 | case AArch64::FMLAv2f32: |
| 10763 | case AArch64::FMLAv2f64: |
| 10764 | case AArch64::FMLAv4f16: |
| 10765 | case AArch64::FMLAv4f32: |
| 10766 | case AArch64::FMLAv8f16: |
| 10767 | case AArch64::FMLSL2v4f16: |
| 10768 | case AArch64::FMLSL2v8f16: |
| 10769 | case AArch64::FMLSLv4f16: |
| 10770 | case AArch64::FMLSLv8f16: |
| 10771 | case AArch64::FMLSv2f32: |
| 10772 | case AArch64::FMLSv2f64: |
| 10773 | case AArch64::FMLSv4f16: |
| 10774 | case AArch64::FMLSv4f32: |
| 10775 | case AArch64::FMLSv8f16: |
| 10776 | case AArch64::MLAv16i8: |
| 10777 | case AArch64::MLAv2i32: |
| 10778 | case AArch64::MLAv4i16: |
| 10779 | case AArch64::MLAv4i32: |
| 10780 | case AArch64::MLAv8i16: |
| 10781 | case AArch64::MLAv8i8: |
| 10782 | case AArch64::MLSv16i8: |
| 10783 | case AArch64::MLSv2i32: |
| 10784 | case AArch64::MLSv4i16: |
| 10785 | case AArch64::MLSv4i32: |
| 10786 | case AArch64::MLSv8i16: |
| 10787 | case AArch64::MLSv8i8: |
| 10788 | case AArch64::RADDHNv2i64_v4i32: |
| 10789 | case AArch64::RADDHNv4i32_v8i16: |
| 10790 | case AArch64::RADDHNv8i16_v16i8: |
| 10791 | case AArch64::RSUBHNv2i64_v4i32: |
| 10792 | case AArch64::RSUBHNv4i32_v8i16: |
| 10793 | case AArch64::RSUBHNv8i16_v16i8: |
| 10794 | case AArch64::SABALv16i8_v8i16: |
| 10795 | case AArch64::SABALv2i32_v2i64: |
| 10796 | case AArch64::SABALv4i16_v4i32: |
| 10797 | case AArch64::SABALv4i32_v2i64: |
| 10798 | case AArch64::SABALv8i16_v4i32: |
| 10799 | case AArch64::SABALv8i8_v8i16: |
| 10800 | case AArch64::SABAv16i8: |
| 10801 | case AArch64::SABAv2i32: |
| 10802 | case AArch64::SABAv4i16: |
| 10803 | case AArch64::SABAv4i32: |
| 10804 | case AArch64::SABAv8i16: |
| 10805 | case AArch64::SABAv8i8: |
| 10806 | case AArch64::SDOTv16i8: |
| 10807 | case AArch64::SDOTv8i8: |
| 10808 | case AArch64::SHA1Crrr: |
| 10809 | case AArch64::SHA1Mrrr: |
| 10810 | case AArch64::SHA1Prrr: |
| 10811 | case AArch64::SHA1SU0rrr: |
| 10812 | case AArch64::SHA256H2rrr: |
| 10813 | case AArch64::SHA256Hrrr: |
| 10814 | case AArch64::SHA256SU1rrr: |
| 10815 | case AArch64::SMLALv16i8_v8i16: |
| 10816 | case AArch64::SMLALv2i32_v2i64: |
| 10817 | case AArch64::SMLALv4i16_v4i32: |
| 10818 | case AArch64::SMLALv4i32_v2i64: |
| 10819 | case AArch64::SMLALv8i16_v4i32: |
| 10820 | case AArch64::SMLALv8i8_v8i16: |
| 10821 | case AArch64::SMLSLv16i8_v8i16: |
| 10822 | case AArch64::SMLSLv2i32_v2i64: |
| 10823 | case AArch64::SMLSLv4i16_v4i32: |
| 10824 | case AArch64::SMLSLv4i32_v2i64: |
| 10825 | case AArch64::SMLSLv8i16_v4i32: |
| 10826 | case AArch64::SMLSLv8i8_v8i16: |
| 10827 | case AArch64::SMMLA: |
| 10828 | case AArch64::SQDMLALi16: |
| 10829 | case AArch64::SQDMLALi32: |
| 10830 | case AArch64::SQDMLALv2i32_v2i64: |
| 10831 | case AArch64::SQDMLALv4i16_v4i32: |
| 10832 | case AArch64::SQDMLALv4i32_v2i64: |
| 10833 | case AArch64::SQDMLALv8i16_v4i32: |
| 10834 | case AArch64::SQDMLSLi16: |
| 10835 | case AArch64::SQDMLSLi32: |
| 10836 | case AArch64::SQDMLSLv2i32_v2i64: |
| 10837 | case AArch64::SQDMLSLv4i16_v4i32: |
| 10838 | case AArch64::SQDMLSLv4i32_v2i64: |
| 10839 | case AArch64::SQDMLSLv8i16_v4i32: |
| 10840 | case AArch64::SQRDMLAHv1i16: |
| 10841 | case AArch64::SQRDMLAHv1i32: |
| 10842 | case AArch64::SQRDMLAHv2i32: |
| 10843 | case AArch64::SQRDMLAHv4i16: |
| 10844 | case AArch64::SQRDMLAHv4i32: |
| 10845 | case AArch64::SQRDMLAHv8i16: |
| 10846 | case AArch64::SQRDMLSHv1i16: |
| 10847 | case AArch64::SQRDMLSHv1i32: |
| 10848 | case AArch64::SQRDMLSHv2i32: |
| 10849 | case AArch64::SQRDMLSHv4i16: |
| 10850 | case AArch64::SQRDMLSHv4i32: |
| 10851 | case AArch64::SQRDMLSHv8i16: |
| 10852 | case AArch64::SUBHNv2i64_v4i32: |
| 10853 | case AArch64::SUBHNv4i32_v8i16: |
| 10854 | case AArch64::SUBHNv8i16_v16i8: |
| 10855 | case AArch64::UABALv16i8_v8i16: |
| 10856 | case AArch64::UABALv2i32_v2i64: |
| 10857 | case AArch64::UABALv4i16_v4i32: |
| 10858 | case AArch64::UABALv4i32_v2i64: |
| 10859 | case AArch64::UABALv8i16_v4i32: |
| 10860 | case AArch64::UABALv8i8_v8i16: |
| 10861 | case AArch64::UABAv16i8: |
| 10862 | case AArch64::UABAv2i32: |
| 10863 | case AArch64::UABAv4i16: |
| 10864 | case AArch64::UABAv4i32: |
| 10865 | case AArch64::UABAv8i16: |
| 10866 | case AArch64::UABAv8i8: |
| 10867 | case AArch64::UDOTv16i8: |
| 10868 | case AArch64::UDOTv8i8: |
| 10869 | case AArch64::UMLALv16i8_v8i16: |
| 10870 | case AArch64::UMLALv2i32_v2i64: |
| 10871 | case AArch64::UMLALv4i16_v4i32: |
| 10872 | case AArch64::UMLALv4i32_v2i64: |
| 10873 | case AArch64::UMLALv8i16_v4i32: |
| 10874 | case AArch64::UMLALv8i8_v8i16: |
| 10875 | case AArch64::UMLSLv16i8_v8i16: |
| 10876 | case AArch64::UMLSLv2i32_v2i64: |
| 10877 | case AArch64::UMLSLv4i16_v4i32: |
| 10878 | case AArch64::UMLSLv4i32_v2i64: |
| 10879 | case AArch64::UMLSLv8i16_v4i32: |
| 10880 | case AArch64::UMLSLv8i8_v8i16: |
| 10881 | case AArch64::UMMLA: |
| 10882 | case AArch64::USDOTv16i8: |
| 10883 | case AArch64::USDOTv8i8: |
| 10884 | case AArch64::USMMLA: { |
| 10885 | // op: Rd |
| 10886 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10887 | op &= UINT64_C(31); |
| 10888 | Value |= op; |
| 10889 | // op: Rn |
| 10890 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10891 | op &= UINT64_C(31); |
| 10892 | op <<= 5; |
| 10893 | Value |= op; |
| 10894 | // op: Rm |
| 10895 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10896 | op &= UINT64_C(31); |
| 10897 | op <<= 16; |
| 10898 | Value |= op; |
| 10899 | break; |
| 10900 | } |
| 10901 | case AArch64::BF16DOTlanev4bf16: |
| 10902 | case AArch64::BF16DOTlanev8bf16: |
| 10903 | case AArch64::FMLAv1i32_indexed: |
| 10904 | case AArch64::FMLAv2i32_indexed: |
| 10905 | case AArch64::FMLAv4i32_indexed: |
| 10906 | case AArch64::FMLSv1i32_indexed: |
| 10907 | case AArch64::FMLSv2i32_indexed: |
| 10908 | case AArch64::FMLSv4i32_indexed: |
| 10909 | case AArch64::MLAv2i32_indexed: |
| 10910 | case AArch64::MLAv4i32_indexed: |
| 10911 | case AArch64::MLSv2i32_indexed: |
| 10912 | case AArch64::MLSv4i32_indexed: |
| 10913 | case AArch64::SDOTlanev16i8: |
| 10914 | case AArch64::SDOTlanev8i8: |
| 10915 | case AArch64::SMLALv2i32_indexed: |
| 10916 | case AArch64::SMLALv4i32_indexed: |
| 10917 | case AArch64::SMLSLv2i32_indexed: |
| 10918 | case AArch64::SMLSLv4i32_indexed: |
| 10919 | case AArch64::SQDMLALv1i64_indexed: |
| 10920 | case AArch64::SQDMLALv2i32_indexed: |
| 10921 | case AArch64::SQDMLALv4i32_indexed: |
| 10922 | case AArch64::SQDMLSLv1i64_indexed: |
| 10923 | case AArch64::SQDMLSLv2i32_indexed: |
| 10924 | case AArch64::SQDMLSLv4i32_indexed: |
| 10925 | case AArch64::SQRDMLAHi32_indexed: |
| 10926 | case AArch64::SQRDMLAHv2i32_indexed: |
| 10927 | case AArch64::SQRDMLAHv4i32_indexed: |
| 10928 | case AArch64::SQRDMLSHi32_indexed: |
| 10929 | case AArch64::SQRDMLSHv2i32_indexed: |
| 10930 | case AArch64::SQRDMLSHv4i32_indexed: |
| 10931 | case AArch64::SUDOTlanev16i8: |
| 10932 | case AArch64::SUDOTlanev8i8: |
| 10933 | case AArch64::UDOTlanev16i8: |
| 10934 | case AArch64::UDOTlanev8i8: |
| 10935 | case AArch64::UMLALv2i32_indexed: |
| 10936 | case AArch64::UMLALv4i32_indexed: |
| 10937 | case AArch64::UMLSLv2i32_indexed: |
| 10938 | case AArch64::UMLSLv4i32_indexed: |
| 10939 | case AArch64::USDOTlanev16i8: |
| 10940 | case AArch64::USDOTlanev8i8: { |
| 10941 | // op: Rd |
| 10942 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10943 | op &= UINT64_C(31); |
| 10944 | Value |= op; |
| 10945 | // op: Rn |
| 10946 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10947 | op &= UINT64_C(31); |
| 10948 | op <<= 5; |
| 10949 | Value |= op; |
| 10950 | // op: Rm |
| 10951 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10952 | op &= UINT64_C(31); |
| 10953 | op <<= 16; |
| 10954 | Value |= op; |
| 10955 | // op: idx |
| 10956 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 10957 | Value |= (op & UINT64_C(1)) << 21; |
| 10958 | Value |= (op & UINT64_C(2)) << 10; |
| 10959 | break; |
| 10960 | } |
| 10961 | case AArch64::FMLAv1i64_indexed: |
| 10962 | case AArch64::FMLAv2i64_indexed: |
| 10963 | case AArch64::FMLSv1i64_indexed: |
| 10964 | case AArch64::FMLSv2i64_indexed: { |
| 10965 | // op: Rd |
| 10966 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10967 | op &= UINT64_C(31); |
| 10968 | Value |= op; |
| 10969 | // op: Rn |
| 10970 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10971 | op &= UINT64_C(31); |
| 10972 | op <<= 5; |
| 10973 | Value |= op; |
| 10974 | // op: Rm |
| 10975 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 10976 | op &= UINT64_C(31); |
| 10977 | op <<= 16; |
| 10978 | Value |= op; |
| 10979 | // op: idx |
| 10980 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 10981 | op &= UINT64_C(1); |
| 10982 | op <<= 11; |
| 10983 | Value |= op; |
| 10984 | break; |
| 10985 | } |
| 10986 | case AArch64::FCMLAv2f32: |
| 10987 | case AArch64::FCMLAv2f64: |
| 10988 | case AArch64::FCMLAv4f16: |
| 10989 | case AArch64::FCMLAv4f32: |
| 10990 | case AArch64::FCMLAv8f16: { |
| 10991 | // op: Rd |
| 10992 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 10993 | op &= UINT64_C(31); |
| 10994 | Value |= op; |
| 10995 | // op: Rn |
| 10996 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 10997 | op &= UINT64_C(31); |
| 10998 | op <<= 5; |
| 10999 | Value |= op; |
| 11000 | // op: Rm |
| 11001 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11002 | op &= UINT64_C(31); |
| 11003 | op <<= 16; |
| 11004 | Value |= op; |
| 11005 | // op: rot |
| 11006 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 11007 | op &= UINT64_C(3); |
| 11008 | op <<= 11; |
| 11009 | Value |= op; |
| 11010 | break; |
| 11011 | } |
| 11012 | case AArch64::FCMLAv8f16_indexed: { |
| 11013 | // op: Rd |
| 11014 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11015 | op &= UINT64_C(31); |
| 11016 | Value |= op; |
| 11017 | // op: Rn |
| 11018 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11019 | op &= UINT64_C(31); |
| 11020 | op <<= 5; |
| 11021 | Value |= op; |
| 11022 | // op: Rm |
| 11023 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11024 | op &= UINT64_C(31); |
| 11025 | op <<= 16; |
| 11026 | Value |= op; |
| 11027 | // op: rot |
| 11028 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 11029 | op &= UINT64_C(3); |
| 11030 | op <<= 13; |
| 11031 | Value |= op; |
| 11032 | // op: idx |
| 11033 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 11034 | Value |= (op & UINT64_C(1)) << 21; |
| 11035 | Value |= (op & UINT64_C(2)) << 10; |
| 11036 | break; |
| 11037 | } |
| 11038 | case AArch64::FCMLAv4f32_indexed: { |
| 11039 | // op: Rd |
| 11040 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11041 | op &= UINT64_C(31); |
| 11042 | Value |= op; |
| 11043 | // op: Rn |
| 11044 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11045 | op &= UINT64_C(31); |
| 11046 | op <<= 5; |
| 11047 | Value |= op; |
| 11048 | // op: Rm |
| 11049 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11050 | op &= UINT64_C(31); |
| 11051 | op <<= 16; |
| 11052 | Value |= op; |
| 11053 | // op: rot |
| 11054 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 11055 | op &= UINT64_C(3); |
| 11056 | op <<= 13; |
| 11057 | Value |= op; |
| 11058 | // op: idx |
| 11059 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 11060 | op &= UINT64_C(1); |
| 11061 | op <<= 11; |
| 11062 | Value |= op; |
| 11063 | break; |
| 11064 | } |
| 11065 | case AArch64::FCMLAv4f16_indexed: { |
| 11066 | // op: Rd |
| 11067 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11068 | op &= UINT64_C(31); |
| 11069 | Value |= op; |
| 11070 | // op: Rn |
| 11071 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11072 | op &= UINT64_C(31); |
| 11073 | op <<= 5; |
| 11074 | Value |= op; |
| 11075 | // op: Rm |
| 11076 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11077 | op &= UINT64_C(31); |
| 11078 | op <<= 16; |
| 11079 | Value |= op; |
| 11080 | // op: rot |
| 11081 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 11082 | op &= UINT64_C(3); |
| 11083 | op <<= 13; |
| 11084 | Value |= op; |
| 11085 | // op: idx |
| 11086 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 11087 | op &= UINT64_C(1); |
| 11088 | op <<= 21; |
| 11089 | Value |= op; |
| 11090 | break; |
| 11091 | } |
| 11092 | case AArch64::SLIv4i16_shift: |
| 11093 | case AArch64::SLIv8i16_shift: { |
| 11094 | // op: Rd |
| 11095 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11096 | op &= UINT64_C(31); |
| 11097 | Value |= op; |
| 11098 | // op: Rn |
| 11099 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11100 | op &= UINT64_C(31); |
| 11101 | op <<= 5; |
| 11102 | Value |= op; |
| 11103 | // op: imm |
| 11104 | op = getVecShiftL16OpValue(MI, 3, Fixups, STI); |
| 11105 | op &= UINT64_C(15); |
| 11106 | op <<= 16; |
| 11107 | Value |= op; |
| 11108 | break; |
| 11109 | } |
| 11110 | case AArch64::SLIv2i32_shift: |
| 11111 | case AArch64::SLIv4i32_shift: { |
| 11112 | // op: Rd |
| 11113 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11114 | op &= UINT64_C(31); |
| 11115 | Value |= op; |
| 11116 | // op: Rn |
| 11117 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11118 | op &= UINT64_C(31); |
| 11119 | op <<= 5; |
| 11120 | Value |= op; |
| 11121 | // op: imm |
| 11122 | op = getVecShiftL32OpValue(MI, 3, Fixups, STI); |
| 11123 | op &= UINT64_C(31); |
| 11124 | op <<= 16; |
| 11125 | Value |= op; |
| 11126 | break; |
| 11127 | } |
| 11128 | case AArch64::SLId: |
| 11129 | case AArch64::SLIv2i64_shift: { |
| 11130 | // op: Rd |
| 11131 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11132 | op &= UINT64_C(31); |
| 11133 | Value |= op; |
| 11134 | // op: Rn |
| 11135 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11136 | op &= UINT64_C(31); |
| 11137 | op <<= 5; |
| 11138 | Value |= op; |
| 11139 | // op: imm |
| 11140 | op = getVecShiftL64OpValue(MI, 3, Fixups, STI); |
| 11141 | op &= UINT64_C(63); |
| 11142 | op <<= 16; |
| 11143 | Value |= op; |
| 11144 | break; |
| 11145 | } |
| 11146 | case AArch64::SLIv16i8_shift: |
| 11147 | case AArch64::SLIv8i8_shift: { |
| 11148 | // op: Rd |
| 11149 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11150 | op &= UINT64_C(31); |
| 11151 | Value |= op; |
| 11152 | // op: Rn |
| 11153 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11154 | op &= UINT64_C(31); |
| 11155 | op <<= 5; |
| 11156 | Value |= op; |
| 11157 | // op: imm |
| 11158 | op = getVecShiftL8OpValue(MI, 3, Fixups, STI); |
| 11159 | op &= UINT64_C(7); |
| 11160 | op <<= 16; |
| 11161 | Value |= op; |
| 11162 | break; |
| 11163 | } |
| 11164 | case AArch64::SRIv4i16_shift: |
| 11165 | case AArch64::SRIv8i16_shift: |
| 11166 | case AArch64::SRSRAv4i16_shift: |
| 11167 | case AArch64::SRSRAv8i16_shift: |
| 11168 | case AArch64::SSRAv4i16_shift: |
| 11169 | case AArch64::SSRAv8i16_shift: |
| 11170 | case AArch64::URSRAv4i16_shift: |
| 11171 | case AArch64::URSRAv8i16_shift: |
| 11172 | case AArch64::USRAv4i16_shift: |
| 11173 | case AArch64::USRAv8i16_shift: { |
| 11174 | // op: Rd |
| 11175 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11176 | op &= UINT64_C(31); |
| 11177 | Value |= op; |
| 11178 | // op: Rn |
| 11179 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11180 | op &= UINT64_C(31); |
| 11181 | op <<= 5; |
| 11182 | Value |= op; |
| 11183 | // op: imm |
| 11184 | op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| 11185 | op &= UINT64_C(15); |
| 11186 | op <<= 16; |
| 11187 | Value |= op; |
| 11188 | break; |
| 11189 | } |
| 11190 | case AArch64::RSHRNv16i8_shift: |
| 11191 | case AArch64::SHRNv16i8_shift: |
| 11192 | case AArch64::SQRSHRNv16i8_shift: |
| 11193 | case AArch64::SQRSHRUNv16i8_shift: |
| 11194 | case AArch64::SQSHRNv16i8_shift: |
| 11195 | case AArch64::SQSHRUNv16i8_shift: |
| 11196 | case AArch64::UQRSHRNv16i8_shift: |
| 11197 | case AArch64::UQSHRNv16i8_shift: { |
| 11198 | // op: Rd |
| 11199 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11200 | op &= UINT64_C(31); |
| 11201 | Value |= op; |
| 11202 | // op: Rn |
| 11203 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11204 | op &= UINT64_C(31); |
| 11205 | op <<= 5; |
| 11206 | Value |= op; |
| 11207 | // op: imm |
| 11208 | op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| 11209 | op &= UINT64_C(7); |
| 11210 | op <<= 16; |
| 11211 | Value |= op; |
| 11212 | break; |
| 11213 | } |
| 11214 | case AArch64::RSHRNv8i16_shift: |
| 11215 | case AArch64::SHRNv8i16_shift: |
| 11216 | case AArch64::SQRSHRNv8i16_shift: |
| 11217 | case AArch64::SQRSHRUNv8i16_shift: |
| 11218 | case AArch64::SQSHRNv8i16_shift: |
| 11219 | case AArch64::SQSHRUNv8i16_shift: |
| 11220 | case AArch64::UQRSHRNv8i16_shift: |
| 11221 | case AArch64::UQSHRNv8i16_shift: { |
| 11222 | // op: Rd |
| 11223 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11224 | op &= UINT64_C(31); |
| 11225 | Value |= op; |
| 11226 | // op: Rn |
| 11227 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11228 | op &= UINT64_C(31); |
| 11229 | op <<= 5; |
| 11230 | Value |= op; |
| 11231 | // op: imm |
| 11232 | op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| 11233 | op &= UINT64_C(15); |
| 11234 | op <<= 16; |
| 11235 | Value |= op; |
| 11236 | break; |
| 11237 | } |
| 11238 | case AArch64::SRIv2i32_shift: |
| 11239 | case AArch64::SRIv4i32_shift: |
| 11240 | case AArch64::SRSRAv2i32_shift: |
| 11241 | case AArch64::SRSRAv4i32_shift: |
| 11242 | case AArch64::SSRAv2i32_shift: |
| 11243 | case AArch64::SSRAv4i32_shift: |
| 11244 | case AArch64::URSRAv2i32_shift: |
| 11245 | case AArch64::URSRAv4i32_shift: |
| 11246 | case AArch64::USRAv2i32_shift: |
| 11247 | case AArch64::USRAv4i32_shift: { |
| 11248 | // op: Rd |
| 11249 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11250 | op &= UINT64_C(31); |
| 11251 | Value |= op; |
| 11252 | // op: Rn |
| 11253 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11254 | op &= UINT64_C(31); |
| 11255 | op <<= 5; |
| 11256 | Value |= op; |
| 11257 | // op: imm |
| 11258 | op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| 11259 | op &= UINT64_C(31); |
| 11260 | op <<= 16; |
| 11261 | Value |= op; |
| 11262 | break; |
| 11263 | } |
| 11264 | case AArch64::RSHRNv4i32_shift: |
| 11265 | case AArch64::SHRNv4i32_shift: |
| 11266 | case AArch64::SQRSHRNv4i32_shift: |
| 11267 | case AArch64::SQRSHRUNv4i32_shift: |
| 11268 | case AArch64::SQSHRNv4i32_shift: |
| 11269 | case AArch64::SQSHRUNv4i32_shift: |
| 11270 | case AArch64::UQRSHRNv4i32_shift: |
| 11271 | case AArch64::UQSHRNv4i32_shift: { |
| 11272 | // op: Rd |
| 11273 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11274 | op &= UINT64_C(31); |
| 11275 | Value |= op; |
| 11276 | // op: Rn |
| 11277 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11278 | op &= UINT64_C(31); |
| 11279 | op <<= 5; |
| 11280 | Value |= op; |
| 11281 | // op: imm |
| 11282 | op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| 11283 | op &= UINT64_C(31); |
| 11284 | op <<= 16; |
| 11285 | Value |= op; |
| 11286 | break; |
| 11287 | } |
| 11288 | case AArch64::SRId: |
| 11289 | case AArch64::SRIv2i64_shift: |
| 11290 | case AArch64::SRSRAd: |
| 11291 | case AArch64::SRSRAv2i64_shift: |
| 11292 | case AArch64::SSRAd: |
| 11293 | case AArch64::SSRAv2i64_shift: |
| 11294 | case AArch64::URSRAd: |
| 11295 | case AArch64::URSRAv2i64_shift: |
| 11296 | case AArch64::USRAd: |
| 11297 | case AArch64::USRAv2i64_shift: { |
| 11298 | // op: Rd |
| 11299 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11300 | op &= UINT64_C(31); |
| 11301 | Value |= op; |
| 11302 | // op: Rn |
| 11303 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11304 | op &= UINT64_C(31); |
| 11305 | op <<= 5; |
| 11306 | Value |= op; |
| 11307 | // op: imm |
| 11308 | op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| 11309 | op &= UINT64_C(63); |
| 11310 | op <<= 16; |
| 11311 | Value |= op; |
| 11312 | break; |
| 11313 | } |
| 11314 | case AArch64::SRIv16i8_shift: |
| 11315 | case AArch64::SRIv8i8_shift: |
| 11316 | case AArch64::SRSRAv16i8_shift: |
| 11317 | case AArch64::SRSRAv8i8_shift: |
| 11318 | case AArch64::SSRAv16i8_shift: |
| 11319 | case AArch64::SSRAv8i8_shift: |
| 11320 | case AArch64::URSRAv16i8_shift: |
| 11321 | case AArch64::URSRAv8i8_shift: |
| 11322 | case AArch64::USRAv16i8_shift: |
| 11323 | case AArch64::USRAv8i8_shift: { |
| 11324 | // op: Rd |
| 11325 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11326 | op &= UINT64_C(31); |
| 11327 | Value |= op; |
| 11328 | // op: Rn |
| 11329 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11330 | op &= UINT64_C(31); |
| 11331 | op <<= 5; |
| 11332 | Value |= op; |
| 11333 | // op: imm |
| 11334 | op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| 11335 | op &= UINT64_C(7); |
| 11336 | op <<= 16; |
| 11337 | Value |= op; |
| 11338 | break; |
| 11339 | } |
| 11340 | case AArch64::INSvi64gpr: { |
| 11341 | // op: Rd |
| 11342 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11343 | op &= UINT64_C(31); |
| 11344 | Value |= op; |
| 11345 | // op: Rn |
| 11346 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11347 | op &= UINT64_C(31); |
| 11348 | op <<= 5; |
| 11349 | Value |= op; |
| 11350 | // op: idx |
| 11351 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11352 | op &= UINT64_C(1); |
| 11353 | op <<= 20; |
| 11354 | Value |= op; |
| 11355 | break; |
| 11356 | } |
| 11357 | case AArch64::INSvi64lane: { |
| 11358 | // op: Rd |
| 11359 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11360 | op &= UINT64_C(31); |
| 11361 | Value |= op; |
| 11362 | // op: Rn |
| 11363 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11364 | op &= UINT64_C(31); |
| 11365 | op <<= 5; |
| 11366 | Value |= op; |
| 11367 | // op: idx |
| 11368 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11369 | op &= UINT64_C(1); |
| 11370 | op <<= 20; |
| 11371 | Value |= op; |
| 11372 | // op: idx2 |
| 11373 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 11374 | op &= UINT64_C(1); |
| 11375 | op <<= 14; |
| 11376 | Value |= op; |
| 11377 | break; |
| 11378 | } |
| 11379 | case AArch64::INSvi8gpr: { |
| 11380 | // op: Rd |
| 11381 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11382 | op &= UINT64_C(31); |
| 11383 | Value |= op; |
| 11384 | // op: Rn |
| 11385 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11386 | op &= UINT64_C(31); |
| 11387 | op <<= 5; |
| 11388 | Value |= op; |
| 11389 | // op: idx |
| 11390 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11391 | op &= UINT64_C(15); |
| 11392 | op <<= 17; |
| 11393 | Value |= op; |
| 11394 | break; |
| 11395 | } |
| 11396 | case AArch64::INSvi8lane: { |
| 11397 | // op: Rd |
| 11398 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11399 | op &= UINT64_C(31); |
| 11400 | Value |= op; |
| 11401 | // op: Rn |
| 11402 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11403 | op &= UINT64_C(31); |
| 11404 | op <<= 5; |
| 11405 | Value |= op; |
| 11406 | // op: idx |
| 11407 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11408 | op &= UINT64_C(15); |
| 11409 | op <<= 17; |
| 11410 | Value |= op; |
| 11411 | // op: idx2 |
| 11412 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 11413 | op &= UINT64_C(15); |
| 11414 | op <<= 11; |
| 11415 | Value |= op; |
| 11416 | break; |
| 11417 | } |
| 11418 | case AArch64::INSvi32gpr: { |
| 11419 | // op: Rd |
| 11420 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11421 | op &= UINT64_C(31); |
| 11422 | Value |= op; |
| 11423 | // op: Rn |
| 11424 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11425 | op &= UINT64_C(31); |
| 11426 | op <<= 5; |
| 11427 | Value |= op; |
| 11428 | // op: idx |
| 11429 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11430 | op &= UINT64_C(3); |
| 11431 | op <<= 19; |
| 11432 | Value |= op; |
| 11433 | break; |
| 11434 | } |
| 11435 | case AArch64::INSvi32lane: { |
| 11436 | // op: Rd |
| 11437 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11438 | op &= UINT64_C(31); |
| 11439 | Value |= op; |
| 11440 | // op: Rn |
| 11441 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11442 | op &= UINT64_C(31); |
| 11443 | op <<= 5; |
| 11444 | Value |= op; |
| 11445 | // op: idx |
| 11446 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11447 | op &= UINT64_C(3); |
| 11448 | op <<= 19; |
| 11449 | Value |= op; |
| 11450 | // op: idx2 |
| 11451 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 11452 | op &= UINT64_C(3); |
| 11453 | op <<= 13; |
| 11454 | Value |= op; |
| 11455 | break; |
| 11456 | } |
| 11457 | case AArch64::INSvi16gpr: { |
| 11458 | // op: Rd |
| 11459 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11460 | op &= UINT64_C(31); |
| 11461 | Value |= op; |
| 11462 | // op: Rn |
| 11463 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11464 | op &= UINT64_C(31); |
| 11465 | op <<= 5; |
| 11466 | Value |= op; |
| 11467 | // op: idx |
| 11468 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11469 | op &= UINT64_C(7); |
| 11470 | op <<= 18; |
| 11471 | Value |= op; |
| 11472 | break; |
| 11473 | } |
| 11474 | case AArch64::INSvi16lane: { |
| 11475 | // op: Rd |
| 11476 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11477 | op &= UINT64_C(31); |
| 11478 | Value |= op; |
| 11479 | // op: Rn |
| 11480 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11481 | op &= UINT64_C(31); |
| 11482 | op <<= 5; |
| 11483 | Value |= op; |
| 11484 | // op: idx |
| 11485 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11486 | op &= UINT64_C(7); |
| 11487 | op <<= 18; |
| 11488 | Value |= op; |
| 11489 | // op: idx2 |
| 11490 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 11491 | op &= UINT64_C(7); |
| 11492 | op <<= 12; |
| 11493 | Value |= op; |
| 11494 | break; |
| 11495 | } |
| 11496 | case AArch64::BICv4i16: |
| 11497 | case AArch64::BICv8i16: |
| 11498 | case AArch64::ORRv4i16: |
| 11499 | case AArch64::ORRv8i16: { |
| 11500 | // op: Rd |
| 11501 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11502 | op &= UINT64_C(31); |
| 11503 | Value |= op; |
| 11504 | // op: imm8 |
| 11505 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11506 | Value |= (op & UINT64_C(224)) << 11; |
| 11507 | Value |= (op & UINT64_C(31)) << 5; |
| 11508 | // op: shift |
| 11509 | op = getVecShifterOpValue(MI, 3, Fixups, STI); |
| 11510 | op &= UINT64_C(1); |
| 11511 | op <<= 13; |
| 11512 | Value |= op; |
| 11513 | break; |
| 11514 | } |
| 11515 | case AArch64::BICv2i32: |
| 11516 | case AArch64::BICv4i32: |
| 11517 | case AArch64::ORRv2i32: |
| 11518 | case AArch64::ORRv4i32: { |
| 11519 | // op: Rd |
| 11520 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11521 | op &= UINT64_C(31); |
| 11522 | Value |= op; |
| 11523 | // op: imm8 |
| 11524 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11525 | Value |= (op & UINT64_C(224)) << 11; |
| 11526 | Value |= (op & UINT64_C(31)) << 5; |
| 11527 | // op: shift |
| 11528 | op = getVecShifterOpValue(MI, 3, Fixups, STI); |
| 11529 | op &= UINT64_C(3); |
| 11530 | op <<= 13; |
| 11531 | Value |= op; |
| 11532 | break; |
| 11533 | } |
| 11534 | case AArch64::DECP_XP_B: |
| 11535 | case AArch64::DECP_XP_D: |
| 11536 | case AArch64::DECP_XP_H: |
| 11537 | case AArch64::DECP_XP_S: |
| 11538 | case AArch64::INCP_XP_B: |
| 11539 | case AArch64::INCP_XP_D: |
| 11540 | case AArch64::INCP_XP_H: |
| 11541 | case AArch64::INCP_XP_S: |
| 11542 | case AArch64::SQDECP_XPWd_B: |
| 11543 | case AArch64::SQDECP_XPWd_D: |
| 11544 | case AArch64::SQDECP_XPWd_H: |
| 11545 | case AArch64::SQDECP_XPWd_S: |
| 11546 | case AArch64::SQDECP_XP_B: |
| 11547 | case AArch64::SQDECP_XP_D: |
| 11548 | case AArch64::SQDECP_XP_H: |
| 11549 | case AArch64::SQDECP_XP_S: |
| 11550 | case AArch64::SQINCP_XPWd_B: |
| 11551 | case AArch64::SQINCP_XPWd_D: |
| 11552 | case AArch64::SQINCP_XPWd_H: |
| 11553 | case AArch64::SQINCP_XPWd_S: |
| 11554 | case AArch64::SQINCP_XP_B: |
| 11555 | case AArch64::SQINCP_XP_D: |
| 11556 | case AArch64::SQINCP_XP_H: |
| 11557 | case AArch64::SQINCP_XP_S: |
| 11558 | case AArch64::UQDECP_WP_B: |
| 11559 | case AArch64::UQDECP_WP_D: |
| 11560 | case AArch64::UQDECP_WP_H: |
| 11561 | case AArch64::UQDECP_WP_S: |
| 11562 | case AArch64::UQDECP_XP_B: |
| 11563 | case AArch64::UQDECP_XP_D: |
| 11564 | case AArch64::UQDECP_XP_H: |
| 11565 | case AArch64::UQDECP_XP_S: |
| 11566 | case AArch64::UQINCP_WP_B: |
| 11567 | case AArch64::UQINCP_WP_D: |
| 11568 | case AArch64::UQINCP_WP_H: |
| 11569 | case AArch64::UQINCP_WP_S: |
| 11570 | case AArch64::UQINCP_XP_B: |
| 11571 | case AArch64::UQINCP_XP_D: |
| 11572 | case AArch64::UQINCP_XP_H: |
| 11573 | case AArch64::UQINCP_XP_S: { |
| 11574 | // op: Rdn |
| 11575 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11576 | op &= UINT64_C(31); |
| 11577 | Value |= op; |
| 11578 | // op: Pg |
| 11579 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11580 | op &= UINT64_C(15); |
| 11581 | op <<= 5; |
| 11582 | Value |= op; |
| 11583 | break; |
| 11584 | } |
| 11585 | case AArch64::DECB_XPiI: |
| 11586 | case AArch64::DECD_XPiI: |
| 11587 | case AArch64::DECH_XPiI: |
| 11588 | case AArch64::DECW_XPiI: |
| 11589 | case AArch64::INCB_XPiI: |
| 11590 | case AArch64::INCD_XPiI: |
| 11591 | case AArch64::INCH_XPiI: |
| 11592 | case AArch64::INCW_XPiI: |
| 11593 | case AArch64::SQDECB_XPiI: |
| 11594 | case AArch64::SQDECB_XPiWdI: |
| 11595 | case AArch64::SQDECD_XPiI: |
| 11596 | case AArch64::SQDECD_XPiWdI: |
| 11597 | case AArch64::SQDECH_XPiI: |
| 11598 | case AArch64::SQDECH_XPiWdI: |
| 11599 | case AArch64::SQDECW_XPiI: |
| 11600 | case AArch64::SQDECW_XPiWdI: |
| 11601 | case AArch64::SQINCB_XPiI: |
| 11602 | case AArch64::SQINCB_XPiWdI: |
| 11603 | case AArch64::SQINCD_XPiI: |
| 11604 | case AArch64::SQINCD_XPiWdI: |
| 11605 | case AArch64::SQINCH_XPiI: |
| 11606 | case AArch64::SQINCH_XPiWdI: |
| 11607 | case AArch64::SQINCW_XPiI: |
| 11608 | case AArch64::SQINCW_XPiWdI: |
| 11609 | case AArch64::UQDECB_WPiI: |
| 11610 | case AArch64::UQDECB_XPiI: |
| 11611 | case AArch64::UQDECD_WPiI: |
| 11612 | case AArch64::UQDECD_XPiI: |
| 11613 | case AArch64::UQDECH_WPiI: |
| 11614 | case AArch64::UQDECH_XPiI: |
| 11615 | case AArch64::UQDECW_WPiI: |
| 11616 | case AArch64::UQDECW_XPiI: |
| 11617 | case AArch64::UQINCB_WPiI: |
| 11618 | case AArch64::UQINCB_XPiI: |
| 11619 | case AArch64::UQINCD_WPiI: |
| 11620 | case AArch64::UQINCD_XPiI: |
| 11621 | case AArch64::UQINCH_WPiI: |
| 11622 | case AArch64::UQINCH_XPiI: |
| 11623 | case AArch64::UQINCW_WPiI: |
| 11624 | case AArch64::UQINCW_XPiI: { |
| 11625 | // op: Rdn |
| 11626 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11627 | op &= UINT64_C(31); |
| 11628 | Value |= op; |
| 11629 | // op: pattern |
| 11630 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11631 | op &= UINT64_C(31); |
| 11632 | op <<= 5; |
| 11633 | Value |= op; |
| 11634 | // op: imm4 |
| 11635 | op = getSVEIncDecImm(MI, 3, Fixups, STI); |
| 11636 | op &= UINT64_C(15); |
| 11637 | op <<= 16; |
| 11638 | Value |= op; |
| 11639 | break; |
| 11640 | } |
| 11641 | case AArch64::CTERMEQ_WW: |
| 11642 | case AArch64::CTERMEQ_XX: |
| 11643 | case AArch64::CTERMNE_WW: |
| 11644 | case AArch64::CTERMNE_XX: |
| 11645 | case AArch64::FCMPDrr: |
| 11646 | case AArch64::FCMPEDrr: |
| 11647 | case AArch64::FCMPEHrr: |
| 11648 | case AArch64::FCMPESrr: |
| 11649 | case AArch64::FCMPHrr: |
| 11650 | case AArch64::FCMPSrr: { |
| 11651 | // op: Rm |
| 11652 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11653 | op &= UINT64_C(31); |
| 11654 | op <<= 16; |
| 11655 | Value |= op; |
| 11656 | // op: Rn |
| 11657 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11658 | op &= UINT64_C(31); |
| 11659 | op <<= 5; |
| 11660 | Value |= op; |
| 11661 | break; |
| 11662 | } |
| 11663 | case AArch64::INDEX_IR_B: |
| 11664 | case AArch64::INDEX_IR_D: |
| 11665 | case AArch64::INDEX_IR_H: |
| 11666 | case AArch64::INDEX_IR_S: { |
| 11667 | // op: Rm |
| 11668 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11669 | op &= UINT64_C(31); |
| 11670 | op <<= 16; |
| 11671 | Value |= op; |
| 11672 | // op: Zd |
| 11673 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11674 | op &= UINT64_C(31); |
| 11675 | Value |= op; |
| 11676 | // op: imm5 |
| 11677 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11678 | op &= UINT64_C(31); |
| 11679 | op <<= 5; |
| 11680 | Value |= op; |
| 11681 | break; |
| 11682 | } |
| 11683 | case AArch64::INSR_ZR_B: |
| 11684 | case AArch64::INSR_ZR_D: |
| 11685 | case AArch64::INSR_ZR_H: |
| 11686 | case AArch64::INSR_ZR_S: { |
| 11687 | // op: Rm |
| 11688 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11689 | op &= UINT64_C(31); |
| 11690 | op <<= 5; |
| 11691 | Value |= op; |
| 11692 | // op: Zdn |
| 11693 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11694 | op &= UINT64_C(31); |
| 11695 | Value |= op; |
| 11696 | break; |
| 11697 | } |
| 11698 | case AArch64::PRFB_PRR: |
| 11699 | case AArch64::PRFD_PRR: |
| 11700 | case AArch64::PRFH_PRR: |
| 11701 | case AArch64::PRFS_PRR: { |
| 11702 | // op: Rm |
| 11703 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11704 | op &= UINT64_C(31); |
| 11705 | op <<= 16; |
| 11706 | Value |= op; |
| 11707 | // op: Rn |
| 11708 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11709 | op &= UINT64_C(31); |
| 11710 | op <<= 5; |
| 11711 | Value |= op; |
| 11712 | // op: Pg |
| 11713 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11714 | op &= UINT64_C(7); |
| 11715 | op <<= 10; |
| 11716 | Value |= op; |
| 11717 | // op: prfop |
| 11718 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11719 | op &= UINT64_C(15); |
| 11720 | Value |= op; |
| 11721 | break; |
| 11722 | } |
| 11723 | case AArch64::BLR: |
| 11724 | case AArch64::BLRAAZ: |
| 11725 | case AArch64::BLRABZ: |
| 11726 | case AArch64::BR: |
| 11727 | case AArch64::BRAAZ: |
| 11728 | case AArch64::BRABZ: |
| 11729 | case AArch64::RET: |
| 11730 | case AArch64::SETF16: |
| 11731 | case AArch64::SETF8: { |
| 11732 | // op: Rn |
| 11733 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11734 | op &= UINT64_C(31); |
| 11735 | op <<= 5; |
| 11736 | Value |= op; |
| 11737 | break; |
| 11738 | } |
| 11739 | case AArch64::BLRAA: |
| 11740 | case AArch64::BLRAB: |
| 11741 | case AArch64::BRAA: |
| 11742 | case AArch64::BRAB: { |
| 11743 | // op: Rn |
| 11744 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11745 | op &= UINT64_C(31); |
| 11746 | op <<= 5; |
| 11747 | Value |= op; |
| 11748 | // op: Rm |
| 11749 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11750 | op &= UINT64_C(31); |
| 11751 | Value |= op; |
| 11752 | break; |
| 11753 | } |
| 11754 | case AArch64::CCMNWr: |
| 11755 | case AArch64::CCMNXr: |
| 11756 | case AArch64::CCMPWr: |
| 11757 | case AArch64::CCMPXr: |
| 11758 | case AArch64::FCCMPDrr: |
| 11759 | case AArch64::FCCMPEDrr: |
| 11760 | case AArch64::FCCMPEHrr: |
| 11761 | case AArch64::FCCMPESrr: |
| 11762 | case AArch64::FCCMPHrr: |
| 11763 | case AArch64::FCCMPSrr: { |
| 11764 | // op: Rn |
| 11765 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11766 | op &= UINT64_C(31); |
| 11767 | op <<= 5; |
| 11768 | Value |= op; |
| 11769 | // op: Rm |
| 11770 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11771 | op &= UINT64_C(31); |
| 11772 | op <<= 16; |
| 11773 | Value |= op; |
| 11774 | // op: nzcv |
| 11775 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11776 | op &= UINT64_C(15); |
| 11777 | Value |= op; |
| 11778 | // op: cond |
| 11779 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11780 | op &= UINT64_C(15); |
| 11781 | op <<= 12; |
| 11782 | Value |= op; |
| 11783 | break; |
| 11784 | } |
| 11785 | case AArch64::CCMNWi: |
| 11786 | case AArch64::CCMNXi: |
| 11787 | case AArch64::CCMPWi: |
| 11788 | case AArch64::CCMPXi: { |
| 11789 | // op: Rn |
| 11790 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11791 | op &= UINT64_C(31); |
| 11792 | op <<= 5; |
| 11793 | Value |= op; |
| 11794 | // op: imm |
| 11795 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11796 | op &= UINT64_C(31); |
| 11797 | op <<= 16; |
| 11798 | Value |= op; |
| 11799 | // op: nzcv |
| 11800 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11801 | op &= UINT64_C(15); |
| 11802 | Value |= op; |
| 11803 | // op: cond |
| 11804 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11805 | op &= UINT64_C(15); |
| 11806 | op <<= 12; |
| 11807 | Value |= op; |
| 11808 | break; |
| 11809 | } |
| 11810 | case AArch64::RMIF: { |
| 11811 | // op: Rn |
| 11812 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11813 | op &= UINT64_C(31); |
| 11814 | op <<= 5; |
| 11815 | Value |= op; |
| 11816 | // op: imm |
| 11817 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11818 | op &= UINT64_C(63); |
| 11819 | op <<= 15; |
| 11820 | Value |= op; |
| 11821 | // op: mask |
| 11822 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11823 | op &= UINT64_C(15); |
| 11824 | Value |= op; |
| 11825 | break; |
| 11826 | } |
| 11827 | case AArch64::FCMPDri: |
| 11828 | case AArch64::FCMPEDri: |
| 11829 | case AArch64::FCMPEHri: |
| 11830 | case AArch64::FCMPESri: |
| 11831 | case AArch64::FCMPHri: |
| 11832 | case AArch64::FCMPSri: { |
| 11833 | // op: Rn |
| 11834 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11835 | op &= UINT64_C(31); |
| 11836 | op <<= 5; |
| 11837 | Value |= op; |
| 11838 | Value = fixOneOperandFPComparison(MI, Value, STI); |
| 11839 | break; |
| 11840 | } |
| 11841 | case AArch64::LDAPRB: |
| 11842 | case AArch64::LDAPRH: |
| 11843 | case AArch64::LDAPRW: |
| 11844 | case AArch64::LDAPRX: |
| 11845 | case AArch64::LDGM: |
| 11846 | case AArch64::STGM: |
| 11847 | case AArch64::STZGM: { |
| 11848 | // op: Rn |
| 11849 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11850 | op &= UINT64_C(31); |
| 11851 | op <<= 5; |
| 11852 | Value |= op; |
| 11853 | // op: Rt |
| 11854 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11855 | op &= UINT64_C(31); |
| 11856 | Value |= op; |
| 11857 | break; |
| 11858 | } |
| 11859 | case AArch64::ST2GOffset: |
| 11860 | case AArch64::STGOffset: |
| 11861 | case AArch64::STZ2GOffset: |
| 11862 | case AArch64::STZGOffset: { |
| 11863 | // op: Rn |
| 11864 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11865 | op &= UINT64_C(31); |
| 11866 | op <<= 5; |
| 11867 | Value |= op; |
| 11868 | // op: Rt |
| 11869 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11870 | op &= UINT64_C(31); |
| 11871 | Value |= op; |
| 11872 | // op: offset |
| 11873 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11874 | op &= UINT64_C(511); |
| 11875 | op <<= 12; |
| 11876 | Value |= op; |
| 11877 | break; |
| 11878 | } |
| 11879 | case AArch64::DUP_ZR_B: |
| 11880 | case AArch64::DUP_ZR_D: |
| 11881 | case AArch64::DUP_ZR_H: |
| 11882 | case AArch64::DUP_ZR_S: { |
| 11883 | // op: Rn |
| 11884 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11885 | op &= UINT64_C(31); |
| 11886 | op <<= 5; |
| 11887 | Value |= op; |
| 11888 | // op: Zd |
| 11889 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11890 | op &= UINT64_C(31); |
| 11891 | Value |= op; |
| 11892 | break; |
| 11893 | } |
| 11894 | case AArch64::INDEX_RI_B: |
| 11895 | case AArch64::INDEX_RI_D: |
| 11896 | case AArch64::INDEX_RI_H: |
| 11897 | case AArch64::INDEX_RI_S: { |
| 11898 | // op: Rn |
| 11899 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11900 | op &= UINT64_C(31); |
| 11901 | op <<= 5; |
| 11902 | Value |= op; |
| 11903 | // op: Zd |
| 11904 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11905 | op &= UINT64_C(31); |
| 11906 | Value |= op; |
| 11907 | // op: imm5 |
| 11908 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11909 | op &= UINT64_C(31); |
| 11910 | op <<= 16; |
| 11911 | Value |= op; |
| 11912 | break; |
| 11913 | } |
| 11914 | case AArch64::LDR_ZXI: |
| 11915 | case AArch64::STR_ZXI: { |
| 11916 | // op: Rn |
| 11917 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11918 | op &= UINT64_C(31); |
| 11919 | op <<= 5; |
| 11920 | Value |= op; |
| 11921 | // op: Zt |
| 11922 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11923 | op &= UINT64_C(31); |
| 11924 | Value |= op; |
| 11925 | // op: imm9 |
| 11926 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11927 | Value |= (op & UINT64_C(504)) << 13; |
| 11928 | Value |= (op & UINT64_C(7)) << 10; |
| 11929 | break; |
| 11930 | } |
| 11931 | case AArch64::PRFB_PRI: |
| 11932 | case AArch64::PRFD_PRI: |
| 11933 | case AArch64::PRFH_PRI: |
| 11934 | case AArch64::PRFW_PRI: { |
| 11935 | // op: Rn |
| 11936 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11937 | op &= UINT64_C(31); |
| 11938 | op <<= 5; |
| 11939 | Value |= op; |
| 11940 | // op: Pg |
| 11941 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11942 | op &= UINT64_C(7); |
| 11943 | op <<= 10; |
| 11944 | Value |= op; |
| 11945 | // op: imm6 |
| 11946 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11947 | op &= UINT64_C(63); |
| 11948 | op <<= 16; |
| 11949 | Value |= op; |
| 11950 | // op: prfop |
| 11951 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 11952 | op &= UINT64_C(15); |
| 11953 | Value |= op; |
| 11954 | break; |
| 11955 | } |
| 11956 | case AArch64::LDG: |
| 11957 | case AArch64::ST2GPostIndex: |
| 11958 | case AArch64::ST2GPreIndex: |
| 11959 | case AArch64::STGPostIndex: |
| 11960 | case AArch64::STGPreIndex: |
| 11961 | case AArch64::STZ2GPostIndex: |
| 11962 | case AArch64::STZ2GPreIndex: |
| 11963 | case AArch64::STZGPostIndex: |
| 11964 | case AArch64::STZGPreIndex: { |
| 11965 | // op: Rn |
| 11966 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 11967 | op &= UINT64_C(31); |
| 11968 | op <<= 5; |
| 11969 | Value |= op; |
| 11970 | // op: Rt |
| 11971 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 11972 | op &= UINT64_C(31); |
| 11973 | Value |= op; |
| 11974 | // op: offset |
| 11975 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 11976 | op &= UINT64_C(511); |
| 11977 | op <<= 12; |
| 11978 | Value |= op; |
| 11979 | break; |
| 11980 | } |
| 11981 | case AArch64::LDADDAB: |
| 11982 | case AArch64::LDADDAH: |
| 11983 | case AArch64::LDADDALB: |
| 11984 | case AArch64::LDADDALH: |
| 11985 | case AArch64::LDADDALW: |
| 11986 | case AArch64::LDADDALX: |
| 11987 | case AArch64::LDADDAW: |
| 11988 | case AArch64::LDADDAX: |
| 11989 | case AArch64::LDADDB: |
| 11990 | case AArch64::LDADDH: |
| 11991 | case AArch64::LDADDLB: |
| 11992 | case AArch64::LDADDLH: |
| 11993 | case AArch64::LDADDLW: |
| 11994 | case AArch64::LDADDLX: |
| 11995 | case AArch64::LDADDW: |
| 11996 | case AArch64::LDADDX: |
| 11997 | case AArch64::LDCLRAB: |
| 11998 | case AArch64::LDCLRAH: |
| 11999 | case AArch64::LDCLRALB: |
| 12000 | case AArch64::LDCLRALH: |
| 12001 | case AArch64::LDCLRALW: |
| 12002 | case AArch64::LDCLRALX: |
| 12003 | case AArch64::LDCLRAW: |
| 12004 | case AArch64::LDCLRAX: |
| 12005 | case AArch64::LDCLRB: |
| 12006 | case AArch64::LDCLRH: |
| 12007 | case AArch64::LDCLRLB: |
| 12008 | case AArch64::LDCLRLH: |
| 12009 | case AArch64::LDCLRLW: |
| 12010 | case AArch64::LDCLRLX: |
| 12011 | case AArch64::LDCLRW: |
| 12012 | case AArch64::LDCLRX: |
| 12013 | case AArch64::LDEORAB: |
| 12014 | case AArch64::LDEORAH: |
| 12015 | case AArch64::LDEORALB: |
| 12016 | case AArch64::LDEORALH: |
| 12017 | case AArch64::LDEORALW: |
| 12018 | case AArch64::LDEORALX: |
| 12019 | case AArch64::LDEORAW: |
| 12020 | case AArch64::LDEORAX: |
| 12021 | case AArch64::LDEORB: |
| 12022 | case AArch64::LDEORH: |
| 12023 | case AArch64::LDEORLB: |
| 12024 | case AArch64::LDEORLH: |
| 12025 | case AArch64::LDEORLW: |
| 12026 | case AArch64::LDEORLX: |
| 12027 | case AArch64::LDEORW: |
| 12028 | case AArch64::LDEORX: |
| 12029 | case AArch64::LDSETAB: |
| 12030 | case AArch64::LDSETAH: |
| 12031 | case AArch64::LDSETALB: |
| 12032 | case AArch64::LDSETALH: |
| 12033 | case AArch64::LDSETALW: |
| 12034 | case AArch64::LDSETALX: |
| 12035 | case AArch64::LDSETAW: |
| 12036 | case AArch64::LDSETAX: |
| 12037 | case AArch64::LDSETB: |
| 12038 | case AArch64::LDSETH: |
| 12039 | case AArch64::LDSETLB: |
| 12040 | case AArch64::LDSETLH: |
| 12041 | case AArch64::LDSETLW: |
| 12042 | case AArch64::LDSETLX: |
| 12043 | case AArch64::LDSETW: |
| 12044 | case AArch64::LDSETX: |
| 12045 | case AArch64::LDSMAXAB: |
| 12046 | case AArch64::LDSMAXAH: |
| 12047 | case AArch64::LDSMAXALB: |
| 12048 | case AArch64::LDSMAXALH: |
| 12049 | case AArch64::LDSMAXALW: |
| 12050 | case AArch64::LDSMAXALX: |
| 12051 | case AArch64::LDSMAXAW: |
| 12052 | case AArch64::LDSMAXAX: |
| 12053 | case AArch64::LDSMAXB: |
| 12054 | case AArch64::LDSMAXH: |
| 12055 | case AArch64::LDSMAXLB: |
| 12056 | case AArch64::LDSMAXLH: |
| 12057 | case AArch64::LDSMAXLW: |
| 12058 | case AArch64::LDSMAXLX: |
| 12059 | case AArch64::LDSMAXW: |
| 12060 | case AArch64::LDSMAXX: |
| 12061 | case AArch64::LDSMINAB: |
| 12062 | case AArch64::LDSMINAH: |
| 12063 | case AArch64::LDSMINALB: |
| 12064 | case AArch64::LDSMINALH: |
| 12065 | case AArch64::LDSMINALW: |
| 12066 | case AArch64::LDSMINALX: |
| 12067 | case AArch64::LDSMINAW: |
| 12068 | case AArch64::LDSMINAX: |
| 12069 | case AArch64::LDSMINB: |
| 12070 | case AArch64::LDSMINH: |
| 12071 | case AArch64::LDSMINLB: |
| 12072 | case AArch64::LDSMINLH: |
| 12073 | case AArch64::LDSMINLW: |
| 12074 | case AArch64::LDSMINLX: |
| 12075 | case AArch64::LDSMINW: |
| 12076 | case AArch64::LDSMINX: |
| 12077 | case AArch64::LDUMAXAB: |
| 12078 | case AArch64::LDUMAXAH: |
| 12079 | case AArch64::LDUMAXALB: |
| 12080 | case AArch64::LDUMAXALH: |
| 12081 | case AArch64::LDUMAXALW: |
| 12082 | case AArch64::LDUMAXALX: |
| 12083 | case AArch64::LDUMAXAW: |
| 12084 | case AArch64::LDUMAXAX: |
| 12085 | case AArch64::LDUMAXB: |
| 12086 | case AArch64::LDUMAXH: |
| 12087 | case AArch64::LDUMAXLB: |
| 12088 | case AArch64::LDUMAXLH: |
| 12089 | case AArch64::LDUMAXLW: |
| 12090 | case AArch64::LDUMAXLX: |
| 12091 | case AArch64::LDUMAXW: |
| 12092 | case AArch64::LDUMAXX: |
| 12093 | case AArch64::LDUMINAB: |
| 12094 | case AArch64::LDUMINAH: |
| 12095 | case AArch64::LDUMINALB: |
| 12096 | case AArch64::LDUMINALH: |
| 12097 | case AArch64::LDUMINALW: |
| 12098 | case AArch64::LDUMINALX: |
| 12099 | case AArch64::LDUMINAW: |
| 12100 | case AArch64::LDUMINAX: |
| 12101 | case AArch64::LDUMINB: |
| 12102 | case AArch64::LDUMINH: |
| 12103 | case AArch64::LDUMINLB: |
| 12104 | case AArch64::LDUMINLH: |
| 12105 | case AArch64::LDUMINLW: |
| 12106 | case AArch64::LDUMINLX: |
| 12107 | case AArch64::LDUMINW: |
| 12108 | case AArch64::LDUMINX: |
| 12109 | case AArch64::SWPAB: |
| 12110 | case AArch64::SWPAH: |
| 12111 | case AArch64::SWPALB: |
| 12112 | case AArch64::SWPALH: |
| 12113 | case AArch64::SWPALW: |
| 12114 | case AArch64::SWPALX: |
| 12115 | case AArch64::SWPAW: |
| 12116 | case AArch64::SWPAX: |
| 12117 | case AArch64::SWPB: |
| 12118 | case AArch64::SWPH: |
| 12119 | case AArch64::SWPLB: |
| 12120 | case AArch64::SWPLH: |
| 12121 | case AArch64::SWPLW: |
| 12122 | case AArch64::SWPLX: |
| 12123 | case AArch64::SWPW: |
| 12124 | case AArch64::SWPX: { |
| 12125 | // op: Rs |
| 12126 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12127 | op &= UINT64_C(31); |
| 12128 | op <<= 16; |
| 12129 | Value |= op; |
| 12130 | // op: Rn |
| 12131 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12132 | op &= UINT64_C(31); |
| 12133 | op <<= 5; |
| 12134 | Value |= op; |
| 12135 | // op: Rt |
| 12136 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12137 | op &= UINT64_C(31); |
| 12138 | Value |= op; |
| 12139 | break; |
| 12140 | } |
| 12141 | case AArch64::CASAB: |
| 12142 | case AArch64::CASAH: |
| 12143 | case AArch64::CASALB: |
| 12144 | case AArch64::CASALH: |
| 12145 | case AArch64::CASALW: |
| 12146 | case AArch64::CASALX: |
| 12147 | case AArch64::CASAW: |
| 12148 | case AArch64::CASAX: |
| 12149 | case AArch64::CASB: |
| 12150 | case AArch64::CASH: |
| 12151 | case AArch64::CASLB: |
| 12152 | case AArch64::CASLH: |
| 12153 | case AArch64::CASLW: |
| 12154 | case AArch64::CASLX: |
| 12155 | case AArch64::CASPALW: |
| 12156 | case AArch64::CASPALX: |
| 12157 | case AArch64::CASPAW: |
| 12158 | case AArch64::CASPAX: |
| 12159 | case AArch64::CASPLW: |
| 12160 | case AArch64::CASPLX: |
| 12161 | case AArch64::CASPW: |
| 12162 | case AArch64::CASPX: |
| 12163 | case AArch64::CASW: |
| 12164 | case AArch64::CASX: { |
| 12165 | // op: Rs |
| 12166 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12167 | op &= UINT64_C(31); |
| 12168 | op <<= 16; |
| 12169 | Value |= op; |
| 12170 | // op: Rn |
| 12171 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12172 | op &= UINT64_C(31); |
| 12173 | op <<= 5; |
| 12174 | Value |= op; |
| 12175 | // op: Rt |
| 12176 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12177 | op &= UINT64_C(31); |
| 12178 | Value |= op; |
| 12179 | break; |
| 12180 | } |
| 12181 | case AArch64::TSTART: |
| 12182 | case AArch64::TTEST: |
| 12183 | case AArch64::WFET: |
| 12184 | case AArch64::WFIT: { |
| 12185 | // op: Rt |
| 12186 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12187 | op &= UINT64_C(31); |
| 12188 | Value |= op; |
| 12189 | break; |
| 12190 | } |
| 12191 | case AArch64::LD64B: |
| 12192 | case AArch64::ST64B: { |
| 12193 | // op: Rt |
| 12194 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12195 | op &= UINT64_C(31); |
| 12196 | Value |= op; |
| 12197 | // op: Rn |
| 12198 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12199 | op &= UINT64_C(31); |
| 12200 | op <<= 5; |
| 12201 | Value |= op; |
| 12202 | break; |
| 12203 | } |
| 12204 | case AArch64::LDRBBroW: |
| 12205 | case AArch64::LDRBBroX: |
| 12206 | case AArch64::LDRBroW: |
| 12207 | case AArch64::LDRBroX: |
| 12208 | case AArch64::LDRDroW: |
| 12209 | case AArch64::LDRDroX: |
| 12210 | case AArch64::LDRHHroW: |
| 12211 | case AArch64::LDRHHroX: |
| 12212 | case AArch64::LDRHroW: |
| 12213 | case AArch64::LDRHroX: |
| 12214 | case AArch64::LDRQroW: |
| 12215 | case AArch64::LDRQroX: |
| 12216 | case AArch64::LDRSBWroW: |
| 12217 | case AArch64::LDRSBWroX: |
| 12218 | case AArch64::LDRSBXroW: |
| 12219 | case AArch64::LDRSBXroX: |
| 12220 | case AArch64::LDRSHWroW: |
| 12221 | case AArch64::LDRSHWroX: |
| 12222 | case AArch64::LDRSHXroW: |
| 12223 | case AArch64::LDRSHXroX: |
| 12224 | case AArch64::LDRSWroW: |
| 12225 | case AArch64::LDRSWroX: |
| 12226 | case AArch64::LDRSroW: |
| 12227 | case AArch64::LDRSroX: |
| 12228 | case AArch64::LDRWroW: |
| 12229 | case AArch64::LDRWroX: |
| 12230 | case AArch64::LDRXroW: |
| 12231 | case AArch64::LDRXroX: |
| 12232 | case AArch64::PRFMroW: |
| 12233 | case AArch64::PRFMroX: |
| 12234 | case AArch64::STRBBroW: |
| 12235 | case AArch64::STRBBroX: |
| 12236 | case AArch64::STRBroW: |
| 12237 | case AArch64::STRBroX: |
| 12238 | case AArch64::STRDroW: |
| 12239 | case AArch64::STRDroX: |
| 12240 | case AArch64::STRHHroW: |
| 12241 | case AArch64::STRHHroX: |
| 12242 | case AArch64::STRHroW: |
| 12243 | case AArch64::STRHroX: |
| 12244 | case AArch64::STRQroW: |
| 12245 | case AArch64::STRQroX: |
| 12246 | case AArch64::STRSroW: |
| 12247 | case AArch64::STRSroX: |
| 12248 | case AArch64::STRWroW: |
| 12249 | case AArch64::STRWroX: |
| 12250 | case AArch64::STRXroW: |
| 12251 | case AArch64::STRXroX: { |
| 12252 | // op: Rt |
| 12253 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12254 | op &= UINT64_C(31); |
| 12255 | Value |= op; |
| 12256 | // op: Rn |
| 12257 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12258 | op &= UINT64_C(31); |
| 12259 | op <<= 5; |
| 12260 | Value |= op; |
| 12261 | // op: Rm |
| 12262 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12263 | op &= UINT64_C(31); |
| 12264 | op <<= 16; |
| 12265 | Value |= op; |
| 12266 | // op: extend |
| 12267 | op = getMemExtendOpValue(MI, 3, Fixups, STI); |
| 12268 | Value |= (op & UINT64_C(2)) << 14; |
| 12269 | Value |= (op & UINT64_C(1)) << 12; |
| 12270 | break; |
| 12271 | } |
| 12272 | case AArch64::LDRQui: |
| 12273 | case AArch64::STRQui: { |
| 12274 | // op: Rt |
| 12275 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12276 | op &= UINT64_C(31); |
| 12277 | Value |= op; |
| 12278 | // op: Rn |
| 12279 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12280 | op &= UINT64_C(31); |
| 12281 | op <<= 5; |
| 12282 | Value |= op; |
| 12283 | // op: offset |
| 12284 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale16>(MI, 2, Fixups, STI); |
| 12285 | op &= UINT64_C(4095); |
| 12286 | op <<= 10; |
| 12287 | Value |= op; |
| 12288 | break; |
| 12289 | } |
| 12290 | case AArch64::LDRBBui: |
| 12291 | case AArch64::LDRBui: |
| 12292 | case AArch64::LDRSBWui: |
| 12293 | case AArch64::LDRSBXui: |
| 12294 | case AArch64::STRBBui: |
| 12295 | case AArch64::STRBui: { |
| 12296 | // op: Rt |
| 12297 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12298 | op &= UINT64_C(31); |
| 12299 | Value |= op; |
| 12300 | // op: Rn |
| 12301 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12302 | op &= UINT64_C(31); |
| 12303 | op <<= 5; |
| 12304 | Value |= op; |
| 12305 | // op: offset |
| 12306 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale1>(MI, 2, Fixups, STI); |
| 12307 | op &= UINT64_C(4095); |
| 12308 | op <<= 10; |
| 12309 | Value |= op; |
| 12310 | break; |
| 12311 | } |
| 12312 | case AArch64::LDRHHui: |
| 12313 | case AArch64::LDRHui: |
| 12314 | case AArch64::LDRSHWui: |
| 12315 | case AArch64::LDRSHXui: |
| 12316 | case AArch64::STRHHui: |
| 12317 | case AArch64::STRHui: { |
| 12318 | // op: Rt |
| 12319 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12320 | op &= UINT64_C(31); |
| 12321 | Value |= op; |
| 12322 | // op: Rn |
| 12323 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12324 | op &= UINT64_C(31); |
| 12325 | op <<= 5; |
| 12326 | Value |= op; |
| 12327 | // op: offset |
| 12328 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale2>(MI, 2, Fixups, STI); |
| 12329 | op &= UINT64_C(4095); |
| 12330 | op <<= 10; |
| 12331 | Value |= op; |
| 12332 | break; |
| 12333 | } |
| 12334 | case AArch64::LDRSWui: |
| 12335 | case AArch64::LDRSui: |
| 12336 | case AArch64::LDRWui: |
| 12337 | case AArch64::STRSui: |
| 12338 | case AArch64::STRWui: { |
| 12339 | // op: Rt |
| 12340 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12341 | op &= UINT64_C(31); |
| 12342 | Value |= op; |
| 12343 | // op: Rn |
| 12344 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12345 | op &= UINT64_C(31); |
| 12346 | op <<= 5; |
| 12347 | Value |= op; |
| 12348 | // op: offset |
| 12349 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale4>(MI, 2, Fixups, STI); |
| 12350 | op &= UINT64_C(4095); |
| 12351 | op <<= 10; |
| 12352 | Value |= op; |
| 12353 | break; |
| 12354 | } |
| 12355 | case AArch64::LDRDui: |
| 12356 | case AArch64::LDRXui: |
| 12357 | case AArch64::PRFMui: |
| 12358 | case AArch64::STRDui: |
| 12359 | case AArch64::STRXui: { |
| 12360 | // op: Rt |
| 12361 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12362 | op &= UINT64_C(31); |
| 12363 | Value |= op; |
| 12364 | // op: Rn |
| 12365 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12366 | op &= UINT64_C(31); |
| 12367 | op <<= 5; |
| 12368 | Value |= op; |
| 12369 | // op: offset |
| 12370 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale8>(MI, 2, Fixups, STI); |
| 12371 | op &= UINT64_C(4095); |
| 12372 | op <<= 10; |
| 12373 | Value |= op; |
| 12374 | break; |
| 12375 | } |
| 12376 | case AArch64::LDAPURBi: |
| 12377 | case AArch64::LDAPURHi: |
| 12378 | case AArch64::LDAPURSBWi: |
| 12379 | case AArch64::LDAPURSBXi: |
| 12380 | case AArch64::LDAPURSHWi: |
| 12381 | case AArch64::LDAPURSHXi: |
| 12382 | case AArch64::LDAPURSWi: |
| 12383 | case AArch64::LDAPURXi: |
| 12384 | case AArch64::LDAPURi: |
| 12385 | case AArch64::LDTRBi: |
| 12386 | case AArch64::LDTRHi: |
| 12387 | case AArch64::LDTRSBWi: |
| 12388 | case AArch64::LDTRSBXi: |
| 12389 | case AArch64::LDTRSHWi: |
| 12390 | case AArch64::LDTRSHXi: |
| 12391 | case AArch64::LDTRSWi: |
| 12392 | case AArch64::LDTRWi: |
| 12393 | case AArch64::LDTRXi: |
| 12394 | case AArch64::LDURBBi: |
| 12395 | case AArch64::LDURBi: |
| 12396 | case AArch64::LDURDi: |
| 12397 | case AArch64::LDURHHi: |
| 12398 | case AArch64::LDURHi: |
| 12399 | case AArch64::LDURQi: |
| 12400 | case AArch64::LDURSBWi: |
| 12401 | case AArch64::LDURSBXi: |
| 12402 | case AArch64::LDURSHWi: |
| 12403 | case AArch64::LDURSHXi: |
| 12404 | case AArch64::LDURSWi: |
| 12405 | case AArch64::LDURSi: |
| 12406 | case AArch64::LDURWi: |
| 12407 | case AArch64::LDURXi: |
| 12408 | case AArch64::PRFUMi: |
| 12409 | case AArch64::STLURBi: |
| 12410 | case AArch64::STLURHi: |
| 12411 | case AArch64::STLURWi: |
| 12412 | case AArch64::STLURXi: |
| 12413 | case AArch64::STTRBi: |
| 12414 | case AArch64::STTRHi: |
| 12415 | case AArch64::STTRWi: |
| 12416 | case AArch64::STTRXi: |
| 12417 | case AArch64::STURBBi: |
| 12418 | case AArch64::STURBi: |
| 12419 | case AArch64::STURDi: |
| 12420 | case AArch64::STURHHi: |
| 12421 | case AArch64::STURHi: |
| 12422 | case AArch64::STURQi: |
| 12423 | case AArch64::STURSi: |
| 12424 | case AArch64::STURWi: |
| 12425 | case AArch64::STURXi: { |
| 12426 | // op: Rt |
| 12427 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12428 | op &= UINT64_C(31); |
| 12429 | Value |= op; |
| 12430 | // op: Rn |
| 12431 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12432 | op &= UINT64_C(31); |
| 12433 | op <<= 5; |
| 12434 | Value |= op; |
| 12435 | // op: offset |
| 12436 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12437 | op &= UINT64_C(511); |
| 12438 | op <<= 12; |
| 12439 | Value |= op; |
| 12440 | break; |
| 12441 | } |
| 12442 | case AArch64::LDARB: |
| 12443 | case AArch64::LDARH: |
| 12444 | case AArch64::LDARW: |
| 12445 | case AArch64::LDARX: |
| 12446 | case AArch64::LDAXRB: |
| 12447 | case AArch64::LDAXRH: |
| 12448 | case AArch64::LDAXRW: |
| 12449 | case AArch64::LDAXRX: |
| 12450 | case AArch64::LDLARB: |
| 12451 | case AArch64::LDLARH: |
| 12452 | case AArch64::LDLARW: |
| 12453 | case AArch64::LDLARX: |
| 12454 | case AArch64::LDXRB: |
| 12455 | case AArch64::LDXRH: |
| 12456 | case AArch64::LDXRW: |
| 12457 | case AArch64::LDXRX: |
| 12458 | case AArch64::STLLRB: |
| 12459 | case AArch64::STLLRH: |
| 12460 | case AArch64::STLLRW: |
| 12461 | case AArch64::STLLRX: |
| 12462 | case AArch64::STLRB: |
| 12463 | case AArch64::STLRH: |
| 12464 | case AArch64::STLRW: |
| 12465 | case AArch64::STLRX: { |
| 12466 | // op: Rt |
| 12467 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12468 | op &= UINT64_C(31); |
| 12469 | Value |= op; |
| 12470 | // op: Rn |
| 12471 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12472 | op &= UINT64_C(31); |
| 12473 | op <<= 5; |
| 12474 | Value |= op; |
| 12475 | Value = fixLoadStoreExclusive<0,0>(MI, Value, STI); |
| 12476 | break; |
| 12477 | } |
| 12478 | case AArch64::LDNPDi: |
| 12479 | case AArch64::LDNPQi: |
| 12480 | case AArch64::LDNPSi: |
| 12481 | case AArch64::LDNPWi: |
| 12482 | case AArch64::LDNPXi: |
| 12483 | case AArch64::LDPDi: |
| 12484 | case AArch64::LDPQi: |
| 12485 | case AArch64::LDPSWi: |
| 12486 | case AArch64::LDPSi: |
| 12487 | case AArch64::LDPWi: |
| 12488 | case AArch64::LDPXi: |
| 12489 | case AArch64::STGPi: |
| 12490 | case AArch64::STNPDi: |
| 12491 | case AArch64::STNPQi: |
| 12492 | case AArch64::STNPSi: |
| 12493 | case AArch64::STNPWi: |
| 12494 | case AArch64::STNPXi: |
| 12495 | case AArch64::STPDi: |
| 12496 | case AArch64::STPQi: |
| 12497 | case AArch64::STPSi: |
| 12498 | case AArch64::STPWi: |
| 12499 | case AArch64::STPXi: { |
| 12500 | // op: Rt |
| 12501 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12502 | op &= UINT64_C(31); |
| 12503 | Value |= op; |
| 12504 | // op: Rt2 |
| 12505 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12506 | op &= UINT64_C(31); |
| 12507 | op <<= 10; |
| 12508 | Value |= op; |
| 12509 | // op: Rn |
| 12510 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12511 | op &= UINT64_C(31); |
| 12512 | op <<= 5; |
| 12513 | Value |= op; |
| 12514 | // op: offset |
| 12515 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12516 | op &= UINT64_C(127); |
| 12517 | op <<= 15; |
| 12518 | Value |= op; |
| 12519 | break; |
| 12520 | } |
| 12521 | case AArch64::LDAXPW: |
| 12522 | case AArch64::LDAXPX: |
| 12523 | case AArch64::LDXPW: |
| 12524 | case AArch64::LDXPX: { |
| 12525 | // op: Rt |
| 12526 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12527 | op &= UINT64_C(31); |
| 12528 | Value |= op; |
| 12529 | // op: Rt2 |
| 12530 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12531 | op &= UINT64_C(31); |
| 12532 | op <<= 10; |
| 12533 | Value |= op; |
| 12534 | // op: Rn |
| 12535 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12536 | op &= UINT64_C(31); |
| 12537 | op <<= 5; |
| 12538 | Value |= op; |
| 12539 | Value = fixLoadStoreExclusive<0,1>(MI, Value, STI); |
| 12540 | break; |
| 12541 | } |
| 12542 | case AArch64::TBNZW: |
| 12543 | case AArch64::TBNZX: |
| 12544 | case AArch64::TBZW: |
| 12545 | case AArch64::TBZX: { |
| 12546 | // op: Rt |
| 12547 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12548 | op &= UINT64_C(31); |
| 12549 | Value |= op; |
| 12550 | // op: bit_off |
| 12551 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12552 | op &= UINT64_C(31); |
| 12553 | op <<= 19; |
| 12554 | Value |= op; |
| 12555 | // op: target |
| 12556 | op = getTestBranchTargetOpValue(MI, 2, Fixups, STI); |
| 12557 | op &= UINT64_C(16383); |
| 12558 | op <<= 5; |
| 12559 | Value |= op; |
| 12560 | break; |
| 12561 | } |
| 12562 | case AArch64::LDRDl: |
| 12563 | case AArch64::LDRQl: |
| 12564 | case AArch64::LDRSWl: |
| 12565 | case AArch64::LDRSl: |
| 12566 | case AArch64::LDRWl: |
| 12567 | case AArch64::LDRXl: |
| 12568 | case AArch64::PRFMl: { |
| 12569 | // op: Rt |
| 12570 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12571 | op &= UINT64_C(31); |
| 12572 | Value |= op; |
| 12573 | // op: label |
| 12574 | op = getLoadLiteralOpValue(MI, 1, Fixups, STI); |
| 12575 | op &= UINT64_C(524287); |
| 12576 | op <<= 5; |
| 12577 | Value |= op; |
| 12578 | break; |
| 12579 | } |
| 12580 | case AArch64::SYSLxt: { |
| 12581 | // op: Rt |
| 12582 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12583 | op &= UINT64_C(31); |
| 12584 | Value |= op; |
| 12585 | // op: op1 |
| 12586 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12587 | op &= UINT64_C(7); |
| 12588 | op <<= 16; |
| 12589 | Value |= op; |
| 12590 | // op: Cn |
| 12591 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12592 | op &= UINT64_C(15); |
| 12593 | op <<= 12; |
| 12594 | Value |= op; |
| 12595 | // op: Cm |
| 12596 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12597 | op &= UINT64_C(15); |
| 12598 | op <<= 8; |
| 12599 | Value |= op; |
| 12600 | // op: op2 |
| 12601 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 12602 | op &= UINT64_C(7); |
| 12603 | op <<= 5; |
| 12604 | Value |= op; |
| 12605 | break; |
| 12606 | } |
| 12607 | case AArch64::MRS: { |
| 12608 | // op: Rt |
| 12609 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12610 | op &= UINT64_C(31); |
| 12611 | Value |= op; |
| 12612 | // op: systemreg |
| 12613 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12614 | op &= UINT64_C(65535); |
| 12615 | op <<= 5; |
| 12616 | Value |= op; |
| 12617 | break; |
| 12618 | } |
| 12619 | case AArch64::CBNZW: |
| 12620 | case AArch64::CBNZX: |
| 12621 | case AArch64::CBZW: |
| 12622 | case AArch64::CBZX: { |
| 12623 | // op: Rt |
| 12624 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12625 | op &= UINT64_C(31); |
| 12626 | Value |= op; |
| 12627 | // op: target |
| 12628 | op = getCondBranchTargetOpValue(MI, 1, Fixups, STI); |
| 12629 | op &= UINT64_C(524287); |
| 12630 | op <<= 5; |
| 12631 | Value |= op; |
| 12632 | break; |
| 12633 | } |
| 12634 | case AArch64::ST64BV: |
| 12635 | case AArch64::ST64BV0: { |
| 12636 | // op: Rt |
| 12637 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12638 | op &= UINT64_C(31); |
| 12639 | Value |= op; |
| 12640 | // op: Rn |
| 12641 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12642 | op &= UINT64_C(31); |
| 12643 | op <<= 5; |
| 12644 | Value |= op; |
| 12645 | // op: Rs |
| 12646 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12647 | op &= UINT64_C(31); |
| 12648 | op <<= 16; |
| 12649 | Value |= op; |
| 12650 | break; |
| 12651 | } |
| 12652 | case AArch64::LDRBBpost: |
| 12653 | case AArch64::LDRBBpre: |
| 12654 | case AArch64::LDRBpost: |
| 12655 | case AArch64::LDRBpre: |
| 12656 | case AArch64::LDRDpost: |
| 12657 | case AArch64::LDRDpre: |
| 12658 | case AArch64::LDRHHpost: |
| 12659 | case AArch64::LDRHHpre: |
| 12660 | case AArch64::LDRHpost: |
| 12661 | case AArch64::LDRHpre: |
| 12662 | case AArch64::LDRQpost: |
| 12663 | case AArch64::LDRQpre: |
| 12664 | case AArch64::LDRSBWpost: |
| 12665 | case AArch64::LDRSBWpre: |
| 12666 | case AArch64::LDRSBXpost: |
| 12667 | case AArch64::LDRSBXpre: |
| 12668 | case AArch64::LDRSHWpost: |
| 12669 | case AArch64::LDRSHWpre: |
| 12670 | case AArch64::LDRSHXpost: |
| 12671 | case AArch64::LDRSHXpre: |
| 12672 | case AArch64::LDRSWpost: |
| 12673 | case AArch64::LDRSWpre: |
| 12674 | case AArch64::LDRSpost: |
| 12675 | case AArch64::LDRSpre: |
| 12676 | case AArch64::LDRWpost: |
| 12677 | case AArch64::LDRWpre: |
| 12678 | case AArch64::LDRXpost: |
| 12679 | case AArch64::LDRXpre: |
| 12680 | case AArch64::STRBBpost: |
| 12681 | case AArch64::STRBBpre: |
| 12682 | case AArch64::STRBpost: |
| 12683 | case AArch64::STRBpre: |
| 12684 | case AArch64::STRDpost: |
| 12685 | case AArch64::STRDpre: |
| 12686 | case AArch64::STRHHpost: |
| 12687 | case AArch64::STRHHpre: |
| 12688 | case AArch64::STRHpost: |
| 12689 | case AArch64::STRHpre: |
| 12690 | case AArch64::STRQpost: |
| 12691 | case AArch64::STRQpre: |
| 12692 | case AArch64::STRSpost: |
| 12693 | case AArch64::STRSpre: |
| 12694 | case AArch64::STRWpost: |
| 12695 | case AArch64::STRWpre: |
| 12696 | case AArch64::STRXpost: |
| 12697 | case AArch64::STRXpre: { |
| 12698 | // op: Rt |
| 12699 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12700 | op &= UINT64_C(31); |
| 12701 | Value |= op; |
| 12702 | // op: Rn |
| 12703 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12704 | op &= UINT64_C(31); |
| 12705 | op <<= 5; |
| 12706 | Value |= op; |
| 12707 | // op: offset |
| 12708 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12709 | op &= UINT64_C(511); |
| 12710 | op <<= 12; |
| 12711 | Value |= op; |
| 12712 | break; |
| 12713 | } |
| 12714 | case AArch64::LDPDpost: |
| 12715 | case AArch64::LDPDpre: |
| 12716 | case AArch64::LDPQpost: |
| 12717 | case AArch64::LDPQpre: |
| 12718 | case AArch64::LDPSWpost: |
| 12719 | case AArch64::LDPSWpre: |
| 12720 | case AArch64::LDPSpost: |
| 12721 | case AArch64::LDPSpre: |
| 12722 | case AArch64::LDPWpost: |
| 12723 | case AArch64::LDPWpre: |
| 12724 | case AArch64::LDPXpost: |
| 12725 | case AArch64::LDPXpre: |
| 12726 | case AArch64::STGPpost: |
| 12727 | case AArch64::STGPpre: |
| 12728 | case AArch64::STPDpost: |
| 12729 | case AArch64::STPDpre: |
| 12730 | case AArch64::STPQpost: |
| 12731 | case AArch64::STPQpre: |
| 12732 | case AArch64::STPSpost: |
| 12733 | case AArch64::STPSpre: |
| 12734 | case AArch64::STPWpost: |
| 12735 | case AArch64::STPWpre: |
| 12736 | case AArch64::STPXpost: |
| 12737 | case AArch64::STPXpre: { |
| 12738 | // op: Rt |
| 12739 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12740 | op &= UINT64_C(31); |
| 12741 | Value |= op; |
| 12742 | // op: Rt2 |
| 12743 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12744 | op &= UINT64_C(31); |
| 12745 | op <<= 10; |
| 12746 | Value |= op; |
| 12747 | // op: Rn |
| 12748 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12749 | op &= UINT64_C(31); |
| 12750 | op <<= 5; |
| 12751 | Value |= op; |
| 12752 | // op: offset |
| 12753 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 12754 | op &= UINT64_C(127); |
| 12755 | op <<= 15; |
| 12756 | Value |= op; |
| 12757 | break; |
| 12758 | } |
| 12759 | case AArch64::MSR: { |
| 12760 | // op: Rt |
| 12761 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12762 | op &= UINT64_C(31); |
| 12763 | Value |= op; |
| 12764 | // op: systemreg |
| 12765 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12766 | op &= UINT64_C(65535); |
| 12767 | op <<= 5; |
| 12768 | Value |= op; |
| 12769 | break; |
| 12770 | } |
| 12771 | case AArch64::SYSxt: { |
| 12772 | // op: Rt |
| 12773 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 12774 | op &= UINT64_C(31); |
| 12775 | Value |= op; |
| 12776 | // op: op1 |
| 12777 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12778 | op &= UINT64_C(7); |
| 12779 | op <<= 16; |
| 12780 | Value |= op; |
| 12781 | // op: Cn |
| 12782 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12783 | op &= UINT64_C(15); |
| 12784 | op <<= 12; |
| 12785 | Value |= op; |
| 12786 | // op: Cm |
| 12787 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12788 | op &= UINT64_C(15); |
| 12789 | op <<= 8; |
| 12790 | Value |= op; |
| 12791 | // op: op2 |
| 12792 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12793 | op &= UINT64_C(7); |
| 12794 | op <<= 5; |
| 12795 | Value |= op; |
| 12796 | break; |
| 12797 | } |
| 12798 | case AArch64::SHA512SU0: |
| 12799 | case AArch64::SM4E: { |
| 12800 | // op: Vd |
| 12801 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12802 | op &= UINT64_C(31); |
| 12803 | Value |= op; |
| 12804 | // op: Vn |
| 12805 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12806 | op &= UINT64_C(31); |
| 12807 | op <<= 5; |
| 12808 | Value |= op; |
| 12809 | break; |
| 12810 | } |
| 12811 | case AArch64::RAX1: |
| 12812 | case AArch64::SM4ENCKEY: |
| 12813 | case AArch64::TBLv16i8Four: |
| 12814 | case AArch64::TBLv16i8One: |
| 12815 | case AArch64::TBLv16i8Three: |
| 12816 | case AArch64::TBLv16i8Two: |
| 12817 | case AArch64::TBLv8i8Four: |
| 12818 | case AArch64::TBLv8i8One: |
| 12819 | case AArch64::TBLv8i8Three: |
| 12820 | case AArch64::TBLv8i8Two: { |
| 12821 | // op: Vd |
| 12822 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12823 | op &= UINT64_C(31); |
| 12824 | Value |= op; |
| 12825 | // op: Vn |
| 12826 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12827 | op &= UINT64_C(31); |
| 12828 | op <<= 5; |
| 12829 | Value |= op; |
| 12830 | // op: Vm |
| 12831 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12832 | op &= UINT64_C(31); |
| 12833 | op <<= 16; |
| 12834 | Value |= op; |
| 12835 | break; |
| 12836 | } |
| 12837 | case AArch64::BCAX: |
| 12838 | case AArch64::EOR3: |
| 12839 | case AArch64::SM3SS1: { |
| 12840 | // op: Vd |
| 12841 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12842 | op &= UINT64_C(31); |
| 12843 | Value |= op; |
| 12844 | // op: Vn |
| 12845 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12846 | op &= UINT64_C(31); |
| 12847 | op <<= 5; |
| 12848 | Value |= op; |
| 12849 | // op: Vm |
| 12850 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12851 | op &= UINT64_C(31); |
| 12852 | op <<= 16; |
| 12853 | Value |= op; |
| 12854 | // op: Va |
| 12855 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12856 | op &= UINT64_C(31); |
| 12857 | op <<= 10; |
| 12858 | Value |= op; |
| 12859 | break; |
| 12860 | } |
| 12861 | case AArch64::XAR: { |
| 12862 | // op: Vd |
| 12863 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12864 | op &= UINT64_C(31); |
| 12865 | Value |= op; |
| 12866 | // op: Vn |
| 12867 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12868 | op &= UINT64_C(31); |
| 12869 | op <<= 5; |
| 12870 | Value |= op; |
| 12871 | // op: imm |
| 12872 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12873 | op &= UINT64_C(63); |
| 12874 | op <<= 10; |
| 12875 | Value |= op; |
| 12876 | // op: Vm |
| 12877 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12878 | op &= UINT64_C(31); |
| 12879 | op <<= 16; |
| 12880 | Value |= op; |
| 12881 | break; |
| 12882 | } |
| 12883 | case AArch64::SHA512H: |
| 12884 | case AArch64::SHA512H2: |
| 12885 | case AArch64::SHA512SU1: |
| 12886 | case AArch64::SM3PARTW1: |
| 12887 | case AArch64::SM3PARTW2: |
| 12888 | case AArch64::TBXv16i8Four: |
| 12889 | case AArch64::TBXv16i8One: |
| 12890 | case AArch64::TBXv16i8Three: |
| 12891 | case AArch64::TBXv16i8Two: |
| 12892 | case AArch64::TBXv8i8Four: |
| 12893 | case AArch64::TBXv8i8One: |
| 12894 | case AArch64::TBXv8i8Three: |
| 12895 | case AArch64::TBXv8i8Two: { |
| 12896 | // op: Vd |
| 12897 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12898 | op &= UINT64_C(31); |
| 12899 | Value |= op; |
| 12900 | // op: Vn |
| 12901 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12902 | op &= UINT64_C(31); |
| 12903 | op <<= 5; |
| 12904 | Value |= op; |
| 12905 | // op: Vm |
| 12906 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12907 | op &= UINT64_C(31); |
| 12908 | op <<= 16; |
| 12909 | Value |= op; |
| 12910 | break; |
| 12911 | } |
| 12912 | case AArch64::SM3TT1A: |
| 12913 | case AArch64::SM3TT1B: |
| 12914 | case AArch64::SM3TT2A: |
| 12915 | case AArch64::SM3TT2B: { |
| 12916 | // op: Vd |
| 12917 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 12918 | op &= UINT64_C(31); |
| 12919 | Value |= op; |
| 12920 | // op: Vn |
| 12921 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12922 | op &= UINT64_C(31); |
| 12923 | op <<= 5; |
| 12924 | Value |= op; |
| 12925 | // op: imm |
| 12926 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 12927 | op &= UINT64_C(3); |
| 12928 | op <<= 12; |
| 12929 | Value |= op; |
| 12930 | // op: Vm |
| 12931 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 12932 | op &= UINT64_C(31); |
| 12933 | op <<= 16; |
| 12934 | Value |= op; |
| 12935 | break; |
| 12936 | } |
| 12937 | case AArch64::INSR_ZV_B: |
| 12938 | case AArch64::INSR_ZV_D: |
| 12939 | case AArch64::INSR_ZV_H: |
| 12940 | case AArch64::INSR_ZV_S: { |
| 12941 | // op: Vm |
| 12942 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 12943 | op &= UINT64_C(31); |
| 12944 | op <<= 5; |
| 12945 | Value |= op; |
| 12946 | // op: Zdn |
| 12947 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 12948 | op &= UINT64_C(31); |
| 12949 | Value |= op; |
| 12950 | break; |
| 12951 | } |
| 12952 | case AArch64::LD1Fourv16b: |
| 12953 | case AArch64::LD1Fourv1d: |
| 12954 | case AArch64::LD1Fourv2d: |
| 12955 | case AArch64::LD1Fourv2s: |
| 12956 | case AArch64::LD1Fourv4h: |
| 12957 | case AArch64::LD1Fourv4s: |
| 12958 | case AArch64::LD1Fourv8b: |
| 12959 | case AArch64::LD1Fourv8h: |
| 12960 | case AArch64::LD1Onev16b: |
| 12961 | case AArch64::LD1Onev1d: |
| 12962 | case AArch64::LD1Onev2d: |
| 12963 | case AArch64::LD1Onev2s: |
| 12964 | case AArch64::LD1Onev4h: |
| 12965 | case AArch64::LD1Onev4s: |
| 12966 | case AArch64::LD1Onev8b: |
| 12967 | case AArch64::LD1Onev8h: |
| 12968 | case AArch64::LD1Rv16b: |
| 12969 | case AArch64::LD1Rv1d: |
| 12970 | case AArch64::LD1Rv2d: |
| 12971 | case AArch64::LD1Rv2s: |
| 12972 | case AArch64::LD1Rv4h: |
| 12973 | case AArch64::LD1Rv4s: |
| 12974 | case AArch64::LD1Rv8b: |
| 12975 | case AArch64::LD1Rv8h: |
| 12976 | case AArch64::LD1Threev16b: |
| 12977 | case AArch64::LD1Threev1d: |
| 12978 | case AArch64::LD1Threev2d: |
| 12979 | case AArch64::LD1Threev2s: |
| 12980 | case AArch64::LD1Threev4h: |
| 12981 | case AArch64::LD1Threev4s: |
| 12982 | case AArch64::LD1Threev8b: |
| 12983 | case AArch64::LD1Threev8h: |
| 12984 | case AArch64::LD1Twov16b: |
| 12985 | case AArch64::LD1Twov1d: |
| 12986 | case AArch64::LD1Twov2d: |
| 12987 | case AArch64::LD1Twov2s: |
| 12988 | case AArch64::LD1Twov4h: |
| 12989 | case AArch64::LD1Twov4s: |
| 12990 | case AArch64::LD1Twov8b: |
| 12991 | case AArch64::LD1Twov8h: |
| 12992 | case AArch64::LD2Rv16b: |
| 12993 | case AArch64::LD2Rv1d: |
| 12994 | case AArch64::LD2Rv2d: |
| 12995 | case AArch64::LD2Rv2s: |
| 12996 | case AArch64::LD2Rv4h: |
| 12997 | case AArch64::LD2Rv4s: |
| 12998 | case AArch64::LD2Rv8b: |
| 12999 | case AArch64::LD2Rv8h: |
| 13000 | case AArch64::LD2Twov16b: |
| 13001 | case AArch64::LD2Twov2d: |
| 13002 | case AArch64::LD2Twov2s: |
| 13003 | case AArch64::LD2Twov4h: |
| 13004 | case AArch64::LD2Twov4s: |
| 13005 | case AArch64::LD2Twov8b: |
| 13006 | case AArch64::LD2Twov8h: |
| 13007 | case AArch64::LD3Rv16b: |
| 13008 | case AArch64::LD3Rv1d: |
| 13009 | case AArch64::LD3Rv2d: |
| 13010 | case AArch64::LD3Rv2s: |
| 13011 | case AArch64::LD3Rv4h: |
| 13012 | case AArch64::LD3Rv4s: |
| 13013 | case AArch64::LD3Rv8b: |
| 13014 | case AArch64::LD3Rv8h: |
| 13015 | case AArch64::LD3Threev16b: |
| 13016 | case AArch64::LD3Threev2d: |
| 13017 | case AArch64::LD3Threev2s: |
| 13018 | case AArch64::LD3Threev4h: |
| 13019 | case AArch64::LD3Threev4s: |
| 13020 | case AArch64::LD3Threev8b: |
| 13021 | case AArch64::LD3Threev8h: |
| 13022 | case AArch64::LD4Fourv16b: |
| 13023 | case AArch64::LD4Fourv2d: |
| 13024 | case AArch64::LD4Fourv2s: |
| 13025 | case AArch64::LD4Fourv4h: |
| 13026 | case AArch64::LD4Fourv4s: |
| 13027 | case AArch64::LD4Fourv8b: |
| 13028 | case AArch64::LD4Fourv8h: |
| 13029 | case AArch64::LD4Rv16b: |
| 13030 | case AArch64::LD4Rv1d: |
| 13031 | case AArch64::LD4Rv2d: |
| 13032 | case AArch64::LD4Rv2s: |
| 13033 | case AArch64::LD4Rv4h: |
| 13034 | case AArch64::LD4Rv4s: |
| 13035 | case AArch64::LD4Rv8b: |
| 13036 | case AArch64::LD4Rv8h: |
| 13037 | case AArch64::ST1Fourv16b: |
| 13038 | case AArch64::ST1Fourv1d: |
| 13039 | case AArch64::ST1Fourv2d: |
| 13040 | case AArch64::ST1Fourv2s: |
| 13041 | case AArch64::ST1Fourv4h: |
| 13042 | case AArch64::ST1Fourv4s: |
| 13043 | case AArch64::ST1Fourv8b: |
| 13044 | case AArch64::ST1Fourv8h: |
| 13045 | case AArch64::ST1Onev16b: |
| 13046 | case AArch64::ST1Onev1d: |
| 13047 | case AArch64::ST1Onev2d: |
| 13048 | case AArch64::ST1Onev2s: |
| 13049 | case AArch64::ST1Onev4h: |
| 13050 | case AArch64::ST1Onev4s: |
| 13051 | case AArch64::ST1Onev8b: |
| 13052 | case AArch64::ST1Onev8h: |
| 13053 | case AArch64::ST1Threev16b: |
| 13054 | case AArch64::ST1Threev1d: |
| 13055 | case AArch64::ST1Threev2d: |
| 13056 | case AArch64::ST1Threev2s: |
| 13057 | case AArch64::ST1Threev4h: |
| 13058 | case AArch64::ST1Threev4s: |
| 13059 | case AArch64::ST1Threev8b: |
| 13060 | case AArch64::ST1Threev8h: |
| 13061 | case AArch64::ST1Twov16b: |
| 13062 | case AArch64::ST1Twov1d: |
| 13063 | case AArch64::ST1Twov2d: |
| 13064 | case AArch64::ST1Twov2s: |
| 13065 | case AArch64::ST1Twov4h: |
| 13066 | case AArch64::ST1Twov4s: |
| 13067 | case AArch64::ST1Twov8b: |
| 13068 | case AArch64::ST1Twov8h: |
| 13069 | case AArch64::ST2Twov16b: |
| 13070 | case AArch64::ST2Twov2d: |
| 13071 | case AArch64::ST2Twov2s: |
| 13072 | case AArch64::ST2Twov4h: |
| 13073 | case AArch64::ST2Twov4s: |
| 13074 | case AArch64::ST2Twov8b: |
| 13075 | case AArch64::ST2Twov8h: |
| 13076 | case AArch64::ST3Threev16b: |
| 13077 | case AArch64::ST3Threev2d: |
| 13078 | case AArch64::ST3Threev2s: |
| 13079 | case AArch64::ST3Threev4h: |
| 13080 | case AArch64::ST3Threev4s: |
| 13081 | case AArch64::ST3Threev8b: |
| 13082 | case AArch64::ST3Threev8h: |
| 13083 | case AArch64::ST4Fourv16b: |
| 13084 | case AArch64::ST4Fourv2d: |
| 13085 | case AArch64::ST4Fourv2s: |
| 13086 | case AArch64::ST4Fourv4h: |
| 13087 | case AArch64::ST4Fourv4s: |
| 13088 | case AArch64::ST4Fourv8b: |
| 13089 | case AArch64::ST4Fourv8h: { |
| 13090 | // op: Vt |
| 13091 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13092 | op &= UINT64_C(31); |
| 13093 | Value |= op; |
| 13094 | // op: Rn |
| 13095 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13096 | op &= UINT64_C(31); |
| 13097 | op <<= 5; |
| 13098 | Value |= op; |
| 13099 | break; |
| 13100 | } |
| 13101 | case AArch64::ST1i32: |
| 13102 | case AArch64::ST2i32: |
| 13103 | case AArch64::ST3i32: |
| 13104 | case AArch64::ST4i32: { |
| 13105 | // op: Vt |
| 13106 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13107 | op &= UINT64_C(31); |
| 13108 | Value |= op; |
| 13109 | // op: Rn |
| 13110 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13111 | op &= UINT64_C(31); |
| 13112 | op <<= 5; |
| 13113 | Value |= op; |
| 13114 | // op: idx |
| 13115 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13116 | Value |= (op & UINT64_C(2)) << 29; |
| 13117 | Value |= (op & UINT64_C(1)) << 12; |
| 13118 | break; |
| 13119 | } |
| 13120 | case AArch64::ST1i16: |
| 13121 | case AArch64::ST2i16: |
| 13122 | case AArch64::ST3i16: |
| 13123 | case AArch64::ST4i16: { |
| 13124 | // op: Vt |
| 13125 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13126 | op &= UINT64_C(31); |
| 13127 | Value |= op; |
| 13128 | // op: Rn |
| 13129 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13130 | op &= UINT64_C(31); |
| 13131 | op <<= 5; |
| 13132 | Value |= op; |
| 13133 | // op: idx |
| 13134 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13135 | Value |= (op & UINT64_C(4)) << 28; |
| 13136 | Value |= (op & UINT64_C(3)) << 11; |
| 13137 | break; |
| 13138 | } |
| 13139 | case AArch64::ST1i8: |
| 13140 | case AArch64::ST2i8: |
| 13141 | case AArch64::ST3i8: |
| 13142 | case AArch64::ST4i8: { |
| 13143 | // op: Vt |
| 13144 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13145 | op &= UINT64_C(31); |
| 13146 | Value |= op; |
| 13147 | // op: Rn |
| 13148 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13149 | op &= UINT64_C(31); |
| 13150 | op <<= 5; |
| 13151 | Value |= op; |
| 13152 | // op: idx |
| 13153 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13154 | Value |= (op & UINT64_C(8)) << 27; |
| 13155 | Value |= (op & UINT64_C(7)) << 10; |
| 13156 | break; |
| 13157 | } |
| 13158 | case AArch64::ST1i64: |
| 13159 | case AArch64::ST2i64: |
| 13160 | case AArch64::ST3i64: |
| 13161 | case AArch64::ST4i64: { |
| 13162 | // op: Vt |
| 13163 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13164 | op &= UINT64_C(31); |
| 13165 | Value |= op; |
| 13166 | // op: Rn |
| 13167 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13168 | op &= UINT64_C(31); |
| 13169 | op <<= 5; |
| 13170 | Value |= op; |
| 13171 | // op: idx |
| 13172 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13173 | op &= UINT64_C(1); |
| 13174 | op <<= 30; |
| 13175 | Value |= op; |
| 13176 | break; |
| 13177 | } |
| 13178 | case AArch64::LD1Fourv16b_POST: |
| 13179 | case AArch64::LD1Fourv1d_POST: |
| 13180 | case AArch64::LD1Fourv2d_POST: |
| 13181 | case AArch64::LD1Fourv2s_POST: |
| 13182 | case AArch64::LD1Fourv4h_POST: |
| 13183 | case AArch64::LD1Fourv4s_POST: |
| 13184 | case AArch64::LD1Fourv8b_POST: |
| 13185 | case AArch64::LD1Fourv8h_POST: |
| 13186 | case AArch64::LD1Onev16b_POST: |
| 13187 | case AArch64::LD1Onev1d_POST: |
| 13188 | case AArch64::LD1Onev2d_POST: |
| 13189 | case AArch64::LD1Onev2s_POST: |
| 13190 | case AArch64::LD1Onev4h_POST: |
| 13191 | case AArch64::LD1Onev4s_POST: |
| 13192 | case AArch64::LD1Onev8b_POST: |
| 13193 | case AArch64::LD1Onev8h_POST: |
| 13194 | case AArch64::LD1Rv16b_POST: |
| 13195 | case AArch64::LD1Rv1d_POST: |
| 13196 | case AArch64::LD1Rv2d_POST: |
| 13197 | case AArch64::LD1Rv2s_POST: |
| 13198 | case AArch64::LD1Rv4h_POST: |
| 13199 | case AArch64::LD1Rv4s_POST: |
| 13200 | case AArch64::LD1Rv8b_POST: |
| 13201 | case AArch64::LD1Rv8h_POST: |
| 13202 | case AArch64::LD1Threev16b_POST: |
| 13203 | case AArch64::LD1Threev1d_POST: |
| 13204 | case AArch64::LD1Threev2d_POST: |
| 13205 | case AArch64::LD1Threev2s_POST: |
| 13206 | case AArch64::LD1Threev4h_POST: |
| 13207 | case AArch64::LD1Threev4s_POST: |
| 13208 | case AArch64::LD1Threev8b_POST: |
| 13209 | case AArch64::LD1Threev8h_POST: |
| 13210 | case AArch64::LD1Twov16b_POST: |
| 13211 | case AArch64::LD1Twov1d_POST: |
| 13212 | case AArch64::LD1Twov2d_POST: |
| 13213 | case AArch64::LD1Twov2s_POST: |
| 13214 | case AArch64::LD1Twov4h_POST: |
| 13215 | case AArch64::LD1Twov4s_POST: |
| 13216 | case AArch64::LD1Twov8b_POST: |
| 13217 | case AArch64::LD1Twov8h_POST: |
| 13218 | case AArch64::LD2Rv16b_POST: |
| 13219 | case AArch64::LD2Rv1d_POST: |
| 13220 | case AArch64::LD2Rv2d_POST: |
| 13221 | case AArch64::LD2Rv2s_POST: |
| 13222 | case AArch64::LD2Rv4h_POST: |
| 13223 | case AArch64::LD2Rv4s_POST: |
| 13224 | case AArch64::LD2Rv8b_POST: |
| 13225 | case AArch64::LD2Rv8h_POST: |
| 13226 | case AArch64::LD2Twov16b_POST: |
| 13227 | case AArch64::LD2Twov2d_POST: |
| 13228 | case AArch64::LD2Twov2s_POST: |
| 13229 | case AArch64::LD2Twov4h_POST: |
| 13230 | case AArch64::LD2Twov4s_POST: |
| 13231 | case AArch64::LD2Twov8b_POST: |
| 13232 | case AArch64::LD2Twov8h_POST: |
| 13233 | case AArch64::LD3Rv16b_POST: |
| 13234 | case AArch64::LD3Rv1d_POST: |
| 13235 | case AArch64::LD3Rv2d_POST: |
| 13236 | case AArch64::LD3Rv2s_POST: |
| 13237 | case AArch64::LD3Rv4h_POST: |
| 13238 | case AArch64::LD3Rv4s_POST: |
| 13239 | case AArch64::LD3Rv8b_POST: |
| 13240 | case AArch64::LD3Rv8h_POST: |
| 13241 | case AArch64::LD3Threev16b_POST: |
| 13242 | case AArch64::LD3Threev2d_POST: |
| 13243 | case AArch64::LD3Threev2s_POST: |
| 13244 | case AArch64::LD3Threev4h_POST: |
| 13245 | case AArch64::LD3Threev4s_POST: |
| 13246 | case AArch64::LD3Threev8b_POST: |
| 13247 | case AArch64::LD3Threev8h_POST: |
| 13248 | case AArch64::LD4Fourv16b_POST: |
| 13249 | case AArch64::LD4Fourv2d_POST: |
| 13250 | case AArch64::LD4Fourv2s_POST: |
| 13251 | case AArch64::LD4Fourv4h_POST: |
| 13252 | case AArch64::LD4Fourv4s_POST: |
| 13253 | case AArch64::LD4Fourv8b_POST: |
| 13254 | case AArch64::LD4Fourv8h_POST: |
| 13255 | case AArch64::LD4Rv16b_POST: |
| 13256 | case AArch64::LD4Rv1d_POST: |
| 13257 | case AArch64::LD4Rv2d_POST: |
| 13258 | case AArch64::LD4Rv2s_POST: |
| 13259 | case AArch64::LD4Rv4h_POST: |
| 13260 | case AArch64::LD4Rv4s_POST: |
| 13261 | case AArch64::LD4Rv8b_POST: |
| 13262 | case AArch64::LD4Rv8h_POST: |
| 13263 | case AArch64::ST1Fourv16b_POST: |
| 13264 | case AArch64::ST1Fourv1d_POST: |
| 13265 | case AArch64::ST1Fourv2d_POST: |
| 13266 | case AArch64::ST1Fourv2s_POST: |
| 13267 | case AArch64::ST1Fourv4h_POST: |
| 13268 | case AArch64::ST1Fourv4s_POST: |
| 13269 | case AArch64::ST1Fourv8b_POST: |
| 13270 | case AArch64::ST1Fourv8h_POST: |
| 13271 | case AArch64::ST1Onev16b_POST: |
| 13272 | case AArch64::ST1Onev1d_POST: |
| 13273 | case AArch64::ST1Onev2d_POST: |
| 13274 | case AArch64::ST1Onev2s_POST: |
| 13275 | case AArch64::ST1Onev4h_POST: |
| 13276 | case AArch64::ST1Onev4s_POST: |
| 13277 | case AArch64::ST1Onev8b_POST: |
| 13278 | case AArch64::ST1Onev8h_POST: |
| 13279 | case AArch64::ST1Threev16b_POST: |
| 13280 | case AArch64::ST1Threev1d_POST: |
| 13281 | case AArch64::ST1Threev2d_POST: |
| 13282 | case AArch64::ST1Threev2s_POST: |
| 13283 | case AArch64::ST1Threev4h_POST: |
| 13284 | case AArch64::ST1Threev4s_POST: |
| 13285 | case AArch64::ST1Threev8b_POST: |
| 13286 | case AArch64::ST1Threev8h_POST: |
| 13287 | case AArch64::ST1Twov16b_POST: |
| 13288 | case AArch64::ST1Twov1d_POST: |
| 13289 | case AArch64::ST1Twov2d_POST: |
| 13290 | case AArch64::ST1Twov2s_POST: |
| 13291 | case AArch64::ST1Twov4h_POST: |
| 13292 | case AArch64::ST1Twov4s_POST: |
| 13293 | case AArch64::ST1Twov8b_POST: |
| 13294 | case AArch64::ST1Twov8h_POST: |
| 13295 | case AArch64::ST2Twov16b_POST: |
| 13296 | case AArch64::ST2Twov2d_POST: |
| 13297 | case AArch64::ST2Twov2s_POST: |
| 13298 | case AArch64::ST2Twov4h_POST: |
| 13299 | case AArch64::ST2Twov4s_POST: |
| 13300 | case AArch64::ST2Twov8b_POST: |
| 13301 | case AArch64::ST2Twov8h_POST: |
| 13302 | case AArch64::ST3Threev16b_POST: |
| 13303 | case AArch64::ST3Threev2d_POST: |
| 13304 | case AArch64::ST3Threev2s_POST: |
| 13305 | case AArch64::ST3Threev4h_POST: |
| 13306 | case AArch64::ST3Threev4s_POST: |
| 13307 | case AArch64::ST3Threev8b_POST: |
| 13308 | case AArch64::ST3Threev8h_POST: |
| 13309 | case AArch64::ST4Fourv16b_POST: |
| 13310 | case AArch64::ST4Fourv2d_POST: |
| 13311 | case AArch64::ST4Fourv2s_POST: |
| 13312 | case AArch64::ST4Fourv4h_POST: |
| 13313 | case AArch64::ST4Fourv4s_POST: |
| 13314 | case AArch64::ST4Fourv8b_POST: |
| 13315 | case AArch64::ST4Fourv8h_POST: { |
| 13316 | // op: Vt |
| 13317 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13318 | op &= UINT64_C(31); |
| 13319 | Value |= op; |
| 13320 | // op: Rn |
| 13321 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13322 | op &= UINT64_C(31); |
| 13323 | op <<= 5; |
| 13324 | Value |= op; |
| 13325 | // op: Xm |
| 13326 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13327 | op &= UINT64_C(31); |
| 13328 | op <<= 16; |
| 13329 | Value |= op; |
| 13330 | break; |
| 13331 | } |
| 13332 | case AArch64::LD1i32: |
| 13333 | case AArch64::LD2i32: |
| 13334 | case AArch64::LD3i32: |
| 13335 | case AArch64::LD4i32: { |
| 13336 | // op: Vt |
| 13337 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13338 | op &= UINT64_C(31); |
| 13339 | Value |= op; |
| 13340 | // op: Rn |
| 13341 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13342 | op &= UINT64_C(31); |
| 13343 | op <<= 5; |
| 13344 | Value |= op; |
| 13345 | // op: idx |
| 13346 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13347 | Value |= (op & UINT64_C(2)) << 29; |
| 13348 | Value |= (op & UINT64_C(1)) << 12; |
| 13349 | break; |
| 13350 | } |
| 13351 | case AArch64::ST1i32_POST: |
| 13352 | case AArch64::ST2i32_POST: |
| 13353 | case AArch64::ST3i32_POST: |
| 13354 | case AArch64::ST4i32_POST: { |
| 13355 | // op: Vt |
| 13356 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13357 | op &= UINT64_C(31); |
| 13358 | Value |= op; |
| 13359 | // op: Rn |
| 13360 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13361 | op &= UINT64_C(31); |
| 13362 | op <<= 5; |
| 13363 | Value |= op; |
| 13364 | // op: idx |
| 13365 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13366 | Value |= (op & UINT64_C(2)) << 29; |
| 13367 | Value |= (op & UINT64_C(1)) << 12; |
| 13368 | // op: Xm |
| 13369 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 13370 | op &= UINT64_C(31); |
| 13371 | op <<= 16; |
| 13372 | Value |= op; |
| 13373 | break; |
| 13374 | } |
| 13375 | case AArch64::LD1i16: |
| 13376 | case AArch64::LD2i16: |
| 13377 | case AArch64::LD3i16: |
| 13378 | case AArch64::LD4i16: { |
| 13379 | // op: Vt |
| 13380 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13381 | op &= UINT64_C(31); |
| 13382 | Value |= op; |
| 13383 | // op: Rn |
| 13384 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13385 | op &= UINT64_C(31); |
| 13386 | op <<= 5; |
| 13387 | Value |= op; |
| 13388 | // op: idx |
| 13389 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13390 | Value |= (op & UINT64_C(4)) << 28; |
| 13391 | Value |= (op & UINT64_C(3)) << 11; |
| 13392 | break; |
| 13393 | } |
| 13394 | case AArch64::ST1i16_POST: |
| 13395 | case AArch64::ST2i16_POST: |
| 13396 | case AArch64::ST3i16_POST: |
| 13397 | case AArch64::ST4i16_POST: { |
| 13398 | // op: Vt |
| 13399 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13400 | op &= UINT64_C(31); |
| 13401 | Value |= op; |
| 13402 | // op: Rn |
| 13403 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13404 | op &= UINT64_C(31); |
| 13405 | op <<= 5; |
| 13406 | Value |= op; |
| 13407 | // op: idx |
| 13408 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13409 | Value |= (op & UINT64_C(4)) << 28; |
| 13410 | Value |= (op & UINT64_C(3)) << 11; |
| 13411 | // op: Xm |
| 13412 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 13413 | op &= UINT64_C(31); |
| 13414 | op <<= 16; |
| 13415 | Value |= op; |
| 13416 | break; |
| 13417 | } |
| 13418 | case AArch64::LD1i8: |
| 13419 | case AArch64::LD2i8: |
| 13420 | case AArch64::LD3i8: |
| 13421 | case AArch64::LD4i8: { |
| 13422 | // op: Vt |
| 13423 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13424 | op &= UINT64_C(31); |
| 13425 | Value |= op; |
| 13426 | // op: Rn |
| 13427 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13428 | op &= UINT64_C(31); |
| 13429 | op <<= 5; |
| 13430 | Value |= op; |
| 13431 | // op: idx |
| 13432 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13433 | Value |= (op & UINT64_C(8)) << 27; |
| 13434 | Value |= (op & UINT64_C(7)) << 10; |
| 13435 | break; |
| 13436 | } |
| 13437 | case AArch64::ST1i8_POST: |
| 13438 | case AArch64::ST2i8_POST: |
| 13439 | case AArch64::ST3i8_POST: |
| 13440 | case AArch64::ST4i8_POST: { |
| 13441 | // op: Vt |
| 13442 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13443 | op &= UINT64_C(31); |
| 13444 | Value |= op; |
| 13445 | // op: Rn |
| 13446 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13447 | op &= UINT64_C(31); |
| 13448 | op <<= 5; |
| 13449 | Value |= op; |
| 13450 | // op: idx |
| 13451 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13452 | Value |= (op & UINT64_C(8)) << 27; |
| 13453 | Value |= (op & UINT64_C(7)) << 10; |
| 13454 | // op: Xm |
| 13455 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 13456 | op &= UINT64_C(31); |
| 13457 | op <<= 16; |
| 13458 | Value |= op; |
| 13459 | break; |
| 13460 | } |
| 13461 | case AArch64::LD1i64: |
| 13462 | case AArch64::LD2i64: |
| 13463 | case AArch64::LD3i64: |
| 13464 | case AArch64::LD4i64: { |
| 13465 | // op: Vt |
| 13466 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13467 | op &= UINT64_C(31); |
| 13468 | Value |= op; |
| 13469 | // op: Rn |
| 13470 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13471 | op &= UINT64_C(31); |
| 13472 | op <<= 5; |
| 13473 | Value |= op; |
| 13474 | // op: idx |
| 13475 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13476 | op &= UINT64_C(1); |
| 13477 | op <<= 30; |
| 13478 | Value |= op; |
| 13479 | break; |
| 13480 | } |
| 13481 | case AArch64::ST1i64_POST: |
| 13482 | case AArch64::ST2i64_POST: |
| 13483 | case AArch64::ST3i64_POST: |
| 13484 | case AArch64::ST4i64_POST: { |
| 13485 | // op: Vt |
| 13486 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13487 | op &= UINT64_C(31); |
| 13488 | Value |= op; |
| 13489 | // op: Rn |
| 13490 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13491 | op &= UINT64_C(31); |
| 13492 | op <<= 5; |
| 13493 | Value |= op; |
| 13494 | // op: idx |
| 13495 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13496 | op &= UINT64_C(1); |
| 13497 | op <<= 30; |
| 13498 | Value |= op; |
| 13499 | // op: Xm |
| 13500 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 13501 | op &= UINT64_C(31); |
| 13502 | op <<= 16; |
| 13503 | Value |= op; |
| 13504 | break; |
| 13505 | } |
| 13506 | case AArch64::LD1i32_POST: |
| 13507 | case AArch64::LD2i32_POST: |
| 13508 | case AArch64::LD3i32_POST: |
| 13509 | case AArch64::LD4i32_POST: { |
| 13510 | // op: Vt |
| 13511 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13512 | op &= UINT64_C(31); |
| 13513 | Value |= op; |
| 13514 | // op: Rn |
| 13515 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 13516 | op &= UINT64_C(31); |
| 13517 | op <<= 5; |
| 13518 | Value |= op; |
| 13519 | // op: idx |
| 13520 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13521 | Value |= (op & UINT64_C(2)) << 29; |
| 13522 | Value |= (op & UINT64_C(1)) << 12; |
| 13523 | // op: Xm |
| 13524 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 13525 | op &= UINT64_C(31); |
| 13526 | op <<= 16; |
| 13527 | Value |= op; |
| 13528 | break; |
| 13529 | } |
| 13530 | case AArch64::LD1i16_POST: |
| 13531 | case AArch64::LD2i16_POST: |
| 13532 | case AArch64::LD3i16_POST: |
| 13533 | case AArch64::LD4i16_POST: { |
| 13534 | // op: Vt |
| 13535 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13536 | op &= UINT64_C(31); |
| 13537 | Value |= op; |
| 13538 | // op: Rn |
| 13539 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 13540 | op &= UINT64_C(31); |
| 13541 | op <<= 5; |
| 13542 | Value |= op; |
| 13543 | // op: idx |
| 13544 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13545 | Value |= (op & UINT64_C(4)) << 28; |
| 13546 | Value |= (op & UINT64_C(3)) << 11; |
| 13547 | // op: Xm |
| 13548 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 13549 | op &= UINT64_C(31); |
| 13550 | op <<= 16; |
| 13551 | Value |= op; |
| 13552 | break; |
| 13553 | } |
| 13554 | case AArch64::LD1i8_POST: |
| 13555 | case AArch64::LD2i8_POST: |
| 13556 | case AArch64::LD3i8_POST: |
| 13557 | case AArch64::LD4i8_POST: { |
| 13558 | // op: Vt |
| 13559 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13560 | op &= UINT64_C(31); |
| 13561 | Value |= op; |
| 13562 | // op: Rn |
| 13563 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 13564 | op &= UINT64_C(31); |
| 13565 | op <<= 5; |
| 13566 | Value |= op; |
| 13567 | // op: idx |
| 13568 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13569 | Value |= (op & UINT64_C(8)) << 27; |
| 13570 | Value |= (op & UINT64_C(7)) << 10; |
| 13571 | // op: Xm |
| 13572 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 13573 | op &= UINT64_C(31); |
| 13574 | op <<= 16; |
| 13575 | Value |= op; |
| 13576 | break; |
| 13577 | } |
| 13578 | case AArch64::LD1i64_POST: |
| 13579 | case AArch64::LD2i64_POST: |
| 13580 | case AArch64::LD3i64_POST: |
| 13581 | case AArch64::LD4i64_POST: { |
| 13582 | // op: Vt |
| 13583 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13584 | op &= UINT64_C(31); |
| 13585 | Value |= op; |
| 13586 | // op: Rn |
| 13587 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 13588 | op &= UINT64_C(31); |
| 13589 | op <<= 5; |
| 13590 | Value |= op; |
| 13591 | // op: idx |
| 13592 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13593 | op &= UINT64_C(1); |
| 13594 | op <<= 30; |
| 13595 | Value |= op; |
| 13596 | // op: Xm |
| 13597 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 13598 | op &= UINT64_C(31); |
| 13599 | op <<= 16; |
| 13600 | Value |= op; |
| 13601 | break; |
| 13602 | } |
| 13603 | case AArch64::STLXRB: |
| 13604 | case AArch64::STLXRH: |
| 13605 | case AArch64::STLXRW: |
| 13606 | case AArch64::STLXRX: |
| 13607 | case AArch64::STXRB: |
| 13608 | case AArch64::STXRH: |
| 13609 | case AArch64::STXRW: |
| 13610 | case AArch64::STXRX: { |
| 13611 | // op: Ws |
| 13612 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13613 | op &= UINT64_C(31); |
| 13614 | op <<= 16; |
| 13615 | Value |= op; |
| 13616 | // op: Rt |
| 13617 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13618 | op &= UINT64_C(31); |
| 13619 | Value |= op; |
| 13620 | // op: Rn |
| 13621 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13622 | op &= UINT64_C(31); |
| 13623 | op <<= 5; |
| 13624 | Value |= op; |
| 13625 | Value = fixLoadStoreExclusive<1,0>(MI, Value, STI); |
| 13626 | break; |
| 13627 | } |
| 13628 | case AArch64::STLXPW: |
| 13629 | case AArch64::STLXPX: |
| 13630 | case AArch64::STXPW: |
| 13631 | case AArch64::STXPX: { |
| 13632 | // op: Ws |
| 13633 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13634 | op &= UINT64_C(31); |
| 13635 | op <<= 16; |
| 13636 | Value |= op; |
| 13637 | // op: Rt |
| 13638 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13639 | op &= UINT64_C(31); |
| 13640 | Value |= op; |
| 13641 | // op: Rt2 |
| 13642 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13643 | op &= UINT64_C(31); |
| 13644 | op <<= 10; |
| 13645 | Value |= op; |
| 13646 | // op: Rn |
| 13647 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13648 | op &= UINT64_C(31); |
| 13649 | op <<= 5; |
| 13650 | Value |= op; |
| 13651 | break; |
| 13652 | } |
| 13653 | case AArch64::ADR: |
| 13654 | case AArch64::ADRP: { |
| 13655 | // op: Xd |
| 13656 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13657 | op &= UINT64_C(31); |
| 13658 | Value |= op; |
| 13659 | // op: label |
| 13660 | op = getAdrLabelOpValue(MI, 1, Fixups, STI); |
| 13661 | Value |= (op & UINT64_C(3)) << 29; |
| 13662 | Value |= (op & UINT64_C(2097148)) << 3; |
| 13663 | break; |
| 13664 | } |
| 13665 | case AArch64::CPY_ZPzI_B: |
| 13666 | case AArch64::CPY_ZPzI_D: |
| 13667 | case AArch64::CPY_ZPzI_H: |
| 13668 | case AArch64::CPY_ZPzI_S: { |
| 13669 | // op: Zd |
| 13670 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13671 | op &= UINT64_C(31); |
| 13672 | Value |= op; |
| 13673 | // op: Pg |
| 13674 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13675 | op &= UINT64_C(15); |
| 13676 | op <<= 16; |
| 13677 | Value |= op; |
| 13678 | // op: imm |
| 13679 | op = getImm8OptLsl(MI, 2, Fixups, STI); |
| 13680 | op &= UINT64_C(511); |
| 13681 | op <<= 5; |
| 13682 | Value |= op; |
| 13683 | break; |
| 13684 | } |
| 13685 | case AArch64::CPY_ZPmI_B: |
| 13686 | case AArch64::CPY_ZPmI_D: |
| 13687 | case AArch64::CPY_ZPmI_H: |
| 13688 | case AArch64::CPY_ZPmI_S: { |
| 13689 | // op: Zd |
| 13690 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13691 | op &= UINT64_C(31); |
| 13692 | Value |= op; |
| 13693 | // op: Pg |
| 13694 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13695 | op &= UINT64_C(15); |
| 13696 | op <<= 16; |
| 13697 | Value |= op; |
| 13698 | // op: imm |
| 13699 | op = getImm8OptLsl(MI, 3, Fixups, STI); |
| 13700 | op &= UINT64_C(511); |
| 13701 | op <<= 5; |
| 13702 | Value |= op; |
| 13703 | break; |
| 13704 | } |
| 13705 | case AArch64::BFCVTNT_ZPmZ: |
| 13706 | case AArch64::BFCVT_ZPmZ: |
| 13707 | case AArch64::RBIT_ZPmZ_B: |
| 13708 | case AArch64::RBIT_ZPmZ_D: |
| 13709 | case AArch64::RBIT_ZPmZ_H: |
| 13710 | case AArch64::RBIT_ZPmZ_S: |
| 13711 | case AArch64::REVB_ZPmZ_D: |
| 13712 | case AArch64::REVB_ZPmZ_H: |
| 13713 | case AArch64::REVB_ZPmZ_S: |
| 13714 | case AArch64::REVH_ZPmZ_D: |
| 13715 | case AArch64::REVH_ZPmZ_S: |
| 13716 | case AArch64::REVW_ZPmZ_D: { |
| 13717 | // op: Zd |
| 13718 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13719 | op &= UINT64_C(31); |
| 13720 | Value |= op; |
| 13721 | // op: Pg |
| 13722 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13723 | op &= UINT64_C(7); |
| 13724 | op <<= 10; |
| 13725 | Value |= op; |
| 13726 | // op: Zn |
| 13727 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13728 | op &= UINT64_C(31); |
| 13729 | op <<= 5; |
| 13730 | Value |= op; |
| 13731 | break; |
| 13732 | } |
| 13733 | case AArch64::INDEX_RR_B: |
| 13734 | case AArch64::INDEX_RR_D: |
| 13735 | case AArch64::INDEX_RR_H: |
| 13736 | case AArch64::INDEX_RR_S: { |
| 13737 | // op: Zd |
| 13738 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13739 | op &= UINT64_C(31); |
| 13740 | Value |= op; |
| 13741 | // op: Rm |
| 13742 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13743 | op &= UINT64_C(31); |
| 13744 | op <<= 16; |
| 13745 | Value |= op; |
| 13746 | // op: Rn |
| 13747 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13748 | op &= UINT64_C(31); |
| 13749 | op <<= 5; |
| 13750 | Value |= op; |
| 13751 | break; |
| 13752 | } |
| 13753 | case AArch64::ADD_ZZZ_B: |
| 13754 | case AArch64::ADD_ZZZ_D: |
| 13755 | case AArch64::ADD_ZZZ_H: |
| 13756 | case AArch64::ADD_ZZZ_S: |
| 13757 | case AArch64::AND_ZZZ: |
| 13758 | case AArch64::ASR_WIDE_ZZZ_B: |
| 13759 | case AArch64::ASR_WIDE_ZZZ_H: |
| 13760 | case AArch64::ASR_WIDE_ZZZ_S: |
| 13761 | case AArch64::BIC_ZZZ: |
| 13762 | case AArch64::EOR_ZZZ: |
| 13763 | case AArch64::FADD_ZZZ_D: |
| 13764 | case AArch64::FADD_ZZZ_H: |
| 13765 | case AArch64::FADD_ZZZ_S: |
| 13766 | case AArch64::FMUL_ZZZ_D: |
| 13767 | case AArch64::FMUL_ZZZ_H: |
| 13768 | case AArch64::FMUL_ZZZ_S: |
| 13769 | case AArch64::FRECPS_ZZZ_D: |
| 13770 | case AArch64::FRECPS_ZZZ_H: |
| 13771 | case AArch64::FRECPS_ZZZ_S: |
| 13772 | case AArch64::FRSQRTS_ZZZ_D: |
| 13773 | case AArch64::FRSQRTS_ZZZ_H: |
| 13774 | case AArch64::FRSQRTS_ZZZ_S: |
| 13775 | case AArch64::FSUB_ZZZ_D: |
| 13776 | case AArch64::FSUB_ZZZ_H: |
| 13777 | case AArch64::FSUB_ZZZ_S: |
| 13778 | case AArch64::FTSMUL_ZZZ_D: |
| 13779 | case AArch64::FTSMUL_ZZZ_H: |
| 13780 | case AArch64::FTSMUL_ZZZ_S: |
| 13781 | case AArch64::FTSSEL_ZZZ_D: |
| 13782 | case AArch64::FTSSEL_ZZZ_H: |
| 13783 | case AArch64::FTSSEL_ZZZ_S: |
| 13784 | case AArch64::LSL_WIDE_ZZZ_B: |
| 13785 | case AArch64::LSL_WIDE_ZZZ_H: |
| 13786 | case AArch64::LSL_WIDE_ZZZ_S: |
| 13787 | case AArch64::LSR_WIDE_ZZZ_B: |
| 13788 | case AArch64::LSR_WIDE_ZZZ_H: |
| 13789 | case AArch64::LSR_WIDE_ZZZ_S: |
| 13790 | case AArch64::MUL_ZZZ_B: |
| 13791 | case AArch64::MUL_ZZZ_D: |
| 13792 | case AArch64::MUL_ZZZ_H: |
| 13793 | case AArch64::MUL_ZZZ_S: |
| 13794 | case AArch64::ORR_ZZZ: |
| 13795 | case AArch64::PMUL_ZZZ_B: |
| 13796 | case AArch64::SMULH_ZZZ_B: |
| 13797 | case AArch64::SMULH_ZZZ_D: |
| 13798 | case AArch64::SMULH_ZZZ_H: |
| 13799 | case AArch64::SMULH_ZZZ_S: |
| 13800 | case AArch64::SQADD_ZZZ_B: |
| 13801 | case AArch64::SQADD_ZZZ_D: |
| 13802 | case AArch64::SQADD_ZZZ_H: |
| 13803 | case AArch64::SQADD_ZZZ_S: |
| 13804 | case AArch64::SQDMULH_ZZZ_B: |
| 13805 | case AArch64::SQDMULH_ZZZ_D: |
| 13806 | case AArch64::SQDMULH_ZZZ_H: |
| 13807 | case AArch64::SQDMULH_ZZZ_S: |
| 13808 | case AArch64::SQRDMULH_ZZZ_B: |
| 13809 | case AArch64::SQRDMULH_ZZZ_D: |
| 13810 | case AArch64::SQRDMULH_ZZZ_H: |
| 13811 | case AArch64::SQRDMULH_ZZZ_S: |
| 13812 | case AArch64::SQSUB_ZZZ_B: |
| 13813 | case AArch64::SQSUB_ZZZ_D: |
| 13814 | case AArch64::SQSUB_ZZZ_H: |
| 13815 | case AArch64::SQSUB_ZZZ_S: |
| 13816 | case AArch64::SUB_ZZZ_B: |
| 13817 | case AArch64::SUB_ZZZ_D: |
| 13818 | case AArch64::SUB_ZZZ_H: |
| 13819 | case AArch64::SUB_ZZZ_S: |
| 13820 | case AArch64::TBL_ZZZZ_B: |
| 13821 | case AArch64::TBL_ZZZZ_D: |
| 13822 | case AArch64::TBL_ZZZZ_H: |
| 13823 | case AArch64::TBL_ZZZZ_S: |
| 13824 | case AArch64::TBL_ZZZ_B: |
| 13825 | case AArch64::TBL_ZZZ_D: |
| 13826 | case AArch64::TBL_ZZZ_H: |
| 13827 | case AArch64::TBL_ZZZ_S: |
| 13828 | case AArch64::TRN1_ZZZ_B: |
| 13829 | case AArch64::TRN1_ZZZ_D: |
| 13830 | case AArch64::TRN1_ZZZ_H: |
| 13831 | case AArch64::TRN1_ZZZ_Q: |
| 13832 | case AArch64::TRN1_ZZZ_S: |
| 13833 | case AArch64::TRN2_ZZZ_B: |
| 13834 | case AArch64::TRN2_ZZZ_D: |
| 13835 | case AArch64::TRN2_ZZZ_H: |
| 13836 | case AArch64::TRN2_ZZZ_Q: |
| 13837 | case AArch64::TRN2_ZZZ_S: |
| 13838 | case AArch64::UMULH_ZZZ_B: |
| 13839 | case AArch64::UMULH_ZZZ_D: |
| 13840 | case AArch64::UMULH_ZZZ_H: |
| 13841 | case AArch64::UMULH_ZZZ_S: |
| 13842 | case AArch64::UQADD_ZZZ_B: |
| 13843 | case AArch64::UQADD_ZZZ_D: |
| 13844 | case AArch64::UQADD_ZZZ_H: |
| 13845 | case AArch64::UQADD_ZZZ_S: |
| 13846 | case AArch64::UQSUB_ZZZ_B: |
| 13847 | case AArch64::UQSUB_ZZZ_D: |
| 13848 | case AArch64::UQSUB_ZZZ_H: |
| 13849 | case AArch64::UQSUB_ZZZ_S: |
| 13850 | case AArch64::UZP1_ZZZ_B: |
| 13851 | case AArch64::UZP1_ZZZ_D: |
| 13852 | case AArch64::UZP1_ZZZ_H: |
| 13853 | case AArch64::UZP1_ZZZ_Q: |
| 13854 | case AArch64::UZP1_ZZZ_S: |
| 13855 | case AArch64::UZP2_ZZZ_B: |
| 13856 | case AArch64::UZP2_ZZZ_D: |
| 13857 | case AArch64::UZP2_ZZZ_H: |
| 13858 | case AArch64::UZP2_ZZZ_Q: |
| 13859 | case AArch64::UZP2_ZZZ_S: |
| 13860 | case AArch64::ZIP1_ZZZ_B: |
| 13861 | case AArch64::ZIP1_ZZZ_D: |
| 13862 | case AArch64::ZIP1_ZZZ_H: |
| 13863 | case AArch64::ZIP1_ZZZ_Q: |
| 13864 | case AArch64::ZIP1_ZZZ_S: |
| 13865 | case AArch64::ZIP2_ZZZ_B: |
| 13866 | case AArch64::ZIP2_ZZZ_D: |
| 13867 | case AArch64::ZIP2_ZZZ_H: |
| 13868 | case AArch64::ZIP2_ZZZ_Q: |
| 13869 | case AArch64::ZIP2_ZZZ_S: { |
| 13870 | // op: Zd |
| 13871 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13872 | op &= UINT64_C(31); |
| 13873 | Value |= op; |
| 13874 | // op: Zm |
| 13875 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13876 | op &= UINT64_C(31); |
| 13877 | op <<= 16; |
| 13878 | Value |= op; |
| 13879 | // op: Zn |
| 13880 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13881 | op &= UINT64_C(31); |
| 13882 | op <<= 5; |
| 13883 | Value |= op; |
| 13884 | break; |
| 13885 | } |
| 13886 | case AArch64::TBX_ZZZ_B: |
| 13887 | case AArch64::TBX_ZZZ_D: |
| 13888 | case AArch64::TBX_ZZZ_H: |
| 13889 | case AArch64::TBX_ZZZ_S: { |
| 13890 | // op: Zd |
| 13891 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13892 | op &= UINT64_C(31); |
| 13893 | Value |= op; |
| 13894 | // op: Zm |
| 13895 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13896 | op &= UINT64_C(31); |
| 13897 | op <<= 16; |
| 13898 | Value |= op; |
| 13899 | // op: Zn |
| 13900 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13901 | op &= UINT64_C(31); |
| 13902 | op <<= 5; |
| 13903 | Value |= op; |
| 13904 | break; |
| 13905 | } |
| 13906 | case AArch64::FEXPA_ZZ_D: |
| 13907 | case AArch64::FEXPA_ZZ_H: |
| 13908 | case AArch64::FEXPA_ZZ_S: |
| 13909 | case AArch64::FRECPE_ZZ_D: |
| 13910 | case AArch64::FRECPE_ZZ_H: |
| 13911 | case AArch64::FRECPE_ZZ_S: |
| 13912 | case AArch64::FRSQRTE_ZZ_D: |
| 13913 | case AArch64::FRSQRTE_ZZ_H: |
| 13914 | case AArch64::FRSQRTE_ZZ_S: |
| 13915 | case AArch64::MOVPRFX_ZZ: |
| 13916 | case AArch64::REV_ZZ_B: |
| 13917 | case AArch64::REV_ZZ_D: |
| 13918 | case AArch64::REV_ZZ_H: |
| 13919 | case AArch64::REV_ZZ_S: |
| 13920 | case AArch64::SQXTNB_ZZ_B: |
| 13921 | case AArch64::SQXTNB_ZZ_H: |
| 13922 | case AArch64::SQXTNB_ZZ_S: |
| 13923 | case AArch64::SQXTUNB_ZZ_B: |
| 13924 | case AArch64::SQXTUNB_ZZ_H: |
| 13925 | case AArch64::SQXTUNB_ZZ_S: |
| 13926 | case AArch64::SUNPKHI_ZZ_D: |
| 13927 | case AArch64::SUNPKHI_ZZ_H: |
| 13928 | case AArch64::SUNPKHI_ZZ_S: |
| 13929 | case AArch64::SUNPKLO_ZZ_D: |
| 13930 | case AArch64::SUNPKLO_ZZ_H: |
| 13931 | case AArch64::SUNPKLO_ZZ_S: |
| 13932 | case AArch64::UQXTNB_ZZ_B: |
| 13933 | case AArch64::UQXTNB_ZZ_H: |
| 13934 | case AArch64::UQXTNB_ZZ_S: |
| 13935 | case AArch64::UUNPKHI_ZZ_D: |
| 13936 | case AArch64::UUNPKHI_ZZ_H: |
| 13937 | case AArch64::UUNPKHI_ZZ_S: |
| 13938 | case AArch64::UUNPKLO_ZZ_D: |
| 13939 | case AArch64::UUNPKLO_ZZ_H: |
| 13940 | case AArch64::UUNPKLO_ZZ_S: { |
| 13941 | // op: Zd |
| 13942 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13943 | op &= UINT64_C(31); |
| 13944 | Value |= op; |
| 13945 | // op: Zn |
| 13946 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13947 | op &= UINT64_C(31); |
| 13948 | op <<= 5; |
| 13949 | Value |= op; |
| 13950 | break; |
| 13951 | } |
| 13952 | case AArch64::SMULLB_ZZZI_D: |
| 13953 | case AArch64::SMULLT_ZZZI_D: |
| 13954 | case AArch64::SQDMULLB_ZZZI_D: |
| 13955 | case AArch64::SQDMULLT_ZZZI_D: |
| 13956 | case AArch64::UMULLB_ZZZI_D: |
| 13957 | case AArch64::UMULLT_ZZZI_D: { |
| 13958 | // op: Zd |
| 13959 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13960 | op &= UINT64_C(31); |
| 13961 | Value |= op; |
| 13962 | // op: Zn |
| 13963 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13964 | op &= UINT64_C(31); |
| 13965 | op <<= 5; |
| 13966 | Value |= op; |
| 13967 | // op: Zm |
| 13968 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13969 | op &= UINT64_C(15); |
| 13970 | op <<= 16; |
| 13971 | Value |= op; |
| 13972 | // op: iop |
| 13973 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13974 | Value |= (op & UINT64_C(2)) << 19; |
| 13975 | Value |= (op & UINT64_C(1)) << 11; |
| 13976 | break; |
| 13977 | } |
| 13978 | case AArch64::FMUL_ZZZI_D: |
| 13979 | case AArch64::MUL_ZZZI_D: |
| 13980 | case AArch64::SQDMULH_ZZZI_D: |
| 13981 | case AArch64::SQRDMULH_ZZZI_D: { |
| 13982 | // op: Zd |
| 13983 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 13984 | op &= UINT64_C(31); |
| 13985 | Value |= op; |
| 13986 | // op: Zn |
| 13987 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 13988 | op &= UINT64_C(31); |
| 13989 | op <<= 5; |
| 13990 | Value |= op; |
| 13991 | // op: Zm |
| 13992 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 13993 | op &= UINT64_C(15); |
| 13994 | op <<= 16; |
| 13995 | Value |= op; |
| 13996 | // op: iop |
| 13997 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 13998 | op &= UINT64_C(1); |
| 13999 | op <<= 20; |
| 14000 | Value |= op; |
| 14001 | break; |
| 14002 | } |
| 14003 | case AArch64::ADDHNB_ZZZ_B: |
| 14004 | case AArch64::ADDHNB_ZZZ_H: |
| 14005 | case AArch64::ADDHNB_ZZZ_S: |
| 14006 | case AArch64::ADR_LSL_ZZZ_D_0: |
| 14007 | case AArch64::ADR_LSL_ZZZ_D_1: |
| 14008 | case AArch64::ADR_LSL_ZZZ_D_2: |
| 14009 | case AArch64::ADR_LSL_ZZZ_D_3: |
| 14010 | case AArch64::ADR_LSL_ZZZ_S_0: |
| 14011 | case AArch64::ADR_LSL_ZZZ_S_1: |
| 14012 | case AArch64::ADR_LSL_ZZZ_S_2: |
| 14013 | case AArch64::ADR_LSL_ZZZ_S_3: |
| 14014 | case AArch64::ADR_SXTW_ZZZ_D_0: |
| 14015 | case AArch64::ADR_SXTW_ZZZ_D_1: |
| 14016 | case AArch64::ADR_SXTW_ZZZ_D_2: |
| 14017 | case AArch64::ADR_SXTW_ZZZ_D_3: |
| 14018 | case AArch64::ADR_UXTW_ZZZ_D_0: |
| 14019 | case AArch64::ADR_UXTW_ZZZ_D_1: |
| 14020 | case AArch64::ADR_UXTW_ZZZ_D_2: |
| 14021 | case AArch64::ADR_UXTW_ZZZ_D_3: |
| 14022 | case AArch64::BDEP_ZZZ_B: |
| 14023 | case AArch64::BDEP_ZZZ_D: |
| 14024 | case AArch64::BDEP_ZZZ_H: |
| 14025 | case AArch64::BDEP_ZZZ_S: |
| 14026 | case AArch64::BEXT_ZZZ_B: |
| 14027 | case AArch64::BEXT_ZZZ_D: |
| 14028 | case AArch64::BEXT_ZZZ_H: |
| 14029 | case AArch64::BEXT_ZZZ_S: |
| 14030 | case AArch64::BGRP_ZZZ_B: |
| 14031 | case AArch64::BGRP_ZZZ_D: |
| 14032 | case AArch64::BGRP_ZZZ_H: |
| 14033 | case AArch64::BGRP_ZZZ_S: |
| 14034 | case AArch64::HISTSEG_ZZZ: |
| 14035 | case AArch64::PMULLB_ZZZ_D: |
| 14036 | case AArch64::PMULLB_ZZZ_H: |
| 14037 | case AArch64::PMULLB_ZZZ_Q: |
| 14038 | case AArch64::PMULLT_ZZZ_D: |
| 14039 | case AArch64::PMULLT_ZZZ_H: |
| 14040 | case AArch64::PMULLT_ZZZ_Q: |
| 14041 | case AArch64::RADDHNB_ZZZ_B: |
| 14042 | case AArch64::RADDHNB_ZZZ_H: |
| 14043 | case AArch64::RADDHNB_ZZZ_S: |
| 14044 | case AArch64::RAX1_ZZZ_D: |
| 14045 | case AArch64::RSUBHNB_ZZZ_B: |
| 14046 | case AArch64::RSUBHNB_ZZZ_H: |
| 14047 | case AArch64::RSUBHNB_ZZZ_S: |
| 14048 | case AArch64::SABDLB_ZZZ_D: |
| 14049 | case AArch64::SABDLB_ZZZ_H: |
| 14050 | case AArch64::SABDLB_ZZZ_S: |
| 14051 | case AArch64::SABDLT_ZZZ_D: |
| 14052 | case AArch64::SABDLT_ZZZ_H: |
| 14053 | case AArch64::SABDLT_ZZZ_S: |
| 14054 | case AArch64::SADDLBT_ZZZ_D: |
| 14055 | case AArch64::SADDLBT_ZZZ_H: |
| 14056 | case AArch64::SADDLBT_ZZZ_S: |
| 14057 | case AArch64::SADDLB_ZZZ_D: |
| 14058 | case AArch64::SADDLB_ZZZ_H: |
| 14059 | case AArch64::SADDLB_ZZZ_S: |
| 14060 | case AArch64::SADDLT_ZZZ_D: |
| 14061 | case AArch64::SADDLT_ZZZ_H: |
| 14062 | case AArch64::SADDLT_ZZZ_S: |
| 14063 | case AArch64::SADDWB_ZZZ_D: |
| 14064 | case AArch64::SADDWB_ZZZ_H: |
| 14065 | case AArch64::SADDWB_ZZZ_S: |
| 14066 | case AArch64::SADDWT_ZZZ_D: |
| 14067 | case AArch64::SADDWT_ZZZ_H: |
| 14068 | case AArch64::SADDWT_ZZZ_S: |
| 14069 | case AArch64::SM4EKEY_ZZZ_S: |
| 14070 | case AArch64::SMULLB_ZZZ_D: |
| 14071 | case AArch64::SMULLB_ZZZ_H: |
| 14072 | case AArch64::SMULLB_ZZZ_S: |
| 14073 | case AArch64::SMULLT_ZZZ_D: |
| 14074 | case AArch64::SMULLT_ZZZ_H: |
| 14075 | case AArch64::SMULLT_ZZZ_S: |
| 14076 | case AArch64::SQDMULLB_ZZZ_D: |
| 14077 | case AArch64::SQDMULLB_ZZZ_H: |
| 14078 | case AArch64::SQDMULLB_ZZZ_S: |
| 14079 | case AArch64::SQDMULLT_ZZZ_D: |
| 14080 | case AArch64::SQDMULLT_ZZZ_H: |
| 14081 | case AArch64::SQDMULLT_ZZZ_S: |
| 14082 | case AArch64::SSUBLBT_ZZZ_D: |
| 14083 | case AArch64::SSUBLBT_ZZZ_H: |
| 14084 | case AArch64::SSUBLBT_ZZZ_S: |
| 14085 | case AArch64::SSUBLB_ZZZ_D: |
| 14086 | case AArch64::SSUBLB_ZZZ_H: |
| 14087 | case AArch64::SSUBLB_ZZZ_S: |
| 14088 | case AArch64::SSUBLTB_ZZZ_D: |
| 14089 | case AArch64::SSUBLTB_ZZZ_H: |
| 14090 | case AArch64::SSUBLTB_ZZZ_S: |
| 14091 | case AArch64::SSUBLT_ZZZ_D: |
| 14092 | case AArch64::SSUBLT_ZZZ_H: |
| 14093 | case AArch64::SSUBLT_ZZZ_S: |
| 14094 | case AArch64::SSUBWB_ZZZ_D: |
| 14095 | case AArch64::SSUBWB_ZZZ_H: |
| 14096 | case AArch64::SSUBWB_ZZZ_S: |
| 14097 | case AArch64::SSUBWT_ZZZ_D: |
| 14098 | case AArch64::SSUBWT_ZZZ_H: |
| 14099 | case AArch64::SSUBWT_ZZZ_S: |
| 14100 | case AArch64::SUBHNB_ZZZ_B: |
| 14101 | case AArch64::SUBHNB_ZZZ_H: |
| 14102 | case AArch64::SUBHNB_ZZZ_S: |
| 14103 | case AArch64::UABDLB_ZZZ_D: |
| 14104 | case AArch64::UABDLB_ZZZ_H: |
| 14105 | case AArch64::UABDLB_ZZZ_S: |
| 14106 | case AArch64::UABDLT_ZZZ_D: |
| 14107 | case AArch64::UABDLT_ZZZ_H: |
| 14108 | case AArch64::UABDLT_ZZZ_S: |
| 14109 | case AArch64::UADDLB_ZZZ_D: |
| 14110 | case AArch64::UADDLB_ZZZ_H: |
| 14111 | case AArch64::UADDLB_ZZZ_S: |
| 14112 | case AArch64::UADDLT_ZZZ_D: |
| 14113 | case AArch64::UADDLT_ZZZ_H: |
| 14114 | case AArch64::UADDLT_ZZZ_S: |
| 14115 | case AArch64::UADDWB_ZZZ_D: |
| 14116 | case AArch64::UADDWB_ZZZ_H: |
| 14117 | case AArch64::UADDWB_ZZZ_S: |
| 14118 | case AArch64::UADDWT_ZZZ_D: |
| 14119 | case AArch64::UADDWT_ZZZ_H: |
| 14120 | case AArch64::UADDWT_ZZZ_S: |
| 14121 | case AArch64::UMULLB_ZZZ_D: |
| 14122 | case AArch64::UMULLB_ZZZ_H: |
| 14123 | case AArch64::UMULLB_ZZZ_S: |
| 14124 | case AArch64::UMULLT_ZZZ_D: |
| 14125 | case AArch64::UMULLT_ZZZ_H: |
| 14126 | case AArch64::UMULLT_ZZZ_S: |
| 14127 | case AArch64::USUBLB_ZZZ_D: |
| 14128 | case AArch64::USUBLB_ZZZ_H: |
| 14129 | case AArch64::USUBLB_ZZZ_S: |
| 14130 | case AArch64::USUBLT_ZZZ_D: |
| 14131 | case AArch64::USUBLT_ZZZ_H: |
| 14132 | case AArch64::USUBLT_ZZZ_S: |
| 14133 | case AArch64::USUBWB_ZZZ_D: |
| 14134 | case AArch64::USUBWB_ZZZ_H: |
| 14135 | case AArch64::USUBWB_ZZZ_S: |
| 14136 | case AArch64::USUBWT_ZZZ_D: |
| 14137 | case AArch64::USUBWT_ZZZ_H: |
| 14138 | case AArch64::USUBWT_ZZZ_S: { |
| 14139 | // op: Zd |
| 14140 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14141 | op &= UINT64_C(31); |
| 14142 | Value |= op; |
| 14143 | // op: Zn |
| 14144 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14145 | op &= UINT64_C(31); |
| 14146 | op <<= 5; |
| 14147 | Value |= op; |
| 14148 | // op: Zm |
| 14149 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14150 | op &= UINT64_C(31); |
| 14151 | op <<= 16; |
| 14152 | Value |= op; |
| 14153 | break; |
| 14154 | } |
| 14155 | case AArch64::FMUL_ZZZI_H: |
| 14156 | case AArch64::MUL_ZZZI_H: |
| 14157 | case AArch64::SQDMULH_ZZZI_H: |
| 14158 | case AArch64::SQRDMULH_ZZZI_H: { |
| 14159 | // op: Zd |
| 14160 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14161 | op &= UINT64_C(31); |
| 14162 | Value |= op; |
| 14163 | // op: Zn |
| 14164 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14165 | op &= UINT64_C(31); |
| 14166 | op <<= 5; |
| 14167 | Value |= op; |
| 14168 | // op: Zm |
| 14169 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14170 | op &= UINT64_C(7); |
| 14171 | op <<= 16; |
| 14172 | Value |= op; |
| 14173 | // op: iop |
| 14174 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14175 | Value |= (op & UINT64_C(4)) << 20; |
| 14176 | Value |= (op & UINT64_C(3)) << 19; |
| 14177 | break; |
| 14178 | } |
| 14179 | case AArch64::SMULLB_ZZZI_S: |
| 14180 | case AArch64::SMULLT_ZZZI_S: |
| 14181 | case AArch64::SQDMULLB_ZZZI_S: |
| 14182 | case AArch64::SQDMULLT_ZZZI_S: |
| 14183 | case AArch64::UMULLB_ZZZI_S: |
| 14184 | case AArch64::UMULLT_ZZZI_S: { |
| 14185 | // op: Zd |
| 14186 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14187 | op &= UINT64_C(31); |
| 14188 | Value |= op; |
| 14189 | // op: Zn |
| 14190 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14191 | op &= UINT64_C(31); |
| 14192 | op <<= 5; |
| 14193 | Value |= op; |
| 14194 | // op: Zm |
| 14195 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14196 | op &= UINT64_C(7); |
| 14197 | op <<= 16; |
| 14198 | Value |= op; |
| 14199 | // op: iop |
| 14200 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14201 | Value |= (op & UINT64_C(6)) << 18; |
| 14202 | Value |= (op & UINT64_C(1)) << 11; |
| 14203 | break; |
| 14204 | } |
| 14205 | case AArch64::FMUL_ZZZI_S: |
| 14206 | case AArch64::MUL_ZZZI_S: |
| 14207 | case AArch64::SQDMULH_ZZZI_S: |
| 14208 | case AArch64::SQRDMULH_ZZZI_S: { |
| 14209 | // op: Zd |
| 14210 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14211 | op &= UINT64_C(31); |
| 14212 | Value |= op; |
| 14213 | // op: Zn |
| 14214 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14215 | op &= UINT64_C(31); |
| 14216 | op <<= 5; |
| 14217 | Value |= op; |
| 14218 | // op: Zm |
| 14219 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14220 | op &= UINT64_C(7); |
| 14221 | op <<= 16; |
| 14222 | Value |= op; |
| 14223 | // op: iop |
| 14224 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14225 | op &= UINT64_C(3); |
| 14226 | op <<= 19; |
| 14227 | Value |= op; |
| 14228 | break; |
| 14229 | } |
| 14230 | case AArch64::DUP_ZZI_S: { |
| 14231 | // op: Zd |
| 14232 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14233 | op &= UINT64_C(31); |
| 14234 | Value |= op; |
| 14235 | // op: Zn |
| 14236 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14237 | op &= UINT64_C(31); |
| 14238 | op <<= 5; |
| 14239 | Value |= op; |
| 14240 | // op: idx |
| 14241 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14242 | Value |= (op & UINT64_C(12)) << 20; |
| 14243 | Value |= (op & UINT64_C(3)) << 19; |
| 14244 | break; |
| 14245 | } |
| 14246 | case AArch64::DUP_ZZI_H: { |
| 14247 | // op: Zd |
| 14248 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14249 | op &= UINT64_C(31); |
| 14250 | Value |= op; |
| 14251 | // op: Zn |
| 14252 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14253 | op &= UINT64_C(31); |
| 14254 | op <<= 5; |
| 14255 | Value |= op; |
| 14256 | // op: idx |
| 14257 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14258 | Value |= (op & UINT64_C(24)) << 19; |
| 14259 | Value |= (op & UINT64_C(7)) << 18; |
| 14260 | break; |
| 14261 | } |
| 14262 | case AArch64::DUP_ZZI_B: { |
| 14263 | // op: Zd |
| 14264 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14265 | op &= UINT64_C(31); |
| 14266 | Value |= op; |
| 14267 | // op: Zn |
| 14268 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14269 | op &= UINT64_C(31); |
| 14270 | op <<= 5; |
| 14271 | Value |= op; |
| 14272 | // op: idx |
| 14273 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14274 | Value |= (op & UINT64_C(48)) << 18; |
| 14275 | Value |= (op & UINT64_C(15)) << 17; |
| 14276 | break; |
| 14277 | } |
| 14278 | case AArch64::DUP_ZZI_D: { |
| 14279 | // op: Zd |
| 14280 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14281 | op &= UINT64_C(31); |
| 14282 | Value |= op; |
| 14283 | // op: Zn |
| 14284 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14285 | op &= UINT64_C(31); |
| 14286 | op <<= 5; |
| 14287 | Value |= op; |
| 14288 | // op: idx |
| 14289 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14290 | Value |= (op & UINT64_C(6)) << 21; |
| 14291 | Value |= (op & UINT64_C(1)) << 20; |
| 14292 | break; |
| 14293 | } |
| 14294 | case AArch64::DUP_ZZI_Q: { |
| 14295 | // op: Zd |
| 14296 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14297 | op &= UINT64_C(31); |
| 14298 | Value |= op; |
| 14299 | // op: Zn |
| 14300 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14301 | op &= UINT64_C(31); |
| 14302 | op <<= 5; |
| 14303 | Value |= op; |
| 14304 | // op: idx |
| 14305 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14306 | op &= UINT64_C(3); |
| 14307 | op <<= 22; |
| 14308 | Value |= op; |
| 14309 | break; |
| 14310 | } |
| 14311 | case AArch64::LSL_ZZI_H: |
| 14312 | case AArch64::SSHLLB_ZZI_S: |
| 14313 | case AArch64::SSHLLT_ZZI_S: |
| 14314 | case AArch64::USHLLB_ZZI_S: |
| 14315 | case AArch64::USHLLT_ZZI_S: { |
| 14316 | // op: Zd |
| 14317 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14318 | op &= UINT64_C(31); |
| 14319 | Value |= op; |
| 14320 | // op: Zn |
| 14321 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14322 | op &= UINT64_C(31); |
| 14323 | op <<= 5; |
| 14324 | Value |= op; |
| 14325 | // op: imm |
| 14326 | op = getVecShiftL16OpValue(MI, 2, Fixups, STI); |
| 14327 | op &= UINT64_C(15); |
| 14328 | op <<= 16; |
| 14329 | Value |= op; |
| 14330 | break; |
| 14331 | } |
| 14332 | case AArch64::LSL_ZZI_S: |
| 14333 | case AArch64::SSHLLB_ZZI_D: |
| 14334 | case AArch64::SSHLLT_ZZI_D: |
| 14335 | case AArch64::USHLLB_ZZI_D: |
| 14336 | case AArch64::USHLLT_ZZI_D: { |
| 14337 | // op: Zd |
| 14338 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14339 | op &= UINT64_C(31); |
| 14340 | Value |= op; |
| 14341 | // op: Zn |
| 14342 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14343 | op &= UINT64_C(31); |
| 14344 | op <<= 5; |
| 14345 | Value |= op; |
| 14346 | // op: imm |
| 14347 | op = getVecShiftL32OpValue(MI, 2, Fixups, STI); |
| 14348 | op &= UINT64_C(31); |
| 14349 | op <<= 16; |
| 14350 | Value |= op; |
| 14351 | break; |
| 14352 | } |
| 14353 | case AArch64::LSL_ZZI_D: { |
| 14354 | // op: Zd |
| 14355 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14356 | op &= UINT64_C(31); |
| 14357 | Value |= op; |
| 14358 | // op: Zn |
| 14359 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14360 | op &= UINT64_C(31); |
| 14361 | op <<= 5; |
| 14362 | Value |= op; |
| 14363 | // op: imm |
| 14364 | op = getVecShiftL64OpValue(MI, 2, Fixups, STI); |
| 14365 | Value |= (op & UINT64_C(32)) << 17; |
| 14366 | Value |= (op & UINT64_C(31)) << 16; |
| 14367 | break; |
| 14368 | } |
| 14369 | case AArch64::LSL_ZZI_B: |
| 14370 | case AArch64::SSHLLB_ZZI_H: |
| 14371 | case AArch64::SSHLLT_ZZI_H: |
| 14372 | case AArch64::USHLLB_ZZI_H: |
| 14373 | case AArch64::USHLLT_ZZI_H: { |
| 14374 | // op: Zd |
| 14375 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14376 | op &= UINT64_C(31); |
| 14377 | Value |= op; |
| 14378 | // op: Zn |
| 14379 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14380 | op &= UINT64_C(31); |
| 14381 | op <<= 5; |
| 14382 | Value |= op; |
| 14383 | // op: imm |
| 14384 | op = getVecShiftL8OpValue(MI, 2, Fixups, STI); |
| 14385 | op &= UINT64_C(7); |
| 14386 | op <<= 16; |
| 14387 | Value |= op; |
| 14388 | break; |
| 14389 | } |
| 14390 | case AArch64::ASR_ZZI_H: |
| 14391 | case AArch64::LSR_ZZI_H: |
| 14392 | case AArch64::RSHRNB_ZZI_H: |
| 14393 | case AArch64::SHRNB_ZZI_H: |
| 14394 | case AArch64::SQRSHRNB_ZZI_H: |
| 14395 | case AArch64::SQRSHRUNB_ZZI_H: |
| 14396 | case AArch64::SQSHRNB_ZZI_H: |
| 14397 | case AArch64::SQSHRUNB_ZZI_H: |
| 14398 | case AArch64::UQRSHRNB_ZZI_H: |
| 14399 | case AArch64::UQSHRNB_ZZI_H: { |
| 14400 | // op: Zd |
| 14401 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14402 | op &= UINT64_C(31); |
| 14403 | Value |= op; |
| 14404 | // op: Zn |
| 14405 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14406 | op &= UINT64_C(31); |
| 14407 | op <<= 5; |
| 14408 | Value |= op; |
| 14409 | // op: imm |
| 14410 | op = getVecShiftR16OpValue(MI, 2, Fixups, STI); |
| 14411 | op &= UINT64_C(15); |
| 14412 | op <<= 16; |
| 14413 | Value |= op; |
| 14414 | break; |
| 14415 | } |
| 14416 | case AArch64::ASR_ZZI_S: |
| 14417 | case AArch64::LSR_ZZI_S: |
| 14418 | case AArch64::RSHRNB_ZZI_S: |
| 14419 | case AArch64::SHRNB_ZZI_S: |
| 14420 | case AArch64::SQRSHRNB_ZZI_S: |
| 14421 | case AArch64::SQRSHRUNB_ZZI_S: |
| 14422 | case AArch64::SQSHRNB_ZZI_S: |
| 14423 | case AArch64::SQSHRUNB_ZZI_S: |
| 14424 | case AArch64::UQRSHRNB_ZZI_S: |
| 14425 | case AArch64::UQSHRNB_ZZI_S: { |
| 14426 | // op: Zd |
| 14427 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14428 | op &= UINT64_C(31); |
| 14429 | Value |= op; |
| 14430 | // op: Zn |
| 14431 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14432 | op &= UINT64_C(31); |
| 14433 | op <<= 5; |
| 14434 | Value |= op; |
| 14435 | // op: imm |
| 14436 | op = getVecShiftR32OpValue(MI, 2, Fixups, STI); |
| 14437 | op &= UINT64_C(31); |
| 14438 | op <<= 16; |
| 14439 | Value |= op; |
| 14440 | break; |
| 14441 | } |
| 14442 | case AArch64::ASR_ZZI_D: |
| 14443 | case AArch64::LSR_ZZI_D: { |
| 14444 | // op: Zd |
| 14445 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14446 | op &= UINT64_C(31); |
| 14447 | Value |= op; |
| 14448 | // op: Zn |
| 14449 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14450 | op &= UINT64_C(31); |
| 14451 | op <<= 5; |
| 14452 | Value |= op; |
| 14453 | // op: imm |
| 14454 | op = getVecShiftR64OpValue(MI, 2, Fixups, STI); |
| 14455 | Value |= (op & UINT64_C(32)) << 17; |
| 14456 | Value |= (op & UINT64_C(31)) << 16; |
| 14457 | break; |
| 14458 | } |
| 14459 | case AArch64::ASR_ZZI_B: |
| 14460 | case AArch64::LSR_ZZI_B: |
| 14461 | case AArch64::RSHRNB_ZZI_B: |
| 14462 | case AArch64::SHRNB_ZZI_B: |
| 14463 | case AArch64::SQRSHRNB_ZZI_B: |
| 14464 | case AArch64::SQRSHRUNB_ZZI_B: |
| 14465 | case AArch64::SQSHRNB_ZZI_B: |
| 14466 | case AArch64::SQSHRUNB_ZZI_B: |
| 14467 | case AArch64::UQRSHRNB_ZZI_B: |
| 14468 | case AArch64::UQSHRNB_ZZI_B: { |
| 14469 | // op: Zd |
| 14470 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14471 | op &= UINT64_C(31); |
| 14472 | Value |= op; |
| 14473 | // op: Zn |
| 14474 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14475 | op &= UINT64_C(31); |
| 14476 | op <<= 5; |
| 14477 | Value |= op; |
| 14478 | // op: imm |
| 14479 | op = getVecShiftR8OpValue(MI, 2, Fixups, STI); |
| 14480 | op &= UINT64_C(7); |
| 14481 | op <<= 16; |
| 14482 | Value |= op; |
| 14483 | break; |
| 14484 | } |
| 14485 | case AArch64::EXT_ZZI_B: { |
| 14486 | // op: Zd |
| 14487 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14488 | op &= UINT64_C(31); |
| 14489 | Value |= op; |
| 14490 | // op: Zn |
| 14491 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14492 | op &= UINT64_C(31); |
| 14493 | op <<= 5; |
| 14494 | Value |= op; |
| 14495 | // op: imm8 |
| 14496 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14497 | Value |= (op & UINT64_C(248)) << 13; |
| 14498 | Value |= (op & UINT64_C(7)) << 10; |
| 14499 | break; |
| 14500 | } |
| 14501 | case AArch64::SQXTNT_ZZ_B: |
| 14502 | case AArch64::SQXTNT_ZZ_H: |
| 14503 | case AArch64::SQXTNT_ZZ_S: |
| 14504 | case AArch64::SQXTUNT_ZZ_B: |
| 14505 | case AArch64::SQXTUNT_ZZ_H: |
| 14506 | case AArch64::SQXTUNT_ZZ_S: |
| 14507 | case AArch64::UQXTNT_ZZ_B: |
| 14508 | case AArch64::UQXTNT_ZZ_H: |
| 14509 | case AArch64::UQXTNT_ZZ_S: { |
| 14510 | // op: Zd |
| 14511 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14512 | op &= UINT64_C(31); |
| 14513 | Value |= op; |
| 14514 | // op: Zn |
| 14515 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14516 | op &= UINT64_C(31); |
| 14517 | op <<= 5; |
| 14518 | Value |= op; |
| 14519 | break; |
| 14520 | } |
| 14521 | case AArch64::HISTCNT_ZPzZZ_D: |
| 14522 | case AArch64::HISTCNT_ZPzZZ_S: { |
| 14523 | // op: Zd |
| 14524 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14525 | op &= UINT64_C(31); |
| 14526 | Value |= op; |
| 14527 | // op: Zn |
| 14528 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14529 | op &= UINT64_C(31); |
| 14530 | op <<= 5; |
| 14531 | Value |= op; |
| 14532 | // op: Pg |
| 14533 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14534 | op &= UINT64_C(7); |
| 14535 | op <<= 10; |
| 14536 | Value |= op; |
| 14537 | // op: Zm |
| 14538 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14539 | op &= UINT64_C(31); |
| 14540 | op <<= 16; |
| 14541 | Value |= op; |
| 14542 | break; |
| 14543 | } |
| 14544 | case AArch64::ADDHNT_ZZZ_B: |
| 14545 | case AArch64::ADDHNT_ZZZ_H: |
| 14546 | case AArch64::ADDHNT_ZZZ_S: |
| 14547 | case AArch64::EORBT_ZZZ_B: |
| 14548 | case AArch64::EORBT_ZZZ_D: |
| 14549 | case AArch64::EORBT_ZZZ_H: |
| 14550 | case AArch64::EORBT_ZZZ_S: |
| 14551 | case AArch64::EORTB_ZZZ_B: |
| 14552 | case AArch64::EORTB_ZZZ_D: |
| 14553 | case AArch64::EORTB_ZZZ_H: |
| 14554 | case AArch64::EORTB_ZZZ_S: |
| 14555 | case AArch64::RADDHNT_ZZZ_B: |
| 14556 | case AArch64::RADDHNT_ZZZ_H: |
| 14557 | case AArch64::RADDHNT_ZZZ_S: |
| 14558 | case AArch64::RSUBHNT_ZZZ_B: |
| 14559 | case AArch64::RSUBHNT_ZZZ_H: |
| 14560 | case AArch64::RSUBHNT_ZZZ_S: |
| 14561 | case AArch64::SUBHNT_ZZZ_B: |
| 14562 | case AArch64::SUBHNT_ZZZ_H: |
| 14563 | case AArch64::SUBHNT_ZZZ_S: { |
| 14564 | // op: Zd |
| 14565 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14566 | op &= UINT64_C(31); |
| 14567 | Value |= op; |
| 14568 | // op: Zn |
| 14569 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14570 | op &= UINT64_C(31); |
| 14571 | op <<= 5; |
| 14572 | Value |= op; |
| 14573 | // op: Zm |
| 14574 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14575 | op &= UINT64_C(31); |
| 14576 | op <<= 16; |
| 14577 | Value |= op; |
| 14578 | break; |
| 14579 | } |
| 14580 | case AArch64::SLI_ZZI_H: { |
| 14581 | // op: Zd |
| 14582 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14583 | op &= UINT64_C(31); |
| 14584 | Value |= op; |
| 14585 | // op: Zn |
| 14586 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14587 | op &= UINT64_C(31); |
| 14588 | op <<= 5; |
| 14589 | Value |= op; |
| 14590 | // op: imm |
| 14591 | op = getVecShiftL16OpValue(MI, 3, Fixups, STI); |
| 14592 | op &= UINT64_C(15); |
| 14593 | op <<= 16; |
| 14594 | Value |= op; |
| 14595 | break; |
| 14596 | } |
| 14597 | case AArch64::SLI_ZZI_S: { |
| 14598 | // op: Zd |
| 14599 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14600 | op &= UINT64_C(31); |
| 14601 | Value |= op; |
| 14602 | // op: Zn |
| 14603 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14604 | op &= UINT64_C(31); |
| 14605 | op <<= 5; |
| 14606 | Value |= op; |
| 14607 | // op: imm |
| 14608 | op = getVecShiftL32OpValue(MI, 3, Fixups, STI); |
| 14609 | op &= UINT64_C(31); |
| 14610 | op <<= 16; |
| 14611 | Value |= op; |
| 14612 | break; |
| 14613 | } |
| 14614 | case AArch64::SLI_ZZI_D: { |
| 14615 | // op: Zd |
| 14616 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14617 | op &= UINT64_C(31); |
| 14618 | Value |= op; |
| 14619 | // op: Zn |
| 14620 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14621 | op &= UINT64_C(31); |
| 14622 | op <<= 5; |
| 14623 | Value |= op; |
| 14624 | // op: imm |
| 14625 | op = getVecShiftL64OpValue(MI, 3, Fixups, STI); |
| 14626 | Value |= (op & UINT64_C(32)) << 17; |
| 14627 | Value |= (op & UINT64_C(31)) << 16; |
| 14628 | break; |
| 14629 | } |
| 14630 | case AArch64::SLI_ZZI_B: { |
| 14631 | // op: Zd |
| 14632 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14633 | op &= UINT64_C(31); |
| 14634 | Value |= op; |
| 14635 | // op: Zn |
| 14636 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14637 | op &= UINT64_C(31); |
| 14638 | op <<= 5; |
| 14639 | Value |= op; |
| 14640 | // op: imm |
| 14641 | op = getVecShiftL8OpValue(MI, 3, Fixups, STI); |
| 14642 | op &= UINT64_C(7); |
| 14643 | op <<= 16; |
| 14644 | Value |= op; |
| 14645 | break; |
| 14646 | } |
| 14647 | case AArch64::RSHRNT_ZZI_H: |
| 14648 | case AArch64::SHRNT_ZZI_H: |
| 14649 | case AArch64::SQRSHRNT_ZZI_H: |
| 14650 | case AArch64::SQRSHRUNT_ZZI_H: |
| 14651 | case AArch64::SQSHRNT_ZZI_H: |
| 14652 | case AArch64::SQSHRUNT_ZZI_H: |
| 14653 | case AArch64::SRI_ZZI_H: |
| 14654 | case AArch64::UQRSHRNT_ZZI_H: |
| 14655 | case AArch64::UQSHRNT_ZZI_H: { |
| 14656 | // op: Zd |
| 14657 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14658 | op &= UINT64_C(31); |
| 14659 | Value |= op; |
| 14660 | // op: Zn |
| 14661 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14662 | op &= UINT64_C(31); |
| 14663 | op <<= 5; |
| 14664 | Value |= op; |
| 14665 | // op: imm |
| 14666 | op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| 14667 | op &= UINT64_C(15); |
| 14668 | op <<= 16; |
| 14669 | Value |= op; |
| 14670 | break; |
| 14671 | } |
| 14672 | case AArch64::RSHRNT_ZZI_S: |
| 14673 | case AArch64::SHRNT_ZZI_S: |
| 14674 | case AArch64::SQRSHRNT_ZZI_S: |
| 14675 | case AArch64::SQRSHRUNT_ZZI_S: |
| 14676 | case AArch64::SQSHRNT_ZZI_S: |
| 14677 | case AArch64::SQSHRUNT_ZZI_S: |
| 14678 | case AArch64::SRI_ZZI_S: |
| 14679 | case AArch64::UQRSHRNT_ZZI_S: |
| 14680 | case AArch64::UQSHRNT_ZZI_S: { |
| 14681 | // op: Zd |
| 14682 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14683 | op &= UINT64_C(31); |
| 14684 | Value |= op; |
| 14685 | // op: Zn |
| 14686 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14687 | op &= UINT64_C(31); |
| 14688 | op <<= 5; |
| 14689 | Value |= op; |
| 14690 | // op: imm |
| 14691 | op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| 14692 | op &= UINT64_C(31); |
| 14693 | op <<= 16; |
| 14694 | Value |= op; |
| 14695 | break; |
| 14696 | } |
| 14697 | case AArch64::SRI_ZZI_D: { |
| 14698 | // op: Zd |
| 14699 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14700 | op &= UINT64_C(31); |
| 14701 | Value |= op; |
| 14702 | // op: Zn |
| 14703 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14704 | op &= UINT64_C(31); |
| 14705 | op <<= 5; |
| 14706 | Value |= op; |
| 14707 | // op: imm |
| 14708 | op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| 14709 | Value |= (op & UINT64_C(32)) << 17; |
| 14710 | Value |= (op & UINT64_C(31)) << 16; |
| 14711 | break; |
| 14712 | } |
| 14713 | case AArch64::RSHRNT_ZZI_B: |
| 14714 | case AArch64::SHRNT_ZZI_B: |
| 14715 | case AArch64::SQRSHRNT_ZZI_B: |
| 14716 | case AArch64::SQRSHRUNT_ZZI_B: |
| 14717 | case AArch64::SQSHRNT_ZZI_B: |
| 14718 | case AArch64::SQSHRUNT_ZZI_B: |
| 14719 | case AArch64::SRI_ZZI_B: |
| 14720 | case AArch64::UQRSHRNT_ZZI_B: |
| 14721 | case AArch64::UQSHRNT_ZZI_B: { |
| 14722 | // op: Zd |
| 14723 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14724 | op &= UINT64_C(31); |
| 14725 | Value |= op; |
| 14726 | // op: Zn |
| 14727 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14728 | op &= UINT64_C(31); |
| 14729 | op <<= 5; |
| 14730 | Value |= op; |
| 14731 | // op: imm |
| 14732 | op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| 14733 | op &= UINT64_C(7); |
| 14734 | op <<= 16; |
| 14735 | Value |= op; |
| 14736 | break; |
| 14737 | } |
| 14738 | case AArch64::FCVTLT_ZPmZ_HtoS: |
| 14739 | case AArch64::FCVTLT_ZPmZ_StoD: |
| 14740 | case AArch64::FCVTNT_ZPmZ_DtoS: |
| 14741 | case AArch64::FCVTNT_ZPmZ_StoH: |
| 14742 | case AArch64::FCVTXNT_ZPmZ_DtoS: { |
| 14743 | // op: Zd |
| 14744 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14745 | op &= UINT64_C(31); |
| 14746 | Value |= op; |
| 14747 | // op: Zn |
| 14748 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14749 | op &= UINT64_C(31); |
| 14750 | op <<= 5; |
| 14751 | Value |= op; |
| 14752 | // op: Pg |
| 14753 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14754 | op &= UINT64_C(7); |
| 14755 | op <<= 10; |
| 14756 | Value |= op; |
| 14757 | break; |
| 14758 | } |
| 14759 | case AArch64::DUP_ZI_B: |
| 14760 | case AArch64::DUP_ZI_D: |
| 14761 | case AArch64::DUP_ZI_H: |
| 14762 | case AArch64::DUP_ZI_S: { |
| 14763 | // op: Zd |
| 14764 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14765 | op &= UINT64_C(31); |
| 14766 | Value |= op; |
| 14767 | // op: imm |
| 14768 | op = getImm8OptLsl(MI, 1, Fixups, STI); |
| 14769 | op &= UINT64_C(511); |
| 14770 | op <<= 5; |
| 14771 | Value |= op; |
| 14772 | break; |
| 14773 | } |
| 14774 | case AArch64::INDEX_II_B: |
| 14775 | case AArch64::INDEX_II_D: |
| 14776 | case AArch64::INDEX_II_H: |
| 14777 | case AArch64::INDEX_II_S: { |
| 14778 | // op: Zd |
| 14779 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14780 | op &= UINT64_C(31); |
| 14781 | Value |= op; |
| 14782 | // op: imm5 |
| 14783 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14784 | op &= UINT64_C(31); |
| 14785 | op <<= 5; |
| 14786 | Value |= op; |
| 14787 | // op: imm5b |
| 14788 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14789 | op &= UINT64_C(31); |
| 14790 | op <<= 16; |
| 14791 | Value |= op; |
| 14792 | break; |
| 14793 | } |
| 14794 | case AArch64::FDUP_ZI_D: |
| 14795 | case AArch64::FDUP_ZI_H: |
| 14796 | case AArch64::FDUP_ZI_S: { |
| 14797 | // op: Zd |
| 14798 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14799 | op &= UINT64_C(31); |
| 14800 | Value |= op; |
| 14801 | // op: imm8 |
| 14802 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14803 | op &= UINT64_C(255); |
| 14804 | op <<= 5; |
| 14805 | Value |= op; |
| 14806 | break; |
| 14807 | } |
| 14808 | case AArch64::DUPM_ZI: { |
| 14809 | // op: Zd |
| 14810 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14811 | op &= UINT64_C(31); |
| 14812 | Value |= op; |
| 14813 | // op: imms |
| 14814 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14815 | op &= UINT64_C(8191); |
| 14816 | op <<= 5; |
| 14817 | Value |= op; |
| 14818 | break; |
| 14819 | } |
| 14820 | case AArch64::FCMLA_ZPmZZ_D: |
| 14821 | case AArch64::FCMLA_ZPmZZ_H: |
| 14822 | case AArch64::FCMLA_ZPmZZ_S: { |
| 14823 | // op: Zda |
| 14824 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14825 | op &= UINT64_C(31); |
| 14826 | Value |= op; |
| 14827 | // op: Pg |
| 14828 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 14829 | op &= UINT64_C(7); |
| 14830 | op <<= 10; |
| 14831 | Value |= op; |
| 14832 | // op: Zn |
| 14833 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14834 | op &= UINT64_C(31); |
| 14835 | op <<= 5; |
| 14836 | Value |= op; |
| 14837 | // op: Zm |
| 14838 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 14839 | op &= UINT64_C(31); |
| 14840 | op <<= 16; |
| 14841 | Value |= op; |
| 14842 | // op: imm |
| 14843 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 14844 | op &= UINT64_C(3); |
| 14845 | op <<= 13; |
| 14846 | Value |= op; |
| 14847 | break; |
| 14848 | } |
| 14849 | case AArch64::SMLALB_ZZZI_D: |
| 14850 | case AArch64::SMLALT_ZZZI_D: |
| 14851 | case AArch64::SMLSLB_ZZZI_D: |
| 14852 | case AArch64::SMLSLT_ZZZI_D: |
| 14853 | case AArch64::SQDMLALB_ZZZI_D: |
| 14854 | case AArch64::SQDMLALT_ZZZI_D: |
| 14855 | case AArch64::SQDMLSLB_ZZZI_D: |
| 14856 | case AArch64::SQDMLSLT_ZZZI_D: |
| 14857 | case AArch64::UMLALB_ZZZI_D: |
| 14858 | case AArch64::UMLALT_ZZZI_D: |
| 14859 | case AArch64::UMLSLB_ZZZI_D: |
| 14860 | case AArch64::UMLSLT_ZZZI_D: { |
| 14861 | // op: Zda |
| 14862 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14863 | op &= UINT64_C(31); |
| 14864 | Value |= op; |
| 14865 | // op: Zn |
| 14866 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14867 | op &= UINT64_C(31); |
| 14868 | op <<= 5; |
| 14869 | Value |= op; |
| 14870 | // op: Zm |
| 14871 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14872 | op &= UINT64_C(15); |
| 14873 | op <<= 16; |
| 14874 | Value |= op; |
| 14875 | // op: iop |
| 14876 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 14877 | Value |= (op & UINT64_C(2)) << 19; |
| 14878 | Value |= (op & UINT64_C(1)) << 11; |
| 14879 | break; |
| 14880 | } |
| 14881 | case AArch64::FMLA_ZZZI_D: |
| 14882 | case AArch64::FMLS_ZZZI_D: |
| 14883 | case AArch64::MLA_ZZZI_D: |
| 14884 | case AArch64::MLS_ZZZI_D: |
| 14885 | case AArch64::SQRDMLAH_ZZZI_D: |
| 14886 | case AArch64::SQRDMLSH_ZZZI_D: { |
| 14887 | // op: Zda |
| 14888 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 14889 | op &= UINT64_C(31); |
| 14890 | Value |= op; |
| 14891 | // op: Zn |
| 14892 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 14893 | op &= UINT64_C(31); |
| 14894 | op <<= 5; |
| 14895 | Value |= op; |
| 14896 | // op: Zm |
| 14897 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 14898 | op &= UINT64_C(15); |
| 14899 | op <<= 16; |
| 14900 | Value |= op; |
| 14901 | // op: iop |
| 14902 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 14903 | op &= UINT64_C(1); |
| 14904 | op <<= 20; |
| 14905 | Value |= op; |
| 14906 | break; |
| 14907 | } |
| 14908 | case AArch64::ADCLB_ZZZ_D: |
| 14909 | case AArch64::ADCLB_ZZZ_S: |
| 14910 | case AArch64::ADCLT_ZZZ_D: |
| 14911 | case AArch64::ADCLT_ZZZ_S: |
| 14912 | case AArch64::BFDOT_ZZZ: |
| 14913 | case AArch64::FMLALB_ZZZ_SHH: |
| 14914 | case AArch64::FMLALT_ZZZ_SHH: |
| 14915 | case AArch64::FMLSLB_ZZZ_SHH: |
| 14916 | case AArch64::FMLSLT_ZZZ_SHH: |
| 14917 | case AArch64::FMMLA_ZZZ_D: |
| 14918 | case AArch64::FMMLA_ZZZ_S: |
| 14919 | case AArch64::SABALB_ZZZ_D: |
| 14920 | case AArch64::SABALB_ZZZ_H: |
| 14921 | case AArch64::SABALB_ZZZ_S: |
| 14922 | case AArch64::SABALT_ZZZ_D: |
| 14923 | case AArch64::SABALT_ZZZ_H: |
| 14924 | case AArch64::SABALT_ZZZ_S: |
| 14925 | case AArch64::SABA_ZZZ_B: |
| 14926 | case AArch64::SABA_ZZZ_D: |
| 14927 | case AArch64::SABA_ZZZ_H: |
| 14928 | case AArch64::SABA_ZZZ_S: |
| 14929 | case AArch64::SBCLB_ZZZ_D: |
| 14930 | case AArch64::SBCLB_ZZZ_S: |
| 14931 | case AArch64::SBCLT_ZZZ_D: |
| 14932 | case AArch64::SBCLT_ZZZ_S: |
| 14933 | case AArch64::SDOT_ZZZ_D: |
| 14934 | case AArch64::SDOT_ZZZ_S: |
| 14935 | case AArch64::SMLALB_ZZZ_D: |
| 14936 | case AArch64::SMLALB_ZZZ_H: |
| 14937 | case AArch64::SMLALB_ZZZ_S: |
| 14938 | case AArch64::SMLALT_ZZZ_D: |
| 14939 | case AArch64::SMLALT_ZZZ_H: |
| 14940 | case AArch64::SMLALT_ZZZ_S: |
| 14941 | case AArch64::SMLSLB_ZZZ_D: |
| 14942 | case AArch64::SMLSLB_ZZZ_H: |
| 14943 | case AArch64::SMLSLB_ZZZ_S: |
| 14944 | case AArch64::SMLSLT_ZZZ_D: |
| 14945 | case AArch64::SMLSLT_ZZZ_H: |
| 14946 | case AArch64::SMLSLT_ZZZ_S: |
| 14947 | case AArch64::SMMLA_ZZZ: |
| 14948 | case AArch64::SQDMLALBT_ZZZ_D: |
| 14949 | case AArch64::SQDMLALBT_ZZZ_H: |
| 14950 | case AArch64::SQDMLALBT_ZZZ_S: |
| 14951 | case AArch64::SQDMLALB_ZZZ_D: |
| 14952 | case AArch64::SQDMLALB_ZZZ_H: |
| 14953 | case AArch64::SQDMLALB_ZZZ_S: |
| 14954 | case AArch64::SQDMLALT_ZZZ_D: |
| 14955 | case AArch64::SQDMLALT_ZZZ_H: |
| 14956 | case AArch64::SQDMLALT_ZZZ_S: |
| 14957 | case AArch64::SQDMLSLBT_ZZZ_D: |
| 14958 | case AArch64::SQDMLSLBT_ZZZ_H: |
| 14959 | case AArch64::SQDMLSLBT_ZZZ_S: |
| 14960 | case AArch64::SQDMLSLB_ZZZ_D: |
| 14961 | case AArch64::SQDMLSLB_ZZZ_H: |
| 14962 | case AArch64::SQDMLSLB_ZZZ_S: |
| 14963 | case AArch64::SQDMLSLT_ZZZ_D: |
| 14964 | case AArch64::SQDMLSLT_ZZZ_H: |
| 14965 | case AArch64::SQDMLSLT_ZZZ_S: |
| 14966 | case AArch64::SQRDMLAH_ZZZ_B: |
| 14967 | case AArch64::SQRDMLAH_ZZZ_D: |
| 14968 | case AArch64::SQRDMLAH_ZZZ_H: |
| 14969 | case AArch64::SQRDMLAH_ZZZ_S: |
| 14970 | case AArch64::SQRDMLSH_ZZZ_B: |
| 14971 | case AArch64::SQRDMLSH_ZZZ_D: |
| 14972 | case AArch64::SQRDMLSH_ZZZ_H: |
| 14973 | case AArch64::SQRDMLSH_ZZZ_S: |
| 14974 | case AArch64::UABALB_ZZZ_D: |
| 14975 | case AArch64::UABALB_ZZZ_H: |
| 14976 | case AArch64::UABALB_ZZZ_S: |
| 14977 | case AArch64::UABALT_ZZZ_D: |
| 14978 | case AArch64::UABALT_ZZZ_H: |
| 14979 | case AArch64::UABALT_ZZZ_S: |
| 14980 | case AArch64::UABA_ZZZ_B: |
| 14981 | case AArch64::UABA_ZZZ_D: |
| 14982 | case AArch64::UABA_ZZZ_H: |
| 14983 | case AArch64::UABA_ZZZ_S: |
| 14984 | case AArch64::UDOT_ZZZ_D: |
| 14985 | case AArch64::UDOT_ZZZ_S: |
| 14986 | case AArch64::UMLALB_ZZZ_D: |
| 14987 | case AArch64::UMLALB_ZZZ_H: |
| 14988 | case AArch64::UMLALB_ZZZ_S: |
| 14989 | case AArch64::UMLALT_ZZZ_D: |
| 14990 | case AArch64::UMLALT_ZZZ_H: |
| 14991 | case AArch64::UMLALT_ZZZ_S: |
| 14992 | case AArch64::UMLSLB_ZZZ_D: |
| 14993 | case AArch64::UMLSLB_ZZZ_H: |
| 14994 | case AArch64::UMLSLB_ZZZ_S: |
| 14995 | case AArch64::UMLSLT_ZZZ_D: |
| 14996 | case AArch64::UMLSLT_ZZZ_H: |
| 14997 | case AArch64::UMLSLT_ZZZ_S: |
| 14998 | case AArch64::UMMLA_ZZZ: |
| 14999 | case AArch64::USDOT_ZZZ: |
| 15000 | case AArch64::USMMLA_ZZZ: { |
| 15001 | // op: Zda |
| 15002 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15003 | op &= UINT64_C(31); |
| 15004 | Value |= op; |
| 15005 | // op: Zn |
| 15006 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15007 | op &= UINT64_C(31); |
| 15008 | op <<= 5; |
| 15009 | Value |= op; |
| 15010 | // op: Zm |
| 15011 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15012 | op &= UINT64_C(31); |
| 15013 | op <<= 16; |
| 15014 | Value |= op; |
| 15015 | break; |
| 15016 | } |
| 15017 | case AArch64::CDOT_ZZZ_D: |
| 15018 | case AArch64::CDOT_ZZZ_S: |
| 15019 | case AArch64::CMLA_ZZZ_B: |
| 15020 | case AArch64::CMLA_ZZZ_D: |
| 15021 | case AArch64::CMLA_ZZZ_H: |
| 15022 | case AArch64::CMLA_ZZZ_S: |
| 15023 | case AArch64::SQRDCMLAH_ZZZ_B: |
| 15024 | case AArch64::SQRDCMLAH_ZZZ_D: |
| 15025 | case AArch64::SQRDCMLAH_ZZZ_H: |
| 15026 | case AArch64::SQRDCMLAH_ZZZ_S: { |
| 15027 | // op: Zda |
| 15028 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15029 | op &= UINT64_C(31); |
| 15030 | Value |= op; |
| 15031 | // op: Zn |
| 15032 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15033 | op &= UINT64_C(31); |
| 15034 | op <<= 5; |
| 15035 | Value |= op; |
| 15036 | // op: Zm |
| 15037 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15038 | op &= UINT64_C(31); |
| 15039 | op <<= 16; |
| 15040 | Value |= op; |
| 15041 | // op: rot |
| 15042 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15043 | op &= UINT64_C(3); |
| 15044 | op <<= 10; |
| 15045 | Value |= op; |
| 15046 | break; |
| 15047 | } |
| 15048 | case AArch64::SUDOT_ZZZI: |
| 15049 | case AArch64::USDOT_ZZZI: { |
| 15050 | // op: Zda |
| 15051 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15052 | op &= UINT64_C(31); |
| 15053 | Value |= op; |
| 15054 | // op: Zn |
| 15055 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15056 | op &= UINT64_C(31); |
| 15057 | op <<= 5; |
| 15058 | Value |= op; |
| 15059 | // op: Zm |
| 15060 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15061 | op &= UINT64_C(7); |
| 15062 | op <<= 16; |
| 15063 | Value |= op; |
| 15064 | // op: idx |
| 15065 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15066 | op &= UINT64_C(3); |
| 15067 | op <<= 19; |
| 15068 | Value |= op; |
| 15069 | break; |
| 15070 | } |
| 15071 | case AArch64::FMLA_ZZZI_H: |
| 15072 | case AArch64::FMLS_ZZZI_H: |
| 15073 | case AArch64::MLA_ZZZI_H: |
| 15074 | case AArch64::MLS_ZZZI_H: |
| 15075 | case AArch64::SQRDMLAH_ZZZI_H: |
| 15076 | case AArch64::SQRDMLSH_ZZZI_H: { |
| 15077 | // op: Zda |
| 15078 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15079 | op &= UINT64_C(31); |
| 15080 | Value |= op; |
| 15081 | // op: Zn |
| 15082 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15083 | op &= UINT64_C(31); |
| 15084 | op <<= 5; |
| 15085 | Value |= op; |
| 15086 | // op: Zm |
| 15087 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15088 | op &= UINT64_C(7); |
| 15089 | op <<= 16; |
| 15090 | Value |= op; |
| 15091 | // op: iop |
| 15092 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15093 | Value |= (op & UINT64_C(4)) << 20; |
| 15094 | Value |= (op & UINT64_C(3)) << 19; |
| 15095 | break; |
| 15096 | } |
| 15097 | case AArch64::FMLALB_ZZZI_SHH: |
| 15098 | case AArch64::FMLALT_ZZZI_SHH: |
| 15099 | case AArch64::FMLSLB_ZZZI_SHH: |
| 15100 | case AArch64::FMLSLT_ZZZI_SHH: |
| 15101 | case AArch64::SMLALB_ZZZI_S: |
| 15102 | case AArch64::SMLALT_ZZZI_S: |
| 15103 | case AArch64::SMLSLB_ZZZI_S: |
| 15104 | case AArch64::SMLSLT_ZZZI_S: |
| 15105 | case AArch64::SQDMLALB_ZZZI_S: |
| 15106 | case AArch64::SQDMLALT_ZZZI_S: |
| 15107 | case AArch64::SQDMLSLB_ZZZI_S: |
| 15108 | case AArch64::SQDMLSLT_ZZZI_S: |
| 15109 | case AArch64::UMLALB_ZZZI_S: |
| 15110 | case AArch64::UMLALT_ZZZI_S: |
| 15111 | case AArch64::UMLSLB_ZZZI_S: |
| 15112 | case AArch64::UMLSLT_ZZZI_S: { |
| 15113 | // op: Zda |
| 15114 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15115 | op &= UINT64_C(31); |
| 15116 | Value |= op; |
| 15117 | // op: Zn |
| 15118 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15119 | op &= UINT64_C(31); |
| 15120 | op <<= 5; |
| 15121 | Value |= op; |
| 15122 | // op: Zm |
| 15123 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15124 | op &= UINT64_C(7); |
| 15125 | op <<= 16; |
| 15126 | Value |= op; |
| 15127 | // op: iop |
| 15128 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15129 | Value |= (op & UINT64_C(6)) << 18; |
| 15130 | Value |= (op & UINT64_C(1)) << 11; |
| 15131 | break; |
| 15132 | } |
| 15133 | case AArch64::FMLA_ZZZI_S: |
| 15134 | case AArch64::FMLS_ZZZI_S: |
| 15135 | case AArch64::MLA_ZZZI_S: |
| 15136 | case AArch64::MLS_ZZZI_S: |
| 15137 | case AArch64::SQRDMLAH_ZZZI_S: |
| 15138 | case AArch64::SQRDMLSH_ZZZI_S: { |
| 15139 | // op: Zda |
| 15140 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15141 | op &= UINT64_C(31); |
| 15142 | Value |= op; |
| 15143 | // op: Zn |
| 15144 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15145 | op &= UINT64_C(31); |
| 15146 | op <<= 5; |
| 15147 | Value |= op; |
| 15148 | // op: Zm |
| 15149 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15150 | op &= UINT64_C(7); |
| 15151 | op <<= 16; |
| 15152 | Value |= op; |
| 15153 | // op: iop |
| 15154 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15155 | op &= UINT64_C(3); |
| 15156 | op <<= 19; |
| 15157 | Value |= op; |
| 15158 | break; |
| 15159 | } |
| 15160 | case AArch64::FCMLA_ZZZI_S: { |
| 15161 | // op: Zda |
| 15162 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15163 | op &= UINT64_C(31); |
| 15164 | Value |= op; |
| 15165 | // op: Zn |
| 15166 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15167 | op &= UINT64_C(31); |
| 15168 | op <<= 5; |
| 15169 | Value |= op; |
| 15170 | // op: imm |
| 15171 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 15172 | op &= UINT64_C(3); |
| 15173 | op <<= 10; |
| 15174 | Value |= op; |
| 15175 | // op: Zm |
| 15176 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15177 | op &= UINT64_C(15); |
| 15178 | op <<= 16; |
| 15179 | Value |= op; |
| 15180 | // op: iop |
| 15181 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15182 | op &= UINT64_C(1); |
| 15183 | op <<= 20; |
| 15184 | Value |= op; |
| 15185 | break; |
| 15186 | } |
| 15187 | case AArch64::FCMLA_ZZZI_H: { |
| 15188 | // op: Zda |
| 15189 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15190 | op &= UINT64_C(31); |
| 15191 | Value |= op; |
| 15192 | // op: Zn |
| 15193 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15194 | op &= UINT64_C(31); |
| 15195 | op <<= 5; |
| 15196 | Value |= op; |
| 15197 | // op: imm |
| 15198 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 15199 | op &= UINT64_C(3); |
| 15200 | op <<= 10; |
| 15201 | Value |= op; |
| 15202 | // op: Zm |
| 15203 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15204 | op &= UINT64_C(7); |
| 15205 | op <<= 16; |
| 15206 | Value |= op; |
| 15207 | // op: iop |
| 15208 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15209 | op &= UINT64_C(3); |
| 15210 | op <<= 19; |
| 15211 | Value |= op; |
| 15212 | break; |
| 15213 | } |
| 15214 | case AArch64::SRSRA_ZZI_H: |
| 15215 | case AArch64::SSRA_ZZI_H: |
| 15216 | case AArch64::URSRA_ZZI_H: |
| 15217 | case AArch64::USRA_ZZI_H: { |
| 15218 | // op: Zda |
| 15219 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15220 | op &= UINT64_C(31); |
| 15221 | Value |= op; |
| 15222 | // op: Zn |
| 15223 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15224 | op &= UINT64_C(31); |
| 15225 | op <<= 5; |
| 15226 | Value |= op; |
| 15227 | // op: imm |
| 15228 | op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| 15229 | op &= UINT64_C(15); |
| 15230 | op <<= 16; |
| 15231 | Value |= op; |
| 15232 | break; |
| 15233 | } |
| 15234 | case AArch64::SRSRA_ZZI_S: |
| 15235 | case AArch64::SSRA_ZZI_S: |
| 15236 | case AArch64::URSRA_ZZI_S: |
| 15237 | case AArch64::USRA_ZZI_S: { |
| 15238 | // op: Zda |
| 15239 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15240 | op &= UINT64_C(31); |
| 15241 | Value |= op; |
| 15242 | // op: Zn |
| 15243 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15244 | op &= UINT64_C(31); |
| 15245 | op <<= 5; |
| 15246 | Value |= op; |
| 15247 | // op: imm |
| 15248 | op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| 15249 | op &= UINT64_C(31); |
| 15250 | op <<= 16; |
| 15251 | Value |= op; |
| 15252 | break; |
| 15253 | } |
| 15254 | case AArch64::SRSRA_ZZI_D: |
| 15255 | case AArch64::SSRA_ZZI_D: |
| 15256 | case AArch64::URSRA_ZZI_D: |
| 15257 | case AArch64::USRA_ZZI_D: { |
| 15258 | // op: Zda |
| 15259 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15260 | op &= UINT64_C(31); |
| 15261 | Value |= op; |
| 15262 | // op: Zn |
| 15263 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15264 | op &= UINT64_C(31); |
| 15265 | op <<= 5; |
| 15266 | Value |= op; |
| 15267 | // op: imm |
| 15268 | op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| 15269 | Value |= (op & UINT64_C(32)) << 17; |
| 15270 | Value |= (op & UINT64_C(31)) << 16; |
| 15271 | break; |
| 15272 | } |
| 15273 | case AArch64::SRSRA_ZZI_B: |
| 15274 | case AArch64::SSRA_ZZI_B: |
| 15275 | case AArch64::URSRA_ZZI_B: |
| 15276 | case AArch64::USRA_ZZI_B: { |
| 15277 | // op: Zda |
| 15278 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15279 | op &= UINT64_C(31); |
| 15280 | Value |= op; |
| 15281 | // op: Zn |
| 15282 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15283 | op &= UINT64_C(31); |
| 15284 | op <<= 5; |
| 15285 | Value |= op; |
| 15286 | // op: imm |
| 15287 | op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| 15288 | op &= UINT64_C(7); |
| 15289 | op <<= 16; |
| 15290 | Value |= op; |
| 15291 | break; |
| 15292 | } |
| 15293 | case AArch64::BFMMLA_B_ZZI: |
| 15294 | case AArch64::BFMMLA_T_ZZI: { |
| 15295 | // op: Zda |
| 15296 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15297 | op &= UINT64_C(31); |
| 15298 | Value |= op; |
| 15299 | // op: Zn |
| 15300 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15301 | op &= UINT64_C(31); |
| 15302 | op <<= 5; |
| 15303 | Value |= op; |
| 15304 | // op: iop |
| 15305 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15306 | Value |= (op & UINT64_C(6)) << 18; |
| 15307 | Value |= (op & UINT64_C(1)) << 11; |
| 15308 | // op: Zm |
| 15309 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15310 | op &= UINT64_C(7); |
| 15311 | op <<= 16; |
| 15312 | Value |= op; |
| 15313 | break; |
| 15314 | } |
| 15315 | case AArch64::SDOT_ZZZI_D: |
| 15316 | case AArch64::UDOT_ZZZI_D: { |
| 15317 | // op: Zda |
| 15318 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15319 | op &= UINT64_C(31); |
| 15320 | Value |= op; |
| 15321 | // op: Zn |
| 15322 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15323 | op &= UINT64_C(31); |
| 15324 | op <<= 5; |
| 15325 | Value |= op; |
| 15326 | // op: iop |
| 15327 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15328 | op &= UINT64_C(1); |
| 15329 | op <<= 20; |
| 15330 | Value |= op; |
| 15331 | // op: Zm |
| 15332 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15333 | op &= UINT64_C(15); |
| 15334 | op <<= 16; |
| 15335 | Value |= op; |
| 15336 | break; |
| 15337 | } |
| 15338 | case AArch64::BFDOT_ZZI: |
| 15339 | case AArch64::SDOT_ZZZI_S: |
| 15340 | case AArch64::UDOT_ZZZI_S: { |
| 15341 | // op: Zda |
| 15342 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15343 | op &= UINT64_C(31); |
| 15344 | Value |= op; |
| 15345 | // op: Zn |
| 15346 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15347 | op &= UINT64_C(31); |
| 15348 | op <<= 5; |
| 15349 | Value |= op; |
| 15350 | // op: iop |
| 15351 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15352 | op &= UINT64_C(3); |
| 15353 | op <<= 19; |
| 15354 | Value |= op; |
| 15355 | // op: Zm |
| 15356 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15357 | op &= UINT64_C(7); |
| 15358 | op <<= 16; |
| 15359 | Value |= op; |
| 15360 | break; |
| 15361 | } |
| 15362 | case AArch64::CDOT_ZZZI_D: |
| 15363 | case AArch64::CMLA_ZZZI_S: |
| 15364 | case AArch64::SQRDCMLAH_ZZZI_S: { |
| 15365 | // op: Zda |
| 15366 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15367 | op &= UINT64_C(31); |
| 15368 | Value |= op; |
| 15369 | // op: Zn |
| 15370 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15371 | op &= UINT64_C(31); |
| 15372 | op <<= 5; |
| 15373 | Value |= op; |
| 15374 | // op: rot |
| 15375 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 15376 | op &= UINT64_C(3); |
| 15377 | op <<= 10; |
| 15378 | Value |= op; |
| 15379 | // op: iop |
| 15380 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15381 | op &= UINT64_C(1); |
| 15382 | op <<= 20; |
| 15383 | Value |= op; |
| 15384 | // op: Zm |
| 15385 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15386 | op &= UINT64_C(15); |
| 15387 | op <<= 16; |
| 15388 | Value |= op; |
| 15389 | break; |
| 15390 | } |
| 15391 | case AArch64::CDOT_ZZZI_S: |
| 15392 | case AArch64::CMLA_ZZZI_H: |
| 15393 | case AArch64::SQRDCMLAH_ZZZI_H: { |
| 15394 | // op: Zda |
| 15395 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15396 | op &= UINT64_C(31); |
| 15397 | Value |= op; |
| 15398 | // op: Zn |
| 15399 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15400 | op &= UINT64_C(31); |
| 15401 | op <<= 5; |
| 15402 | Value |= op; |
| 15403 | // op: rot |
| 15404 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| 15405 | op &= UINT64_C(3); |
| 15406 | op <<= 10; |
| 15407 | Value |= op; |
| 15408 | // op: iop |
| 15409 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15410 | op &= UINT64_C(3); |
| 15411 | op <<= 19; |
| 15412 | Value |= op; |
| 15413 | // op: Zm |
| 15414 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15415 | op &= UINT64_C(7); |
| 15416 | op <<= 16; |
| 15417 | Value |= op; |
| 15418 | break; |
| 15419 | } |
| 15420 | case AArch64::AESIMC_ZZ_B: |
| 15421 | case AArch64::AESMC_ZZ_B: { |
| 15422 | // op: Zdn |
| 15423 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15424 | op &= UINT64_C(31); |
| 15425 | Value |= op; |
| 15426 | break; |
| 15427 | } |
| 15428 | case AArch64::BCAX_ZZZZ: |
| 15429 | case AArch64::BSL1N_ZZZZ: |
| 15430 | case AArch64::BSL2N_ZZZZ: |
| 15431 | case AArch64::BSL_ZZZZ: |
| 15432 | case AArch64::EOR3_ZZZZ: |
| 15433 | case AArch64::NBSL_ZZZZ: { |
| 15434 | // op: Zdn |
| 15435 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15436 | op &= UINT64_C(31); |
| 15437 | Value |= op; |
| 15438 | // op: Zk |
| 15439 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15440 | op &= UINT64_C(31); |
| 15441 | op <<= 5; |
| 15442 | Value |= op; |
| 15443 | // op: Zm |
| 15444 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15445 | op &= UINT64_C(31); |
| 15446 | op <<= 16; |
| 15447 | Value |= op; |
| 15448 | break; |
| 15449 | } |
| 15450 | case AArch64::AESD_ZZZ_B: |
| 15451 | case AArch64::AESE_ZZZ_B: |
| 15452 | case AArch64::SM4E_ZZZ_S: { |
| 15453 | // op: Zdn |
| 15454 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15455 | op &= UINT64_C(31); |
| 15456 | Value |= op; |
| 15457 | // op: Zm |
| 15458 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15459 | op &= UINT64_C(31); |
| 15460 | op <<= 5; |
| 15461 | Value |= op; |
| 15462 | break; |
| 15463 | } |
| 15464 | case AArch64::XAR_ZZZI_H: { |
| 15465 | // op: Zdn |
| 15466 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15467 | op &= UINT64_C(31); |
| 15468 | Value |= op; |
| 15469 | // op: Zm |
| 15470 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15471 | op &= UINT64_C(31); |
| 15472 | op <<= 5; |
| 15473 | Value |= op; |
| 15474 | // op: imm |
| 15475 | op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| 15476 | op &= UINT64_C(15); |
| 15477 | op <<= 16; |
| 15478 | Value |= op; |
| 15479 | break; |
| 15480 | } |
| 15481 | case AArch64::XAR_ZZZI_S: { |
| 15482 | // op: Zdn |
| 15483 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15484 | op &= UINT64_C(31); |
| 15485 | Value |= op; |
| 15486 | // op: Zm |
| 15487 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15488 | op &= UINT64_C(31); |
| 15489 | op <<= 5; |
| 15490 | Value |= op; |
| 15491 | // op: imm |
| 15492 | op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| 15493 | op &= UINT64_C(31); |
| 15494 | op <<= 16; |
| 15495 | Value |= op; |
| 15496 | break; |
| 15497 | } |
| 15498 | case AArch64::XAR_ZZZI_D: { |
| 15499 | // op: Zdn |
| 15500 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15501 | op &= UINT64_C(31); |
| 15502 | Value |= op; |
| 15503 | // op: Zm |
| 15504 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15505 | op &= UINT64_C(31); |
| 15506 | op <<= 5; |
| 15507 | Value |= op; |
| 15508 | // op: imm |
| 15509 | op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| 15510 | Value |= (op & UINT64_C(32)) << 17; |
| 15511 | Value |= (op & UINT64_C(31)) << 16; |
| 15512 | break; |
| 15513 | } |
| 15514 | case AArch64::XAR_ZZZI_B: { |
| 15515 | // op: Zdn |
| 15516 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15517 | op &= UINT64_C(31); |
| 15518 | Value |= op; |
| 15519 | // op: Zm |
| 15520 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15521 | op &= UINT64_C(31); |
| 15522 | op <<= 5; |
| 15523 | Value |= op; |
| 15524 | // op: imm |
| 15525 | op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| 15526 | op &= UINT64_C(7); |
| 15527 | op <<= 16; |
| 15528 | Value |= op; |
| 15529 | break; |
| 15530 | } |
| 15531 | case AArch64::FTMAD_ZZI_D: |
| 15532 | case AArch64::FTMAD_ZZI_H: |
| 15533 | case AArch64::FTMAD_ZZI_S: { |
| 15534 | // op: Zdn |
| 15535 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15536 | op &= UINT64_C(31); |
| 15537 | Value |= op; |
| 15538 | // op: Zm |
| 15539 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15540 | op &= UINT64_C(31); |
| 15541 | op <<= 5; |
| 15542 | Value |= op; |
| 15543 | // op: imm3 |
| 15544 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15545 | op &= UINT64_C(7); |
| 15546 | op <<= 16; |
| 15547 | Value |= op; |
| 15548 | break; |
| 15549 | } |
| 15550 | case AArch64::EXT_ZZI: { |
| 15551 | // op: Zdn |
| 15552 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15553 | op &= UINT64_C(31); |
| 15554 | Value |= op; |
| 15555 | // op: Zm |
| 15556 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15557 | op &= UINT64_C(31); |
| 15558 | op <<= 5; |
| 15559 | Value |= op; |
| 15560 | // op: imm8 |
| 15561 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15562 | Value |= (op & UINT64_C(248)) << 13; |
| 15563 | Value |= (op & UINT64_C(7)) << 10; |
| 15564 | break; |
| 15565 | } |
| 15566 | case AArch64::CADD_ZZI_B: |
| 15567 | case AArch64::CADD_ZZI_D: |
| 15568 | case AArch64::CADD_ZZI_H: |
| 15569 | case AArch64::CADD_ZZI_S: |
| 15570 | case AArch64::SQCADD_ZZI_B: |
| 15571 | case AArch64::SQCADD_ZZI_D: |
| 15572 | case AArch64::SQCADD_ZZI_H: |
| 15573 | case AArch64::SQCADD_ZZI_S: { |
| 15574 | // op: Zdn |
| 15575 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15576 | op &= UINT64_C(31); |
| 15577 | Value |= op; |
| 15578 | // op: Zm |
| 15579 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15580 | op &= UINT64_C(31); |
| 15581 | op <<= 5; |
| 15582 | Value |= op; |
| 15583 | // op: rot |
| 15584 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15585 | op &= UINT64_C(1); |
| 15586 | op <<= 10; |
| 15587 | Value |= op; |
| 15588 | break; |
| 15589 | } |
| 15590 | case AArch64::FCADD_ZPmZ_D: |
| 15591 | case AArch64::FCADD_ZPmZ_H: |
| 15592 | case AArch64::FCADD_ZPmZ_S: { |
| 15593 | // op: Zdn |
| 15594 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15595 | op &= UINT64_C(31); |
| 15596 | Value |= op; |
| 15597 | // op: Zm |
| 15598 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15599 | op &= UINT64_C(31); |
| 15600 | op <<= 5; |
| 15601 | Value |= op; |
| 15602 | // op: Pg |
| 15603 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15604 | op &= UINT64_C(7); |
| 15605 | op <<= 10; |
| 15606 | Value |= op; |
| 15607 | // op: imm |
| 15608 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| 15609 | op &= UINT64_C(1); |
| 15610 | op <<= 16; |
| 15611 | Value |= op; |
| 15612 | break; |
| 15613 | } |
| 15614 | case AArch64::ADD_ZI_B: |
| 15615 | case AArch64::ADD_ZI_D: |
| 15616 | case AArch64::ADD_ZI_H: |
| 15617 | case AArch64::ADD_ZI_S: |
| 15618 | case AArch64::SQADD_ZI_B: |
| 15619 | case AArch64::SQADD_ZI_D: |
| 15620 | case AArch64::SQADD_ZI_H: |
| 15621 | case AArch64::SQADD_ZI_S: |
| 15622 | case AArch64::SQSUB_ZI_B: |
| 15623 | case AArch64::SQSUB_ZI_D: |
| 15624 | case AArch64::SQSUB_ZI_H: |
| 15625 | case AArch64::SQSUB_ZI_S: |
| 15626 | case AArch64::SUBR_ZI_B: |
| 15627 | case AArch64::SUBR_ZI_D: |
| 15628 | case AArch64::SUBR_ZI_H: |
| 15629 | case AArch64::SUBR_ZI_S: |
| 15630 | case AArch64::SUB_ZI_B: |
| 15631 | case AArch64::SUB_ZI_D: |
| 15632 | case AArch64::SUB_ZI_H: |
| 15633 | case AArch64::SUB_ZI_S: |
| 15634 | case AArch64::UQADD_ZI_B: |
| 15635 | case AArch64::UQADD_ZI_D: |
| 15636 | case AArch64::UQADD_ZI_H: |
| 15637 | case AArch64::UQADD_ZI_S: |
| 15638 | case AArch64::UQSUB_ZI_B: |
| 15639 | case AArch64::UQSUB_ZI_D: |
| 15640 | case AArch64::UQSUB_ZI_H: |
| 15641 | case AArch64::UQSUB_ZI_S: { |
| 15642 | // op: Zdn |
| 15643 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15644 | op &= UINT64_C(31); |
| 15645 | Value |= op; |
| 15646 | // op: imm |
| 15647 | op = getImm8OptLsl(MI, 2, Fixups, STI); |
| 15648 | op &= UINT64_C(511); |
| 15649 | op <<= 5; |
| 15650 | Value |= op; |
| 15651 | break; |
| 15652 | } |
| 15653 | case AArch64::MUL_ZI_B: |
| 15654 | case AArch64::MUL_ZI_D: |
| 15655 | case AArch64::MUL_ZI_H: |
| 15656 | case AArch64::MUL_ZI_S: |
| 15657 | case AArch64::SMAX_ZI_B: |
| 15658 | case AArch64::SMAX_ZI_D: |
| 15659 | case AArch64::SMAX_ZI_H: |
| 15660 | case AArch64::SMAX_ZI_S: |
| 15661 | case AArch64::SMIN_ZI_B: |
| 15662 | case AArch64::SMIN_ZI_D: |
| 15663 | case AArch64::SMIN_ZI_H: |
| 15664 | case AArch64::SMIN_ZI_S: |
| 15665 | case AArch64::UMAX_ZI_B: |
| 15666 | case AArch64::UMAX_ZI_D: |
| 15667 | case AArch64::UMAX_ZI_H: |
| 15668 | case AArch64::UMAX_ZI_S: |
| 15669 | case AArch64::UMIN_ZI_B: |
| 15670 | case AArch64::UMIN_ZI_D: |
| 15671 | case AArch64::UMIN_ZI_H: |
| 15672 | case AArch64::UMIN_ZI_S: { |
| 15673 | // op: Zdn |
| 15674 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15675 | op &= UINT64_C(31); |
| 15676 | Value |= op; |
| 15677 | // op: imm |
| 15678 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15679 | op &= UINT64_C(255); |
| 15680 | op <<= 5; |
| 15681 | Value |= op; |
| 15682 | break; |
| 15683 | } |
| 15684 | case AArch64::AND_ZI: |
| 15685 | case AArch64::EOR_ZI: |
| 15686 | case AArch64::ORR_ZI: { |
| 15687 | // op: Zdn |
| 15688 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15689 | op &= UINT64_C(31); |
| 15690 | Value |= op; |
| 15691 | // op: imms13 |
| 15692 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15693 | op &= UINT64_C(8191); |
| 15694 | op <<= 5; |
| 15695 | Value |= op; |
| 15696 | break; |
| 15697 | } |
| 15698 | case AArch64::DECD_ZPiI: |
| 15699 | case AArch64::DECH_ZPiI: |
| 15700 | case AArch64::DECW_ZPiI: |
| 15701 | case AArch64::INCD_ZPiI: |
| 15702 | case AArch64::INCH_ZPiI: |
| 15703 | case AArch64::INCW_ZPiI: |
| 15704 | case AArch64::SQDECD_ZPiI: |
| 15705 | case AArch64::SQDECH_ZPiI: |
| 15706 | case AArch64::SQDECW_ZPiI: |
| 15707 | case AArch64::SQINCD_ZPiI: |
| 15708 | case AArch64::SQINCH_ZPiI: |
| 15709 | case AArch64::SQINCW_ZPiI: |
| 15710 | case AArch64::UQDECD_ZPiI: |
| 15711 | case AArch64::UQDECH_ZPiI: |
| 15712 | case AArch64::UQDECW_ZPiI: |
| 15713 | case AArch64::UQINCD_ZPiI: |
| 15714 | case AArch64::UQINCH_ZPiI: |
| 15715 | case AArch64::UQINCW_ZPiI: { |
| 15716 | // op: Zdn |
| 15717 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15718 | op &= UINT64_C(31); |
| 15719 | Value |= op; |
| 15720 | // op: pattern |
| 15721 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15722 | op &= UINT64_C(31); |
| 15723 | op <<= 5; |
| 15724 | Value |= op; |
| 15725 | // op: imm4 |
| 15726 | op = getSVEIncDecImm(MI, 3, Fixups, STI); |
| 15727 | op &= UINT64_C(15); |
| 15728 | op <<= 16; |
| 15729 | Value |= op; |
| 15730 | break; |
| 15731 | } |
| 15732 | case AArch64::BFMMLA_B_ZZZ: |
| 15733 | case AArch64::BFMMLA_T_ZZZ: |
| 15734 | case AArch64::BFMMLA_ZZZ: { |
| 15735 | // op: Zm |
| 15736 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15737 | op &= UINT64_C(31); |
| 15738 | op <<= 16; |
| 15739 | Value |= op; |
| 15740 | // op: Zda |
| 15741 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15742 | op &= UINT64_C(31); |
| 15743 | Value |= op; |
| 15744 | // op: Zn |
| 15745 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15746 | op &= UINT64_C(31); |
| 15747 | op <<= 5; |
| 15748 | Value |= op; |
| 15749 | break; |
| 15750 | } |
| 15751 | case AArch64::FADDV_VPZ_D: |
| 15752 | case AArch64::FADDV_VPZ_H: |
| 15753 | case AArch64::FADDV_VPZ_S: |
| 15754 | case AArch64::FMAXNMV_VPZ_D: |
| 15755 | case AArch64::FMAXNMV_VPZ_H: |
| 15756 | case AArch64::FMAXNMV_VPZ_S: |
| 15757 | case AArch64::FMAXV_VPZ_D: |
| 15758 | case AArch64::FMAXV_VPZ_H: |
| 15759 | case AArch64::FMAXV_VPZ_S: |
| 15760 | case AArch64::FMINNMV_VPZ_D: |
| 15761 | case AArch64::FMINNMV_VPZ_H: |
| 15762 | case AArch64::FMINNMV_VPZ_S: |
| 15763 | case AArch64::FMINV_VPZ_D: |
| 15764 | case AArch64::FMINV_VPZ_H: |
| 15765 | case AArch64::FMINV_VPZ_S: { |
| 15766 | // op: Zn |
| 15767 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15768 | op &= UINT64_C(31); |
| 15769 | op <<= 5; |
| 15770 | Value |= op; |
| 15771 | // op: Vd |
| 15772 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15773 | op &= UINT64_C(31); |
| 15774 | Value |= op; |
| 15775 | // op: Pg |
| 15776 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15777 | op &= UINT64_C(7); |
| 15778 | op <<= 10; |
| 15779 | Value |= op; |
| 15780 | break; |
| 15781 | } |
| 15782 | case AArch64::LD1B: |
| 15783 | case AArch64::LD1B_D: |
| 15784 | case AArch64::LD1B_H: |
| 15785 | case AArch64::LD1B_S: |
| 15786 | case AArch64::LD1D: |
| 15787 | case AArch64::LD1H: |
| 15788 | case AArch64::LD1H_D: |
| 15789 | case AArch64::LD1H_S: |
| 15790 | case AArch64::LD1SB_D: |
| 15791 | case AArch64::LD1SB_H: |
| 15792 | case AArch64::LD1SB_S: |
| 15793 | case AArch64::LD1SH_D: |
| 15794 | case AArch64::LD1SH_S: |
| 15795 | case AArch64::LD1SW_D: |
| 15796 | case AArch64::LD1W: |
| 15797 | case AArch64::LD1W_D: |
| 15798 | case AArch64::LDFF1B_D_REAL: |
| 15799 | case AArch64::LDFF1B_H_REAL: |
| 15800 | case AArch64::LDFF1B_REAL: |
| 15801 | case AArch64::LDFF1B_S_REAL: |
| 15802 | case AArch64::LDFF1D_REAL: |
| 15803 | case AArch64::LDFF1H_D_REAL: |
| 15804 | case AArch64::LDFF1H_REAL: |
| 15805 | case AArch64::LDFF1H_S_REAL: |
| 15806 | case AArch64::LDFF1SB_D_REAL: |
| 15807 | case AArch64::LDFF1SB_H_REAL: |
| 15808 | case AArch64::LDFF1SB_S_REAL: |
| 15809 | case AArch64::LDFF1SH_D_REAL: |
| 15810 | case AArch64::LDFF1SH_S_REAL: |
| 15811 | case AArch64::LDFF1SW_D_REAL: |
| 15812 | case AArch64::LDFF1W_D_REAL: |
| 15813 | case AArch64::LDFF1W_REAL: { |
| 15814 | // op: Zt |
| 15815 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15816 | op &= UINT64_C(31); |
| 15817 | Value |= op; |
| 15818 | // op: Pg |
| 15819 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15820 | op &= UINT64_C(7); |
| 15821 | op <<= 10; |
| 15822 | Value |= op; |
| 15823 | // op: Rm |
| 15824 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15825 | op &= UINT64_C(31); |
| 15826 | op <<= 16; |
| 15827 | Value |= op; |
| 15828 | // op: Rn |
| 15829 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15830 | op &= UINT64_C(31); |
| 15831 | op <<= 5; |
| 15832 | Value |= op; |
| 15833 | break; |
| 15834 | } |
| 15835 | case AArch64::LD1RO_B: |
| 15836 | case AArch64::LD1RO_D: |
| 15837 | case AArch64::LD1RO_H: |
| 15838 | case AArch64::LD1RO_W: |
| 15839 | case AArch64::LD1RQ_B: |
| 15840 | case AArch64::LD1RQ_D: |
| 15841 | case AArch64::LD1RQ_H: |
| 15842 | case AArch64::LD1RQ_W: { |
| 15843 | // op: Zt |
| 15844 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15845 | op &= UINT64_C(31); |
| 15846 | Value |= op; |
| 15847 | // op: Pg |
| 15848 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15849 | op &= UINT64_C(7); |
| 15850 | op <<= 10; |
| 15851 | Value |= op; |
| 15852 | // op: Rn |
| 15853 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15854 | op &= UINT64_C(31); |
| 15855 | op <<= 5; |
| 15856 | Value |= op; |
| 15857 | // op: Rm |
| 15858 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15859 | op &= UINT64_C(31); |
| 15860 | op <<= 16; |
| 15861 | Value |= op; |
| 15862 | break; |
| 15863 | } |
| 15864 | case AArch64::LD2B_IMM: |
| 15865 | case AArch64::LD2D_IMM: |
| 15866 | case AArch64::LD2H_IMM: |
| 15867 | case AArch64::LD2W_IMM: |
| 15868 | case AArch64::LD3B_IMM: |
| 15869 | case AArch64::LD3D_IMM: |
| 15870 | case AArch64::LD3H_IMM: |
| 15871 | case AArch64::LD3W_IMM: |
| 15872 | case AArch64::LD4B_IMM: |
| 15873 | case AArch64::LD4D_IMM: |
| 15874 | case AArch64::LD4H_IMM: |
| 15875 | case AArch64::LD4W_IMM: |
| 15876 | case AArch64::LDNT1B_ZRI: |
| 15877 | case AArch64::LDNT1D_ZRI: |
| 15878 | case AArch64::LDNT1H_ZRI: |
| 15879 | case AArch64::LDNT1W_ZRI: { |
| 15880 | // op: Zt |
| 15881 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15882 | op &= UINT64_C(31); |
| 15883 | Value |= op; |
| 15884 | // op: Pg |
| 15885 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15886 | op &= UINT64_C(7); |
| 15887 | op <<= 10; |
| 15888 | Value |= op; |
| 15889 | // op: Rn |
| 15890 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15891 | op &= UINT64_C(31); |
| 15892 | op <<= 5; |
| 15893 | Value |= op; |
| 15894 | // op: imm4 |
| 15895 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15896 | op &= UINT64_C(15); |
| 15897 | op <<= 16; |
| 15898 | Value |= op; |
| 15899 | break; |
| 15900 | } |
| 15901 | case AArch64::LD1RO_B_IMM: |
| 15902 | case AArch64::LD1RO_D_IMM: |
| 15903 | case AArch64::LD1RO_H_IMM: |
| 15904 | case AArch64::LD1RO_W_IMM: |
| 15905 | case AArch64::LD1RQ_B_IMM: |
| 15906 | case AArch64::LD1RQ_D_IMM: |
| 15907 | case AArch64::LD1RQ_H_IMM: |
| 15908 | case AArch64::LD1RQ_W_IMM: { |
| 15909 | // op: Zt |
| 15910 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15911 | op &= UINT64_C(31); |
| 15912 | Value |= op; |
| 15913 | // op: Rn |
| 15914 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15915 | op &= UINT64_C(31); |
| 15916 | op <<= 5; |
| 15917 | Value |= op; |
| 15918 | // op: Pg |
| 15919 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15920 | op &= UINT64_C(7); |
| 15921 | op <<= 10; |
| 15922 | Value |= op; |
| 15923 | // op: imm4 |
| 15924 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 15925 | op &= UINT64_C(15); |
| 15926 | op <<= 16; |
| 15927 | Value |= op; |
| 15928 | break; |
| 15929 | } |
| 15930 | case AArch64::B: |
| 15931 | case AArch64::BL: { |
| 15932 | // op: addr |
| 15933 | op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
| 15934 | op &= UINT64_C(67108863); |
| 15935 | Value |= op; |
| 15936 | break; |
| 15937 | } |
| 15938 | case AArch64::Bcc: { |
| 15939 | // op: cond |
| 15940 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15941 | op &= UINT64_C(15); |
| 15942 | Value |= op; |
| 15943 | // op: target |
| 15944 | op = getCondBranchTargetOpValue(MI, 1, Fixups, STI); |
| 15945 | op &= UINT64_C(524287); |
| 15946 | op <<= 5; |
| 15947 | Value |= op; |
| 15948 | break; |
| 15949 | } |
| 15950 | case AArch64::CPYi64: { |
| 15951 | // op: dst |
| 15952 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15953 | op &= UINT64_C(31); |
| 15954 | Value |= op; |
| 15955 | // op: src |
| 15956 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15957 | op &= UINT64_C(31); |
| 15958 | op <<= 5; |
| 15959 | Value |= op; |
| 15960 | // op: idx |
| 15961 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15962 | op &= UINT64_C(1); |
| 15963 | op <<= 20; |
| 15964 | Value |= op; |
| 15965 | break; |
| 15966 | } |
| 15967 | case AArch64::CPYi8: { |
| 15968 | // op: dst |
| 15969 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15970 | op &= UINT64_C(31); |
| 15971 | Value |= op; |
| 15972 | // op: src |
| 15973 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15974 | op &= UINT64_C(31); |
| 15975 | op <<= 5; |
| 15976 | Value |= op; |
| 15977 | // op: idx |
| 15978 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15979 | op &= UINT64_C(15); |
| 15980 | op <<= 17; |
| 15981 | Value |= op; |
| 15982 | break; |
| 15983 | } |
| 15984 | case AArch64::CPYi32: { |
| 15985 | // op: dst |
| 15986 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 15987 | op &= UINT64_C(31); |
| 15988 | Value |= op; |
| 15989 | // op: src |
| 15990 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 15991 | op &= UINT64_C(31); |
| 15992 | op <<= 5; |
| 15993 | Value |= op; |
| 15994 | // op: idx |
| 15995 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 15996 | op &= UINT64_C(3); |
| 15997 | op <<= 19; |
| 15998 | Value |= op; |
| 15999 | break; |
| 16000 | } |
| 16001 | case AArch64::CPYi16: { |
| 16002 | // op: dst |
| 16003 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 16004 | op &= UINT64_C(31); |
| 16005 | Value |= op; |
| 16006 | // op: src |
| 16007 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 16008 | op &= UINT64_C(31); |
| 16009 | op <<= 5; |
| 16010 | Value |= op; |
| 16011 | // op: idx |
| 16012 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 16013 | op &= UINT64_C(7); |
| 16014 | op <<= 18; |
| 16015 | Value |= op; |
| 16016 | break; |
| 16017 | } |
| 16018 | case AArch64::ADDSWrs: |
| 16019 | case AArch64::ADDSXrs: |
| 16020 | case AArch64::ADDWrs: |
| 16021 | case AArch64::ADDXrs: |
| 16022 | case AArch64::ANDSWrs: |
| 16023 | case AArch64::ANDSXrs: |
| 16024 | case AArch64::ANDWrs: |
| 16025 | case AArch64::ANDXrs: |
| 16026 | case AArch64::BICSWrs: |
| 16027 | case AArch64::BICSXrs: |
| 16028 | case AArch64::BICWrs: |
| 16029 | case AArch64::BICXrs: |
| 16030 | case AArch64::EONWrs: |
| 16031 | case AArch64::EONXrs: |
| 16032 | case AArch64::EORWrs: |
| 16033 | case AArch64::EORXrs: |
| 16034 | case AArch64::ORNWrs: |
| 16035 | case AArch64::ORNXrs: |
| 16036 | case AArch64::ORRWrs: |
| 16037 | case AArch64::ORRXrs: |
| 16038 | case AArch64::SUBSWrs: |
| 16039 | case AArch64::SUBSXrs: |
| 16040 | case AArch64::SUBWrs: |
| 16041 | case AArch64::SUBXrs: { |
| 16042 | // op: dst |
| 16043 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 16044 | op &= UINT64_C(31); |
| 16045 | Value |= op; |
| 16046 | // op: src1 |
| 16047 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 16048 | op &= UINT64_C(31); |
| 16049 | op <<= 5; |
| 16050 | Value |= op; |
| 16051 | // op: src2 |
| 16052 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 16053 | op &= UINT64_C(31); |
| 16054 | op <<= 16; |
| 16055 | Value |= op; |
| 16056 | // op: shift |
| 16057 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 16058 | Value |= (op & UINT64_C(192)) << 16; |
| 16059 | Value |= (op & UINT64_C(63)) << 10; |
| 16060 | break; |
| 16061 | } |
| 16062 | case AArch64::HINT: { |
| 16063 | // op: imm |
| 16064 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 16065 | op &= UINT64_C(127); |
| 16066 | op <<= 5; |
| 16067 | Value |= op; |
| 16068 | break; |
| 16069 | } |
| 16070 | case AArch64::UDF: { |
| 16071 | // op: imm |
| 16072 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 16073 | op &= UINT64_C(65535); |
| 16074 | Value |= op; |
| 16075 | break; |
| 16076 | } |
| 16077 | case AArch64::BRK: |
| 16078 | case AArch64::DCPS1: |
| 16079 | case AArch64::DCPS2: |
| 16080 | case AArch64::DCPS3: |
| 16081 | case AArch64::HLT: |
| 16082 | case AArch64::HVC: |
| 16083 | case AArch64::SMC: |
| 16084 | case AArch64::SVC: |
| 16085 | case AArch64::TCANCEL: { |
| 16086 | // op: imm |
| 16087 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 16088 | op &= UINT64_C(65535); |
| 16089 | op <<= 5; |
| 16090 | Value |= op; |
| 16091 | break; |
| 16092 | } |
| 16093 | case AArch64::LDRAAindexed: |
| 16094 | case AArch64::LDRABindexed: { |
| 16095 | // op: offset |
| 16096 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 16097 | Value |= (op & UINT64_C(512)) << 13; |
| 16098 | Value |= (op & UINT64_C(511)) << 12; |
| 16099 | // op: Rn |
| 16100 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 16101 | op &= UINT64_C(31); |
| 16102 | op <<= 5; |
| 16103 | Value |= op; |
| 16104 | // op: Rt |
| 16105 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 16106 | op &= UINT64_C(31); |
| 16107 | Value |= op; |
| 16108 | break; |
| 16109 | } |
| 16110 | case AArch64::LDRAAwriteback: |
| 16111 | case AArch64::LDRABwriteback: { |
| 16112 | // op: offset |
| 16113 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| 16114 | Value |= (op & UINT64_C(512)) << 13; |
| 16115 | Value |= (op & UINT64_C(511)) << 12; |
| 16116 | // op: Rn |
| 16117 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| 16118 | op &= UINT64_C(31); |
| 16119 | op <<= 5; |
| 16120 | Value |= op; |
| 16121 | // op: Rt |
| 16122 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 16123 | op &= UINT64_C(31); |
| 16124 | Value |= op; |
| 16125 | break; |
| 16126 | } |
| 16127 | case AArch64::MSRpstateImm1: { |
| 16128 | // op: pstatefield |
| 16129 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 16130 | Value |= (op & UINT64_C(56)) << 13; |
| 16131 | Value |= (op & UINT64_C(7)) << 5; |
| 16132 | // op: imm |
| 16133 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 16134 | op &= UINT64_C(1); |
| 16135 | op <<= 8; |
| 16136 | Value |= op; |
| 16137 | break; |
| 16138 | } |
| 16139 | case AArch64::MSRpstateImm4: { |
| 16140 | // op: pstatefield |
| 16141 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| 16142 | Value |= (op & UINT64_C(56)) << 13; |
| 16143 | Value |= (op & UINT64_C(7)) << 5; |
| 16144 | // op: imm |
| 16145 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| 16146 | op &= UINT64_C(15); |
| 16147 | op <<= 8; |
| 16148 | Value |= op; |
| 16149 | break; |
| 16150 | } |
| 16151 | default: |
| 16152 | std::string msg; |
| 16153 | raw_string_ostream Msg(msg); |
| 16154 | Msg << "Not supported instr: " << MI; |
| 16155 | report_fatal_error(Msg.str()); |
| 16156 | } |
| 16157 | return Value; |
| 16158 | } |
| 16159 | |
| 16160 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 16161 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 16162 | #include <sstream> |
| 16163 | |
| 16164 | // Bits for subtarget features that participate in instruction matching. |
| 16165 | enum SubtargetFeatureBits : uint8_t { |
| 16166 | Feature_HasV8_1aBit = 60, |
| 16167 | Feature_HasV8_2aBit = 61, |
| 16168 | Feature_HasV8_3aBit = 62, |
| 16169 | Feature_HasV8_4aBit = 63, |
| 16170 | Feature_HasV8_5aBit = 64, |
| 16171 | Feature_HasV8_6aBit = 65, |
| 16172 | Feature_HasV8_7aBit = 66, |
| 16173 | Feature_HasVHBit = 67, |
| 16174 | Feature_HasLORBit = 23, |
| 16175 | Feature_HasPAuthBit = 35, |
| 16176 | Feature_HasJSBit = 22, |
| 16177 | Feature_HasCCIDXBit = 7, |
| 16178 | Feature_HasComplxNumBit = 11, |
| 16179 | Feature_HasNVBit = 32, |
| 16180 | Feature_HasMPAMBit = 26, |
| 16181 | Feature_HasDITBit = 13, |
| 16182 | Feature_HasTRACEV8_4Bit = 58, |
| 16183 | Feature_HasAMBit = 1, |
| 16184 | Feature_HasSEL2Bit = 44, |
| 16185 | Feature_HasPMUBit = 36, |
| 16186 | Feature_HasTLB_RMIBit = 56, |
| 16187 | Feature_HasFlagMBit = 19, |
| 16188 | Feature_HasRCPC_IMMOBit = 41, |
| 16189 | Feature_HasFPARMv8Bit = 17, |
| 16190 | Feature_HasNEONBit = 31, |
| 16191 | Feature_HasCryptoBit = 12, |
| 16192 | Feature_HasSM4Bit = 47, |
| 16193 | Feature_HasSHA3Bit = 46, |
| 16194 | Feature_HasSHA2Bit = 45, |
| 16195 | Feature_HasAESBit = 0, |
| 16196 | Feature_HasDotProdBit = 14, |
| 16197 | Feature_HasCRCBit = 10, |
| 16198 | Feature_HasLSEBit = 25, |
| 16199 | Feature_HasRASBit = 39, |
| 16200 | Feature_HasRDMBit = 42, |
| 16201 | Feature_HasFullFP16Bit = 20, |
| 16202 | Feature_HasFP16FMLBit = 16, |
| 16203 | Feature_HasSPEBit = 48, |
| 16204 | Feature_HasFuseAESBit = 21, |
| 16205 | Feature_HasSVEBit = 50, |
| 16206 | Feature_HasSVE2Bit = 51, |
| 16207 | Feature_HasSVE2AESBit = 52, |
| 16208 | Feature_HasSVE2SM4Bit = 55, |
| 16209 | Feature_HasSVE2SHA3Bit = 54, |
| 16210 | Feature_HasSVE2BitPermBit = 53, |
| 16211 | Feature_HasRCPCBit = 40, |
| 16212 | Feature_HasAltNZCVBit = 2, |
| 16213 | Feature_HasFRInt3264Bit = 18, |
| 16214 | Feature_HasSBBit = 43, |
| 16215 | Feature_HasPredResBit = 37, |
| 16216 | Feature_HasCCDPBit = 6, |
| 16217 | Feature_HasBTIBit = 5, |
| 16218 | Feature_HasMTEBit = 27, |
| 16219 | Feature_HasTMEBit = 57, |
| 16220 | Feature_HasETEBit = 15, |
| 16221 | Feature_HasTRBEBit = 59, |
| 16222 | Feature_HasBF16Bit = 3, |
| 16223 | Feature_HasMatMulInt8Bit = 30, |
| 16224 | Feature_HasMatMulFP32Bit = 28, |
| 16225 | Feature_HasMatMulFP64Bit = 29, |
| 16226 | Feature_HasXSBit = 69, |
| 16227 | Feature_HasWFxTBit = 68, |
| 16228 | Feature_HasLS64Bit = 24, |
| 16229 | Feature_HasBRBEBit = 4, |
| 16230 | Feature_HasSPE_EEFBit = 49, |
| 16231 | Feature_UseNegativeImmediatesBit = 70, |
| 16232 | Feature_HasCCPPBit = 8, |
| 16233 | Feature_HasPANBit = 33, |
| 16234 | Feature_HasPsUAOBit = 38, |
| 16235 | Feature_HasPAN_RWVBit = 34, |
| 16236 | Feature_HasCONTEXTIDREL2Bit = 9, |
| 16237 | }; |
| 16238 | |
| 16239 | #ifndef NDEBUG |
| 16240 | static const char *SubtargetFeatureNames[] = { |
| 16241 | "Feature_HasAES" , |
| 16242 | "Feature_HasAM" , |
| 16243 | "Feature_HasAltNZCV" , |
| 16244 | "Feature_HasBF16" , |
| 16245 | "Feature_HasBRBE" , |
| 16246 | "Feature_HasBTI" , |
| 16247 | "Feature_HasCCDP" , |
| 16248 | "Feature_HasCCIDX" , |
| 16249 | "Feature_HasCCPP" , |
| 16250 | "Feature_HasCONTEXTIDREL2" , |
| 16251 | "Feature_HasCRC" , |
| 16252 | "Feature_HasComplxNum" , |
| 16253 | "Feature_HasCrypto" , |
| 16254 | "Feature_HasDIT" , |
| 16255 | "Feature_HasDotProd" , |
| 16256 | "Feature_HasETE" , |
| 16257 | "Feature_HasFP16FML" , |
| 16258 | "Feature_HasFPARMv8" , |
| 16259 | "Feature_HasFRInt3264" , |
| 16260 | "Feature_HasFlagM" , |
| 16261 | "Feature_HasFullFP16" , |
| 16262 | "Feature_HasFuseAES" , |
| 16263 | "Feature_HasJS" , |
| 16264 | "Feature_HasLOR" , |
| 16265 | "Feature_HasLS64" , |
| 16266 | "Feature_HasLSE" , |
| 16267 | "Feature_HasMPAM" , |
| 16268 | "Feature_HasMTE" , |
| 16269 | "Feature_HasMatMulFP32" , |
| 16270 | "Feature_HasMatMulFP64" , |
| 16271 | "Feature_HasMatMulInt8" , |
| 16272 | "Feature_HasNEON" , |
| 16273 | "Feature_HasNV" , |
| 16274 | "Feature_HasPAN" , |
| 16275 | "Feature_HasPAN_RWV" , |
| 16276 | "Feature_HasPAuth" , |
| 16277 | "Feature_HasPMU" , |
| 16278 | "Feature_HasPredRes" , |
| 16279 | "Feature_HasPsUAO" , |
| 16280 | "Feature_HasRAS" , |
| 16281 | "Feature_HasRCPC" , |
| 16282 | "Feature_HasRCPC_IMMO" , |
| 16283 | "Feature_HasRDM" , |
| 16284 | "Feature_HasSB" , |
| 16285 | "Feature_HasSEL2" , |
| 16286 | "Feature_HasSHA2" , |
| 16287 | "Feature_HasSHA3" , |
| 16288 | "Feature_HasSM4" , |
| 16289 | "Feature_HasSPE" , |
| 16290 | "Feature_HasSPE_EEF" , |
| 16291 | "Feature_HasSVE" , |
| 16292 | "Feature_HasSVE2" , |
| 16293 | "Feature_HasSVE2AES" , |
| 16294 | "Feature_HasSVE2BitPerm" , |
| 16295 | "Feature_HasSVE2SHA3" , |
| 16296 | "Feature_HasSVE2SM4" , |
| 16297 | "Feature_HasTLB_RMI" , |
| 16298 | "Feature_HasTME" , |
| 16299 | "Feature_HasTRACEV8_4" , |
| 16300 | "Feature_HasTRBE" , |
| 16301 | "Feature_HasV8_1a" , |
| 16302 | "Feature_HasV8_2a" , |
| 16303 | "Feature_HasV8_3a" , |
| 16304 | "Feature_HasV8_4a" , |
| 16305 | "Feature_HasV8_5a" , |
| 16306 | "Feature_HasV8_6a" , |
| 16307 | "Feature_HasV8_7a" , |
| 16308 | "Feature_HasVH" , |
| 16309 | "Feature_HasWFxT" , |
| 16310 | "Feature_HasXS" , |
| 16311 | "Feature_UseNegativeImmediates" , |
| 16312 | nullptr |
| 16313 | }; |
| 16314 | |
| 16315 | #endif // NDEBUG |
| 16316 | FeatureBitset AArch64MCCodeEmitter:: |
| 16317 | computeAvailableFeatures(const FeatureBitset &FB) const { |
| 16318 | FeatureBitset Features; |
| 16319 | if (FB[AArch64::HasV8_1aOps]) |
| 16320 | Features.set(Feature_HasV8_1aBit); |
| 16321 | if (FB[AArch64::HasV8_2aOps]) |
| 16322 | Features.set(Feature_HasV8_2aBit); |
| 16323 | if (FB[AArch64::HasV8_3aOps]) |
| 16324 | Features.set(Feature_HasV8_3aBit); |
| 16325 | if (FB[AArch64::HasV8_4aOps]) |
| 16326 | Features.set(Feature_HasV8_4aBit); |
| 16327 | if (FB[AArch64::HasV8_5aOps]) |
| 16328 | Features.set(Feature_HasV8_5aBit); |
| 16329 | if (FB[AArch64::HasV8_6aOps]) |
| 16330 | Features.set(Feature_HasV8_6aBit); |
| 16331 | if (FB[AArch64::HasV8_7aOps]) |
| 16332 | Features.set(Feature_HasV8_7aBit); |
| 16333 | if (FB[AArch64::FeatureVH]) |
| 16334 | Features.set(Feature_HasVHBit); |
| 16335 | if (FB[AArch64::FeatureLOR]) |
| 16336 | Features.set(Feature_HasLORBit); |
| 16337 | if (FB[AArch64::FeaturePAuth]) |
| 16338 | Features.set(Feature_HasPAuthBit); |
| 16339 | if (FB[AArch64::FeatureJS]) |
| 16340 | Features.set(Feature_HasJSBit); |
| 16341 | if (FB[AArch64::FeatureCCIDX]) |
| 16342 | Features.set(Feature_HasCCIDXBit); |
| 16343 | if (FB[AArch64::FeatureComplxNum]) |
| 16344 | Features.set(Feature_HasComplxNumBit); |
| 16345 | if (FB[AArch64::FeatureNV]) |
| 16346 | Features.set(Feature_HasNVBit); |
| 16347 | if (FB[AArch64::FeatureMPAM]) |
| 16348 | Features.set(Feature_HasMPAMBit); |
| 16349 | if (FB[AArch64::FeatureDIT]) |
| 16350 | Features.set(Feature_HasDITBit); |
| 16351 | if (FB[AArch64::FeatureTRACEV8_4]) |
| 16352 | Features.set(Feature_HasTRACEV8_4Bit); |
| 16353 | if (FB[AArch64::FeatureAM]) |
| 16354 | Features.set(Feature_HasAMBit); |
| 16355 | if (FB[AArch64::FeatureSEL2]) |
| 16356 | Features.set(Feature_HasSEL2Bit); |
| 16357 | if (FB[AArch64::FeaturePMU]) |
| 16358 | Features.set(Feature_HasPMUBit); |
| 16359 | if (FB[AArch64::FeatureTLB_RMI]) |
| 16360 | Features.set(Feature_HasTLB_RMIBit); |
| 16361 | if (FB[AArch64::FeatureFlagM]) |
| 16362 | Features.set(Feature_HasFlagMBit); |
| 16363 | if (FB[AArch64::FeatureRCPC_IMMO]) |
| 16364 | Features.set(Feature_HasRCPC_IMMOBit); |
| 16365 | if (FB[AArch64::FeatureFPARMv8]) |
| 16366 | Features.set(Feature_HasFPARMv8Bit); |
| 16367 | if (FB[AArch64::FeatureNEON]) |
| 16368 | Features.set(Feature_HasNEONBit); |
| 16369 | if (FB[AArch64::FeatureCrypto]) |
| 16370 | Features.set(Feature_HasCryptoBit); |
| 16371 | if (FB[AArch64::FeatureSM4]) |
| 16372 | Features.set(Feature_HasSM4Bit); |
| 16373 | if (FB[AArch64::FeatureSHA3]) |
| 16374 | Features.set(Feature_HasSHA3Bit); |
| 16375 | if (FB[AArch64::FeatureSHA2]) |
| 16376 | Features.set(Feature_HasSHA2Bit); |
| 16377 | if (FB[AArch64::FeatureAES]) |
| 16378 | Features.set(Feature_HasAESBit); |
| 16379 | if (FB[AArch64::FeatureDotProd]) |
| 16380 | Features.set(Feature_HasDotProdBit); |
| 16381 | if (FB[AArch64::FeatureCRC]) |
| 16382 | Features.set(Feature_HasCRCBit); |
| 16383 | if (FB[AArch64::FeatureLSE]) |
| 16384 | Features.set(Feature_HasLSEBit); |
| 16385 | if (FB[AArch64::FeatureRAS]) |
| 16386 | Features.set(Feature_HasRASBit); |
| 16387 | if (FB[AArch64::FeatureRDM]) |
| 16388 | Features.set(Feature_HasRDMBit); |
| 16389 | if (FB[AArch64::FeatureFullFP16]) |
| 16390 | Features.set(Feature_HasFullFP16Bit); |
| 16391 | if (FB[AArch64::FeatureFP16FML]) |
| 16392 | Features.set(Feature_HasFP16FMLBit); |
| 16393 | if (FB[AArch64::FeatureSPE]) |
| 16394 | Features.set(Feature_HasSPEBit); |
| 16395 | if (FB[AArch64::FeatureFuseAES]) |
| 16396 | Features.set(Feature_HasFuseAESBit); |
| 16397 | if (FB[AArch64::FeatureSVE]) |
| 16398 | Features.set(Feature_HasSVEBit); |
| 16399 | if (FB[AArch64::FeatureSVE2]) |
| 16400 | Features.set(Feature_HasSVE2Bit); |
| 16401 | if (FB[AArch64::FeatureSVE2AES]) |
| 16402 | Features.set(Feature_HasSVE2AESBit); |
| 16403 | if (FB[AArch64::FeatureSVE2SM4]) |
| 16404 | Features.set(Feature_HasSVE2SM4Bit); |
| 16405 | if (FB[AArch64::FeatureSVE2SHA3]) |
| 16406 | Features.set(Feature_HasSVE2SHA3Bit); |
| 16407 | if (FB[AArch64::FeatureSVE2BitPerm]) |
| 16408 | Features.set(Feature_HasSVE2BitPermBit); |
| 16409 | if (FB[AArch64::FeatureRCPC]) |
| 16410 | Features.set(Feature_HasRCPCBit); |
| 16411 | if (FB[AArch64::FeatureAltFPCmp]) |
| 16412 | Features.set(Feature_HasAltNZCVBit); |
| 16413 | if (FB[AArch64::FeatureFRInt3264]) |
| 16414 | Features.set(Feature_HasFRInt3264Bit); |
| 16415 | if (FB[AArch64::FeatureSB]) |
| 16416 | Features.set(Feature_HasSBBit); |
| 16417 | if (FB[AArch64::FeaturePredRes]) |
| 16418 | Features.set(Feature_HasPredResBit); |
| 16419 | if (FB[AArch64::FeatureCacheDeepPersist]) |
| 16420 | Features.set(Feature_HasCCDPBit); |
| 16421 | if (FB[AArch64::FeatureBranchTargetId]) |
| 16422 | Features.set(Feature_HasBTIBit); |
| 16423 | if (FB[AArch64::FeatureMTE]) |
| 16424 | Features.set(Feature_HasMTEBit); |
| 16425 | if (FB[AArch64::FeatureTME]) |
| 16426 | Features.set(Feature_HasTMEBit); |
| 16427 | if (FB[AArch64::FeatureETE]) |
| 16428 | Features.set(Feature_HasETEBit); |
| 16429 | if (FB[AArch64::FeatureTRBE]) |
| 16430 | Features.set(Feature_HasTRBEBit); |
| 16431 | if (FB[AArch64::FeatureBF16]) |
| 16432 | Features.set(Feature_HasBF16Bit); |
| 16433 | if (FB[AArch64::FeatureMatMulInt8]) |
| 16434 | Features.set(Feature_HasMatMulInt8Bit); |
| 16435 | if (FB[AArch64::FeatureMatMulFP32]) |
| 16436 | Features.set(Feature_HasMatMulFP32Bit); |
| 16437 | if (FB[AArch64::FeatureMatMulFP64]) |
| 16438 | Features.set(Feature_HasMatMulFP64Bit); |
| 16439 | if (FB[AArch64::FeatureXS]) |
| 16440 | Features.set(Feature_HasXSBit); |
| 16441 | if (FB[AArch64::FeatureWFxT]) |
| 16442 | Features.set(Feature_HasWFxTBit); |
| 16443 | if (FB[AArch64::FeatureLS64]) |
| 16444 | Features.set(Feature_HasLS64Bit); |
| 16445 | if (FB[AArch64::FeatureBRBE]) |
| 16446 | Features.set(Feature_HasBRBEBit); |
| 16447 | if (FB[AArch64::FeatureSPE_EEF]) |
| 16448 | Features.set(Feature_HasSPE_EEFBit); |
| 16449 | if (!FB[AArch64::FeatureNoNegativeImmediates]) |
| 16450 | Features.set(Feature_UseNegativeImmediatesBit); |
| 16451 | if (FB[AArch64::FeatureCCPP]) |
| 16452 | Features.set(Feature_HasCCPPBit); |
| 16453 | if (FB[AArch64::FeaturePAN]) |
| 16454 | Features.set(Feature_HasPANBit); |
| 16455 | if (FB[AArch64::FeaturePsUAO]) |
| 16456 | Features.set(Feature_HasPsUAOBit); |
| 16457 | if (FB[AArch64::FeaturePAN_RWV]) |
| 16458 | Features.set(Feature_HasPAN_RWVBit); |
| 16459 | if (FB[AArch64::FeatureCONTEXTIDREL2]) |
| 16460 | Features.set(Feature_HasCONTEXTIDREL2Bit); |
| 16461 | return Features; |
| 16462 | } |
| 16463 | |
| 16464 | #ifndef NDEBUG |
| 16465 | // Feature bitsets. |
| 16466 | enum : uint8_t { |
| 16467 | CEFBS_None, |
| 16468 | CEFBS_HasAES, |
| 16469 | CEFBS_HasAltNZCV, |
| 16470 | CEFBS_HasBF16, |
| 16471 | CEFBS_HasBRBE, |
| 16472 | CEFBS_HasCRC, |
| 16473 | CEFBS_HasDotProd, |
| 16474 | CEFBS_HasFPARMv8, |
| 16475 | CEFBS_HasFRInt3264, |
| 16476 | CEFBS_HasFlagM, |
| 16477 | CEFBS_HasFullFP16, |
| 16478 | CEFBS_HasLOR, |
| 16479 | CEFBS_HasLS64, |
| 16480 | CEFBS_HasLSE, |
| 16481 | CEFBS_HasMTE, |
| 16482 | CEFBS_HasMatMulInt8, |
| 16483 | CEFBS_HasNEON, |
| 16484 | CEFBS_HasPAuth, |
| 16485 | CEFBS_HasRCPC, |
| 16486 | CEFBS_HasRCPC_IMMO, |
| 16487 | CEFBS_HasRDM, |
| 16488 | CEFBS_HasSB, |
| 16489 | CEFBS_HasSHA2, |
| 16490 | CEFBS_HasSHA3, |
| 16491 | CEFBS_HasSM4, |
| 16492 | CEFBS_HasSVE, |
| 16493 | CEFBS_HasSVE2, |
| 16494 | CEFBS_HasSVE2AES, |
| 16495 | CEFBS_HasSVE2BitPerm, |
| 16496 | CEFBS_HasSVE2SHA3, |
| 16497 | CEFBS_HasSVE2SM4, |
| 16498 | CEFBS_HasTME, |
| 16499 | CEFBS_HasTRACEV8_4, |
| 16500 | CEFBS_HasWFxT, |
| 16501 | CEFBS_HasXS, |
| 16502 | CEFBS_HasBF16_HasSVE, |
| 16503 | CEFBS_HasComplxNum_HasNEON, |
| 16504 | CEFBS_HasJS_HasFPARMv8, |
| 16505 | CEFBS_HasNEON_HasFP16FML, |
| 16506 | CEFBS_HasNEON_HasFullFP16, |
| 16507 | CEFBS_HasNEON_HasRDM, |
| 16508 | CEFBS_HasSVE_HasMatMulFP32, |
| 16509 | CEFBS_HasSVE_HasMatMulFP64, |
| 16510 | CEFBS_HasSVE_HasMatMulInt8, |
| 16511 | CEFBS_HasComplxNum_HasNEON_HasFullFP16, |
| 16512 | }; |
| 16513 | |
| 16514 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 16515 | {}, // CEFBS_None |
| 16516 | {Feature_HasAESBit, }, |
| 16517 | {Feature_HasAltNZCVBit, }, |
| 16518 | {Feature_HasBF16Bit, }, |
| 16519 | {Feature_HasBRBEBit, }, |
| 16520 | {Feature_HasCRCBit, }, |
| 16521 | {Feature_HasDotProdBit, }, |
| 16522 | {Feature_HasFPARMv8Bit, }, |
| 16523 | {Feature_HasFRInt3264Bit, }, |
| 16524 | {Feature_HasFlagMBit, }, |
| 16525 | {Feature_HasFullFP16Bit, }, |
| 16526 | {Feature_HasLORBit, }, |
| 16527 | {Feature_HasLS64Bit, }, |
| 16528 | {Feature_HasLSEBit, }, |
| 16529 | {Feature_HasMTEBit, }, |
| 16530 | {Feature_HasMatMulInt8Bit, }, |
| 16531 | {Feature_HasNEONBit, }, |
| 16532 | {Feature_HasPAuthBit, }, |
| 16533 | {Feature_HasRCPCBit, }, |
| 16534 | {Feature_HasRCPC_IMMOBit, }, |
| 16535 | {Feature_HasRDMBit, }, |
| 16536 | {Feature_HasSBBit, }, |
| 16537 | {Feature_HasSHA2Bit, }, |
| 16538 | {Feature_HasSHA3Bit, }, |
| 16539 | {Feature_HasSM4Bit, }, |
| 16540 | {Feature_HasSVEBit, }, |
| 16541 | {Feature_HasSVE2Bit, }, |
| 16542 | {Feature_HasSVE2AESBit, }, |
| 16543 | {Feature_HasSVE2BitPermBit, }, |
| 16544 | {Feature_HasSVE2SHA3Bit, }, |
| 16545 | {Feature_HasSVE2SM4Bit, }, |
| 16546 | {Feature_HasTMEBit, }, |
| 16547 | {Feature_HasTRACEV8_4Bit, }, |
| 16548 | {Feature_HasWFxTBit, }, |
| 16549 | {Feature_HasXSBit, }, |
| 16550 | {Feature_HasBF16Bit, Feature_HasSVEBit, }, |
| 16551 | {Feature_HasComplxNumBit, Feature_HasNEONBit, }, |
| 16552 | {Feature_HasJSBit, Feature_HasFPARMv8Bit, }, |
| 16553 | {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, |
| 16554 | {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 16555 | {Feature_HasNEONBit, Feature_HasRDMBit, }, |
| 16556 | {Feature_HasSVEBit, Feature_HasMatMulFP32Bit, }, |
| 16557 | {Feature_HasSVEBit, Feature_HasMatMulFP64Bit, }, |
| 16558 | {Feature_HasSVEBit, Feature_HasMatMulInt8Bit, }, |
| 16559 | {Feature_HasComplxNumBit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 16560 | }; |
| 16561 | #endif // NDEBUG |
| 16562 | |
| 16563 | void AArch64MCCodeEmitter::verifyInstructionPredicates( |
| 16564 | const MCInst &Inst, const FeatureBitset &AvailableFeatures) const { |
| 16565 | #ifndef NDEBUG |
| 16566 | static uint8_t RequiredFeaturesRefs[] = { |
| 16567 | CEFBS_None, // PHI = 0 |
| 16568 | CEFBS_None, // INLINEASM = 1 |
| 16569 | CEFBS_None, // INLINEASM_BR = 2 |
| 16570 | CEFBS_None, // CFI_INSTRUCTION = 3 |
| 16571 | CEFBS_None, // EH_LABEL = 4 |
| 16572 | CEFBS_None, // GC_LABEL = 5 |
| 16573 | CEFBS_None, // ANNOTATION_LABEL = 6 |
| 16574 | CEFBS_None, // KILL = 7 |
| 16575 | CEFBS_None, // EXTRACT_SUBREG = 8 |
| 16576 | CEFBS_None, // INSERT_SUBREG = 9 |
| 16577 | CEFBS_None, // IMPLICIT_DEF = 10 |
| 16578 | CEFBS_None, // SUBREG_TO_REG = 11 |
| 16579 | CEFBS_None, // COPY_TO_REGCLASS = 12 |
| 16580 | CEFBS_None, // DBG_VALUE = 13 |
| 16581 | CEFBS_None, // DBG_INSTR_REF = 14 |
| 16582 | CEFBS_None, // DBG_LABEL = 15 |
| 16583 | CEFBS_None, // REG_SEQUENCE = 16 |
| 16584 | CEFBS_None, // COPY = 17 |
| 16585 | CEFBS_None, // BUNDLE = 18 |
| 16586 | CEFBS_None, // LIFETIME_START = 19 |
| 16587 | CEFBS_None, // LIFETIME_END = 20 |
| 16588 | CEFBS_None, // PSEUDO_PROBE = 21 |
| 16589 | CEFBS_None, // STACKMAP = 22 |
| 16590 | CEFBS_None, // FENTRY_CALL = 23 |
| 16591 | CEFBS_None, // PATCHPOINT = 24 |
| 16592 | CEFBS_None, // LOAD_STACK_GUARD = 25 |
| 16593 | CEFBS_None, // PREALLOCATED_SETUP = 26 |
| 16594 | CEFBS_None, // PREALLOCATED_ARG = 27 |
| 16595 | CEFBS_None, // STATEPOINT = 28 |
| 16596 | CEFBS_None, // LOCAL_ESCAPE = 29 |
| 16597 | CEFBS_None, // FAULTING_OP = 30 |
| 16598 | CEFBS_None, // PATCHABLE_OP = 31 |
| 16599 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 32 |
| 16600 | CEFBS_None, // PATCHABLE_RET = 33 |
| 16601 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 34 |
| 16602 | CEFBS_None, // PATCHABLE_TAIL_CALL = 35 |
| 16603 | CEFBS_None, // PATCHABLE_EVENT_CALL = 36 |
| 16604 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 37 |
| 16605 | CEFBS_None, // ICALL_BRANCH_FUNNEL = 38 |
| 16606 | CEFBS_None, // G_ADD = 39 |
| 16607 | CEFBS_None, // G_SUB = 40 |
| 16608 | CEFBS_None, // G_MUL = 41 |
| 16609 | CEFBS_None, // G_SDIV = 42 |
| 16610 | CEFBS_None, // G_UDIV = 43 |
| 16611 | CEFBS_None, // G_SREM = 44 |
| 16612 | CEFBS_None, // G_UREM = 45 |
| 16613 | CEFBS_None, // G_AND = 46 |
| 16614 | CEFBS_None, // G_OR = 47 |
| 16615 | CEFBS_None, // G_XOR = 48 |
| 16616 | CEFBS_None, // G_IMPLICIT_DEF = 49 |
| 16617 | CEFBS_None, // G_PHI = 50 |
| 16618 | CEFBS_None, // G_FRAME_INDEX = 51 |
| 16619 | CEFBS_None, // G_GLOBAL_VALUE = 52 |
| 16620 | CEFBS_None, // G_EXTRACT = 53 |
| 16621 | CEFBS_None, // G_UNMERGE_VALUES = 54 |
| 16622 | CEFBS_None, // G_INSERT = 55 |
| 16623 | CEFBS_None, // G_MERGE_VALUES = 56 |
| 16624 | CEFBS_None, // G_BUILD_VECTOR = 57 |
| 16625 | CEFBS_None, // G_BUILD_VECTOR_TRUNC = 58 |
| 16626 | CEFBS_None, // G_CONCAT_VECTORS = 59 |
| 16627 | CEFBS_None, // G_PTRTOINT = 60 |
| 16628 | CEFBS_None, // G_INTTOPTR = 61 |
| 16629 | CEFBS_None, // G_BITCAST = 62 |
| 16630 | CEFBS_None, // G_FREEZE = 63 |
| 16631 | CEFBS_None, // G_INTRINSIC_TRUNC = 64 |
| 16632 | CEFBS_None, // G_INTRINSIC_ROUND = 65 |
| 16633 | CEFBS_None, // G_INTRINSIC_LRINT = 66 |
| 16634 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 67 |
| 16635 | CEFBS_None, // G_READCYCLECOUNTER = 68 |
| 16636 | CEFBS_None, // G_LOAD = 69 |
| 16637 | CEFBS_None, // G_SEXTLOAD = 70 |
| 16638 | CEFBS_None, // G_ZEXTLOAD = 71 |
| 16639 | CEFBS_None, // G_INDEXED_LOAD = 72 |
| 16640 | CEFBS_None, // G_INDEXED_SEXTLOAD = 73 |
| 16641 | CEFBS_None, // G_INDEXED_ZEXTLOAD = 74 |
| 16642 | CEFBS_None, // G_STORE = 75 |
| 16643 | CEFBS_None, // G_INDEXED_STORE = 76 |
| 16644 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 77 |
| 16645 | CEFBS_None, // G_ATOMIC_CMPXCHG = 78 |
| 16646 | CEFBS_None, // G_ATOMICRMW_XCHG = 79 |
| 16647 | CEFBS_None, // G_ATOMICRMW_ADD = 80 |
| 16648 | CEFBS_None, // G_ATOMICRMW_SUB = 81 |
| 16649 | CEFBS_None, // G_ATOMICRMW_AND = 82 |
| 16650 | CEFBS_None, // G_ATOMICRMW_NAND = 83 |
| 16651 | CEFBS_None, // G_ATOMICRMW_OR = 84 |
| 16652 | CEFBS_None, // G_ATOMICRMW_XOR = 85 |
| 16653 | CEFBS_None, // G_ATOMICRMW_MAX = 86 |
| 16654 | CEFBS_None, // G_ATOMICRMW_MIN = 87 |
| 16655 | CEFBS_None, // G_ATOMICRMW_UMAX = 88 |
| 16656 | CEFBS_None, // G_ATOMICRMW_UMIN = 89 |
| 16657 | CEFBS_None, // G_ATOMICRMW_FADD = 90 |
| 16658 | CEFBS_None, // G_ATOMICRMW_FSUB = 91 |
| 16659 | CEFBS_None, // G_FENCE = 92 |
| 16660 | CEFBS_None, // G_BRCOND = 93 |
| 16661 | CEFBS_None, // G_BRINDIRECT = 94 |
| 16662 | CEFBS_None, // G_INTRINSIC = 95 |
| 16663 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 96 |
| 16664 | CEFBS_None, // G_ANYEXT = 97 |
| 16665 | CEFBS_None, // G_TRUNC = 98 |
| 16666 | CEFBS_None, // G_CONSTANT = 99 |
| 16667 | CEFBS_None, // G_FCONSTANT = 100 |
| 16668 | CEFBS_None, // G_VASTART = 101 |
| 16669 | CEFBS_None, // G_VAARG = 102 |
| 16670 | CEFBS_None, // G_SEXT = 103 |
| 16671 | CEFBS_None, // G_SEXT_INREG = 104 |
| 16672 | CEFBS_None, // G_ZEXT = 105 |
| 16673 | CEFBS_None, // G_SHL = 106 |
| 16674 | CEFBS_None, // G_LSHR = 107 |
| 16675 | CEFBS_None, // G_ASHR = 108 |
| 16676 | CEFBS_None, // G_FSHL = 109 |
| 16677 | CEFBS_None, // G_FSHR = 110 |
| 16678 | CEFBS_None, // G_ICMP = 111 |
| 16679 | CEFBS_None, // G_FCMP = 112 |
| 16680 | CEFBS_None, // G_SELECT = 113 |
| 16681 | CEFBS_None, // G_UADDO = 114 |
| 16682 | CEFBS_None, // G_UADDE = 115 |
| 16683 | CEFBS_None, // G_USUBO = 116 |
| 16684 | CEFBS_None, // G_USUBE = 117 |
| 16685 | CEFBS_None, // G_SADDO = 118 |
| 16686 | CEFBS_None, // G_SADDE = 119 |
| 16687 | CEFBS_None, // G_SSUBO = 120 |
| 16688 | CEFBS_None, // G_SSUBE = 121 |
| 16689 | CEFBS_None, // G_UMULO = 122 |
| 16690 | CEFBS_None, // G_SMULO = 123 |
| 16691 | CEFBS_None, // G_UMULH = 124 |
| 16692 | CEFBS_None, // G_SMULH = 125 |
| 16693 | CEFBS_None, // G_UADDSAT = 126 |
| 16694 | CEFBS_None, // G_SADDSAT = 127 |
| 16695 | CEFBS_None, // G_USUBSAT = 128 |
| 16696 | CEFBS_None, // G_SSUBSAT = 129 |
| 16697 | CEFBS_None, // G_USHLSAT = 130 |
| 16698 | CEFBS_None, // G_SSHLSAT = 131 |
| 16699 | CEFBS_None, // G_SMULFIX = 132 |
| 16700 | CEFBS_None, // G_UMULFIX = 133 |
| 16701 | CEFBS_None, // G_SMULFIXSAT = 134 |
| 16702 | CEFBS_None, // G_UMULFIXSAT = 135 |
| 16703 | CEFBS_None, // G_SDIVFIX = 136 |
| 16704 | CEFBS_None, // G_UDIVFIX = 137 |
| 16705 | CEFBS_None, // G_SDIVFIXSAT = 138 |
| 16706 | CEFBS_None, // G_UDIVFIXSAT = 139 |
| 16707 | CEFBS_None, // G_FADD = 140 |
| 16708 | CEFBS_None, // G_FSUB = 141 |
| 16709 | CEFBS_None, // G_FMUL = 142 |
| 16710 | CEFBS_None, // G_FMA = 143 |
| 16711 | CEFBS_None, // G_FMAD = 144 |
| 16712 | CEFBS_None, // G_FDIV = 145 |
| 16713 | CEFBS_None, // G_FREM = 146 |
| 16714 | CEFBS_None, // G_FPOW = 147 |
| 16715 | CEFBS_None, // G_FPOWI = 148 |
| 16716 | CEFBS_None, // G_FEXP = 149 |
| 16717 | CEFBS_None, // G_FEXP2 = 150 |
| 16718 | CEFBS_None, // G_FLOG = 151 |
| 16719 | CEFBS_None, // G_FLOG2 = 152 |
| 16720 | CEFBS_None, // G_FLOG10 = 153 |
| 16721 | CEFBS_None, // G_FNEG = 154 |
| 16722 | CEFBS_None, // G_FPEXT = 155 |
| 16723 | CEFBS_None, // G_FPTRUNC = 156 |
| 16724 | CEFBS_None, // G_FPTOSI = 157 |
| 16725 | CEFBS_None, // G_FPTOUI = 158 |
| 16726 | CEFBS_None, // G_SITOFP = 159 |
| 16727 | CEFBS_None, // G_UITOFP = 160 |
| 16728 | CEFBS_None, // G_FABS = 161 |
| 16729 | CEFBS_None, // G_FCOPYSIGN = 162 |
| 16730 | CEFBS_None, // G_FCANONICALIZE = 163 |
| 16731 | CEFBS_None, // G_FMINNUM = 164 |
| 16732 | CEFBS_None, // G_FMAXNUM = 165 |
| 16733 | CEFBS_None, // G_FMINNUM_IEEE = 166 |
| 16734 | CEFBS_None, // G_FMAXNUM_IEEE = 167 |
| 16735 | CEFBS_None, // G_FMINIMUM = 168 |
| 16736 | CEFBS_None, // G_FMAXIMUM = 169 |
| 16737 | CEFBS_None, // G_PTR_ADD = 170 |
| 16738 | CEFBS_None, // G_PTRMASK = 171 |
| 16739 | CEFBS_None, // G_SMIN = 172 |
| 16740 | CEFBS_None, // G_SMAX = 173 |
| 16741 | CEFBS_None, // G_UMIN = 174 |
| 16742 | CEFBS_None, // G_UMAX = 175 |
| 16743 | CEFBS_None, // G_ABS = 176 |
| 16744 | CEFBS_None, // G_BR = 177 |
| 16745 | CEFBS_None, // G_BRJT = 178 |
| 16746 | CEFBS_None, // G_INSERT_VECTOR_ELT = 179 |
| 16747 | CEFBS_None, // G_EXTRACT_VECTOR_ELT = 180 |
| 16748 | CEFBS_None, // G_SHUFFLE_VECTOR = 181 |
| 16749 | CEFBS_None, // G_CTTZ = 182 |
| 16750 | CEFBS_None, // G_CTTZ_ZERO_UNDEF = 183 |
| 16751 | CEFBS_None, // G_CTLZ = 184 |
| 16752 | CEFBS_None, // G_CTLZ_ZERO_UNDEF = 185 |
| 16753 | CEFBS_None, // G_CTPOP = 186 |
| 16754 | CEFBS_None, // G_BSWAP = 187 |
| 16755 | CEFBS_None, // G_BITREVERSE = 188 |
| 16756 | CEFBS_None, // G_FCEIL = 189 |
| 16757 | CEFBS_None, // G_FCOS = 190 |
| 16758 | CEFBS_None, // G_FSIN = 191 |
| 16759 | CEFBS_None, // G_FSQRT = 192 |
| 16760 | CEFBS_None, // G_FFLOOR = 193 |
| 16761 | CEFBS_None, // G_FRINT = 194 |
| 16762 | CEFBS_None, // G_FNEARBYINT = 195 |
| 16763 | CEFBS_None, // G_ADDRSPACE_CAST = 196 |
| 16764 | CEFBS_None, // G_BLOCK_ADDR = 197 |
| 16765 | CEFBS_None, // G_JUMP_TABLE = 198 |
| 16766 | CEFBS_None, // G_DYN_STACKALLOC = 199 |
| 16767 | CEFBS_None, // G_STRICT_FADD = 200 |
| 16768 | CEFBS_None, // G_STRICT_FSUB = 201 |
| 16769 | CEFBS_None, // G_STRICT_FMUL = 202 |
| 16770 | CEFBS_None, // G_STRICT_FDIV = 203 |
| 16771 | CEFBS_None, // G_STRICT_FREM = 204 |
| 16772 | CEFBS_None, // G_STRICT_FMA = 205 |
| 16773 | CEFBS_None, // G_STRICT_FSQRT = 206 |
| 16774 | CEFBS_None, // G_READ_REGISTER = 207 |
| 16775 | CEFBS_None, // G_WRITE_REGISTER = 208 |
| 16776 | CEFBS_None, // G_MEMCPY = 209 |
| 16777 | CEFBS_None, // G_MEMMOVE = 210 |
| 16778 | CEFBS_None, // G_MEMSET = 211 |
| 16779 | CEFBS_None, // G_VECREDUCE_SEQ_FADD = 212 |
| 16780 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 213 |
| 16781 | CEFBS_None, // G_VECREDUCE_FADD = 214 |
| 16782 | CEFBS_None, // G_VECREDUCE_FMUL = 215 |
| 16783 | CEFBS_None, // G_VECREDUCE_FMAX = 216 |
| 16784 | CEFBS_None, // G_VECREDUCE_FMIN = 217 |
| 16785 | CEFBS_None, // G_VECREDUCE_ADD = 218 |
| 16786 | CEFBS_None, // G_VECREDUCE_MUL = 219 |
| 16787 | CEFBS_None, // G_VECREDUCE_AND = 220 |
| 16788 | CEFBS_None, // G_VECREDUCE_OR = 221 |
| 16789 | CEFBS_None, // G_VECREDUCE_XOR = 222 |
| 16790 | CEFBS_None, // G_VECREDUCE_SMAX = 223 |
| 16791 | CEFBS_None, // G_VECREDUCE_SMIN = 224 |
| 16792 | CEFBS_None, // G_VECREDUCE_UMAX = 225 |
| 16793 | CEFBS_None, // G_VECREDUCE_UMIN = 226 |
| 16794 | CEFBS_None, // ADDSWrr = 227 |
| 16795 | CEFBS_None, // ADDSXrr = 228 |
| 16796 | CEFBS_None, // ADDWrr = 229 |
| 16797 | CEFBS_None, // ADDXrr = 230 |
| 16798 | CEFBS_HasSVE, // ADD_ZPZZ_UNDEF_B = 231 |
| 16799 | CEFBS_HasSVE, // ADD_ZPZZ_UNDEF_D = 232 |
| 16800 | CEFBS_HasSVE, // ADD_ZPZZ_UNDEF_H = 233 |
| 16801 | CEFBS_HasSVE, // ADD_ZPZZ_UNDEF_S = 234 |
| 16802 | CEFBS_HasSVE, // ADD_ZPZZ_ZERO_B = 235 |
| 16803 | CEFBS_HasSVE, // ADD_ZPZZ_ZERO_D = 236 |
| 16804 | CEFBS_HasSVE, // ADD_ZPZZ_ZERO_H = 237 |
| 16805 | CEFBS_HasSVE, // ADD_ZPZZ_ZERO_S = 238 |
| 16806 | CEFBS_None, // ADDlowTLS = 239 |
| 16807 | CEFBS_None, // ADJCALLSTACKDOWN = 240 |
| 16808 | CEFBS_None, // ADJCALLSTACKUP = 241 |
| 16809 | CEFBS_None, // AESIMCrrTied = 242 |
| 16810 | CEFBS_None, // AESMCrrTied = 243 |
| 16811 | CEFBS_None, // ANDSWrr = 244 |
| 16812 | CEFBS_None, // ANDSXrr = 245 |
| 16813 | CEFBS_None, // ANDWrr = 246 |
| 16814 | CEFBS_None, // ANDXrr = 247 |
| 16815 | CEFBS_HasSVE, // ASRD_ZPZI_ZERO_B = 248 |
| 16816 | CEFBS_HasSVE, // ASRD_ZPZI_ZERO_D = 249 |
| 16817 | CEFBS_HasSVE, // ASRD_ZPZI_ZERO_H = 250 |
| 16818 | CEFBS_HasSVE, // ASRD_ZPZI_ZERO_S = 251 |
| 16819 | CEFBS_HasSVE, // ASR_ZPZI_UNDEF_B = 252 |
| 16820 | CEFBS_HasSVE, // ASR_ZPZI_UNDEF_D = 253 |
| 16821 | CEFBS_HasSVE, // ASR_ZPZI_UNDEF_H = 254 |
| 16822 | CEFBS_HasSVE, // ASR_ZPZI_UNDEF_S = 255 |
| 16823 | CEFBS_HasSVE, // ASR_ZPZZ_UNDEF_B = 256 |
| 16824 | CEFBS_HasSVE, // ASR_ZPZZ_UNDEF_D = 257 |
| 16825 | CEFBS_HasSVE, // ASR_ZPZZ_UNDEF_H = 258 |
| 16826 | CEFBS_HasSVE, // ASR_ZPZZ_UNDEF_S = 259 |
| 16827 | CEFBS_HasSVE, // ASR_ZPZZ_ZERO_B = 260 |
| 16828 | CEFBS_HasSVE, // ASR_ZPZZ_ZERO_D = 261 |
| 16829 | CEFBS_HasSVE, // ASR_ZPZZ_ZERO_H = 262 |
| 16830 | CEFBS_HasSVE, // ASR_ZPZZ_ZERO_S = 263 |
| 16831 | CEFBS_None, // BICSWrr = 264 |
| 16832 | CEFBS_None, // BICSXrr = 265 |
| 16833 | CEFBS_None, // BICWrr = 266 |
| 16834 | CEFBS_None, // BICXrr = 267 |
| 16835 | CEFBS_None, // BLRNoIP = 268 |
| 16836 | CEFBS_None, // BLR_RVMARKER = 269 |
| 16837 | CEFBS_HasNEON, // BSPv16i8 = 270 |
| 16838 | CEFBS_HasNEON, // BSPv8i8 = 271 |
| 16839 | CEFBS_None, // CATCHRET = 272 |
| 16840 | CEFBS_None, // CLEANUPRET = 273 |
| 16841 | CEFBS_None, // CMP_SWAP_128 = 274 |
| 16842 | CEFBS_None, // CMP_SWAP_16 = 275 |
| 16843 | CEFBS_None, // CMP_SWAP_32 = 276 |
| 16844 | CEFBS_None, // CMP_SWAP_64 = 277 |
| 16845 | CEFBS_None, // CMP_SWAP_8 = 278 |
| 16846 | CEFBS_None, // CompilerBarrier = 279 |
| 16847 | CEFBS_None, // EMITBKEY = 280 |
| 16848 | CEFBS_None, // EONWrr = 281 |
| 16849 | CEFBS_None, // EONXrr = 282 |
| 16850 | CEFBS_None, // EORWrr = 283 |
| 16851 | CEFBS_None, // EORXrr = 284 |
| 16852 | CEFBS_None, // F128CSEL = 285 |
| 16853 | CEFBS_HasSVE, // FABD_ZPZZ_ZERO_D = 286 |
| 16854 | CEFBS_HasSVE, // FABD_ZPZZ_ZERO_H = 287 |
| 16855 | CEFBS_HasSVE, // FABD_ZPZZ_ZERO_S = 288 |
| 16856 | CEFBS_HasSVE, // FADD_ZPZZ_UNDEF_D = 289 |
| 16857 | CEFBS_HasSVE, // FADD_ZPZZ_UNDEF_H = 290 |
| 16858 | CEFBS_HasSVE, // FADD_ZPZZ_UNDEF_S = 291 |
| 16859 | CEFBS_HasSVE, // FADD_ZPZZ_ZERO_D = 292 |
| 16860 | CEFBS_HasSVE, // FADD_ZPZZ_ZERO_H = 293 |
| 16861 | CEFBS_HasSVE, // FADD_ZPZZ_ZERO_S = 294 |
| 16862 | CEFBS_HasSVE, // FDIVR_ZPZZ_ZERO_D = 295 |
| 16863 | CEFBS_HasSVE, // FDIVR_ZPZZ_ZERO_H = 296 |
| 16864 | CEFBS_HasSVE, // FDIVR_ZPZZ_ZERO_S = 297 |
| 16865 | CEFBS_HasSVE, // FDIV_ZPZZ_UNDEF_D = 298 |
| 16866 | CEFBS_HasSVE, // FDIV_ZPZZ_UNDEF_H = 299 |
| 16867 | CEFBS_HasSVE, // FDIV_ZPZZ_UNDEF_S = 300 |
| 16868 | CEFBS_HasSVE, // FDIV_ZPZZ_ZERO_D = 301 |
| 16869 | CEFBS_HasSVE, // FDIV_ZPZZ_ZERO_H = 302 |
| 16870 | CEFBS_HasSVE, // FDIV_ZPZZ_ZERO_S = 303 |
| 16871 | CEFBS_HasSVE, // FMAXNM_ZPZZ_UNDEF_D = 304 |
| 16872 | CEFBS_HasSVE, // FMAXNM_ZPZZ_UNDEF_H = 305 |
| 16873 | CEFBS_HasSVE, // FMAXNM_ZPZZ_UNDEF_S = 306 |
| 16874 | CEFBS_HasSVE, // FMAXNM_ZPZZ_ZERO_D = 307 |
| 16875 | CEFBS_HasSVE, // FMAXNM_ZPZZ_ZERO_H = 308 |
| 16876 | CEFBS_HasSVE, // FMAXNM_ZPZZ_ZERO_S = 309 |
| 16877 | CEFBS_HasSVE, // FMAX_ZPZZ_ZERO_D = 310 |
| 16878 | CEFBS_HasSVE, // FMAX_ZPZZ_ZERO_H = 311 |
| 16879 | CEFBS_HasSVE, // FMAX_ZPZZ_ZERO_S = 312 |
| 16880 | CEFBS_HasSVE, // FMINNM_ZPZZ_UNDEF_D = 313 |
| 16881 | CEFBS_HasSVE, // FMINNM_ZPZZ_UNDEF_H = 314 |
| 16882 | CEFBS_HasSVE, // FMINNM_ZPZZ_UNDEF_S = 315 |
| 16883 | CEFBS_HasSVE, // FMINNM_ZPZZ_ZERO_D = 316 |
| 16884 | CEFBS_HasSVE, // FMINNM_ZPZZ_ZERO_H = 317 |
| 16885 | CEFBS_HasSVE, // FMINNM_ZPZZ_ZERO_S = 318 |
| 16886 | CEFBS_HasSVE, // FMIN_ZPZZ_ZERO_D = 319 |
| 16887 | CEFBS_HasSVE, // FMIN_ZPZZ_ZERO_H = 320 |
| 16888 | CEFBS_HasSVE, // FMIN_ZPZZ_ZERO_S = 321 |
| 16889 | CEFBS_None, // FMOVD0 = 322 |
| 16890 | CEFBS_HasFullFP16, // FMOVH0 = 323 |
| 16891 | CEFBS_None, // FMOVS0 = 324 |
| 16892 | CEFBS_HasSVE, // FMULX_ZPZZ_ZERO_D = 325 |
| 16893 | CEFBS_HasSVE, // FMULX_ZPZZ_ZERO_H = 326 |
| 16894 | CEFBS_HasSVE, // FMULX_ZPZZ_ZERO_S = 327 |
| 16895 | CEFBS_HasSVE, // FMUL_ZPZZ_UNDEF_D = 328 |
| 16896 | CEFBS_HasSVE, // FMUL_ZPZZ_UNDEF_H = 329 |
| 16897 | CEFBS_HasSVE, // FMUL_ZPZZ_UNDEF_S = 330 |
| 16898 | CEFBS_HasSVE, // FMUL_ZPZZ_ZERO_D = 331 |
| 16899 | CEFBS_HasSVE, // FMUL_ZPZZ_ZERO_H = 332 |
| 16900 | CEFBS_HasSVE, // FMUL_ZPZZ_ZERO_S = 333 |
| 16901 | CEFBS_HasSVE, // FSUBR_ZPZZ_ZERO_D = 334 |
| 16902 | CEFBS_HasSVE, // FSUBR_ZPZZ_ZERO_H = 335 |
| 16903 | CEFBS_HasSVE, // FSUBR_ZPZZ_ZERO_S = 336 |
| 16904 | CEFBS_HasSVE, // FSUB_ZPZZ_UNDEF_D = 337 |
| 16905 | CEFBS_HasSVE, // FSUB_ZPZZ_UNDEF_H = 338 |
| 16906 | CEFBS_HasSVE, // FSUB_ZPZZ_UNDEF_S = 339 |
| 16907 | CEFBS_HasSVE, // FSUB_ZPZZ_ZERO_D = 340 |
| 16908 | CEFBS_HasSVE, // FSUB_ZPZZ_ZERO_H = 341 |
| 16909 | CEFBS_HasSVE, // FSUB_ZPZZ_ZERO_S = 342 |
| 16910 | CEFBS_HasSVE, // GLD1B_D = 343 |
| 16911 | CEFBS_HasSVE, // GLD1B_D_IMM = 344 |
| 16912 | CEFBS_HasSVE, // GLD1B_D_SXTW = 345 |
| 16913 | CEFBS_HasSVE, // GLD1B_D_UXTW = 346 |
| 16914 | CEFBS_HasSVE, // GLD1B_S_IMM = 347 |
| 16915 | CEFBS_HasSVE, // GLD1B_S_SXTW = 348 |
| 16916 | CEFBS_HasSVE, // GLD1B_S_UXTW = 349 |
| 16917 | CEFBS_HasSVE, // GLD1D = 350 |
| 16918 | CEFBS_HasSVE, // GLD1D_IMM = 351 |
| 16919 | CEFBS_HasSVE, // GLD1D_SCALED = 352 |
| 16920 | CEFBS_HasSVE, // GLD1D_SXTW = 353 |
| 16921 | CEFBS_HasSVE, // GLD1D_SXTW_SCALED = 354 |
| 16922 | CEFBS_HasSVE, // GLD1D_UXTW = 355 |
| 16923 | CEFBS_HasSVE, // GLD1D_UXTW_SCALED = 356 |
| 16924 | CEFBS_HasSVE, // GLD1H_D = 357 |
| 16925 | CEFBS_HasSVE, // GLD1H_D_IMM = 358 |
| 16926 | CEFBS_HasSVE, // GLD1H_D_SCALED = 359 |
| 16927 | CEFBS_HasSVE, // GLD1H_D_SXTW = 360 |
| 16928 | CEFBS_HasSVE, // GLD1H_D_SXTW_SCALED = 361 |
| 16929 | CEFBS_HasSVE, // GLD1H_D_UXTW = 362 |
| 16930 | CEFBS_HasSVE, // GLD1H_D_UXTW_SCALED = 363 |
| 16931 | CEFBS_HasSVE, // GLD1H_S_IMM = 364 |
| 16932 | CEFBS_HasSVE, // GLD1H_S_SXTW = 365 |
| 16933 | CEFBS_HasSVE, // GLD1H_S_SXTW_SCALED = 366 |
| 16934 | CEFBS_HasSVE, // GLD1H_S_UXTW = 367 |
| 16935 | CEFBS_HasSVE, // GLD1H_S_UXTW_SCALED = 368 |
| 16936 | CEFBS_HasSVE, // GLD1SB_D = 369 |
| 16937 | CEFBS_HasSVE, // GLD1SB_D_IMM = 370 |
| 16938 | CEFBS_HasSVE, // GLD1SB_D_SXTW = 371 |
| 16939 | CEFBS_HasSVE, // GLD1SB_D_UXTW = 372 |
| 16940 | CEFBS_HasSVE, // GLD1SB_S_IMM = 373 |
| 16941 | CEFBS_HasSVE, // GLD1SB_S_SXTW = 374 |
| 16942 | CEFBS_HasSVE, // GLD1SB_S_UXTW = 375 |
| 16943 | CEFBS_HasSVE, // GLD1SH_D = 376 |
| 16944 | CEFBS_HasSVE, // GLD1SH_D_IMM = 377 |
| 16945 | CEFBS_HasSVE, // GLD1SH_D_SCALED = 378 |
| 16946 | CEFBS_HasSVE, // GLD1SH_D_SXTW = 379 |
| 16947 | CEFBS_HasSVE, // GLD1SH_D_SXTW_SCALED = 380 |
| 16948 | CEFBS_HasSVE, // GLD1SH_D_UXTW = 381 |
| 16949 | CEFBS_HasSVE, // GLD1SH_D_UXTW_SCALED = 382 |
| 16950 | CEFBS_HasSVE, // GLD1SH_S_IMM = 383 |
| 16951 | CEFBS_HasSVE, // GLD1SH_S_SXTW = 384 |
| 16952 | CEFBS_HasSVE, // GLD1SH_S_SXTW_SCALED = 385 |
| 16953 | CEFBS_HasSVE, // GLD1SH_S_UXTW = 386 |
| 16954 | CEFBS_HasSVE, // GLD1SH_S_UXTW_SCALED = 387 |
| 16955 | CEFBS_HasSVE, // GLD1SW_D = 388 |
| 16956 | CEFBS_HasSVE, // GLD1SW_D_IMM = 389 |
| 16957 | CEFBS_HasSVE, // GLD1SW_D_SCALED = 390 |
| 16958 | CEFBS_HasSVE, // GLD1SW_D_SXTW = 391 |
| 16959 | CEFBS_HasSVE, // GLD1SW_D_SXTW_SCALED = 392 |
| 16960 | CEFBS_HasSVE, // GLD1SW_D_UXTW = 393 |
| 16961 | CEFBS_HasSVE, // GLD1SW_D_UXTW_SCALED = 394 |
| 16962 | CEFBS_HasSVE, // GLD1W_D = 395 |
| 16963 | CEFBS_HasSVE, // GLD1W_D_IMM = 396 |
| 16964 | CEFBS_HasSVE, // GLD1W_D_SCALED = 397 |
| 16965 | CEFBS_HasSVE, // GLD1W_D_SXTW = 398 |
| 16966 | CEFBS_HasSVE, // GLD1W_D_SXTW_SCALED = 399 |
| 16967 | CEFBS_HasSVE, // GLD1W_D_UXTW = 400 |
| 16968 | CEFBS_HasSVE, // GLD1W_D_UXTW_SCALED = 401 |
| 16969 | CEFBS_HasSVE, // GLD1W_IMM = 402 |
| 16970 | CEFBS_HasSVE, // GLD1W_SXTW = 403 |
| 16971 | CEFBS_HasSVE, // GLD1W_SXTW_SCALED = 404 |
| 16972 | CEFBS_HasSVE, // GLD1W_UXTW = 405 |
| 16973 | CEFBS_HasSVE, // GLD1W_UXTW_SCALED = 406 |
| 16974 | CEFBS_HasSVE, // GLDFF1B_D = 407 |
| 16975 | CEFBS_HasSVE, // GLDFF1B_D_IMM = 408 |
| 16976 | CEFBS_HasSVE, // GLDFF1B_D_SXTW = 409 |
| 16977 | CEFBS_HasSVE, // GLDFF1B_D_UXTW = 410 |
| 16978 | CEFBS_HasSVE, // GLDFF1B_S_IMM = 411 |
| 16979 | CEFBS_HasSVE, // GLDFF1B_S_SXTW = 412 |
| 16980 | CEFBS_HasSVE, // GLDFF1B_S_UXTW = 413 |
| 16981 | CEFBS_HasSVE, // GLDFF1D = 414 |
| 16982 | CEFBS_HasSVE, // GLDFF1D_IMM = 415 |
| 16983 | CEFBS_HasSVE, // GLDFF1D_SCALED = 416 |
| 16984 | CEFBS_HasSVE, // GLDFF1D_SXTW = 417 |
| 16985 | CEFBS_HasSVE, // GLDFF1D_SXTW_SCALED = 418 |
| 16986 | CEFBS_HasSVE, // GLDFF1D_UXTW = 419 |
| 16987 | CEFBS_HasSVE, // GLDFF1D_UXTW_SCALED = 420 |
| 16988 | CEFBS_HasSVE, // GLDFF1H_D = 421 |
| 16989 | CEFBS_HasSVE, // GLDFF1H_D_IMM = 422 |
| 16990 | CEFBS_HasSVE, // GLDFF1H_D_SCALED = 423 |
| 16991 | CEFBS_HasSVE, // GLDFF1H_D_SXTW = 424 |
| 16992 | CEFBS_HasSVE, // GLDFF1H_D_SXTW_SCALED = 425 |
| 16993 | CEFBS_HasSVE, // GLDFF1H_D_UXTW = 426 |
| 16994 | CEFBS_HasSVE, // GLDFF1H_D_UXTW_SCALED = 427 |
| 16995 | CEFBS_HasSVE, // GLDFF1H_S_IMM = 428 |
| 16996 | CEFBS_HasSVE, // GLDFF1H_S_SXTW = 429 |
| 16997 | CEFBS_HasSVE, // GLDFF1H_S_SXTW_SCALED = 430 |
| 16998 | CEFBS_HasSVE, // GLDFF1H_S_UXTW = 431 |
| 16999 | CEFBS_HasSVE, // GLDFF1H_S_UXTW_SCALED = 432 |
| 17000 | CEFBS_HasSVE, // GLDFF1SB_D = 433 |
| 17001 | CEFBS_HasSVE, // GLDFF1SB_D_IMM = 434 |
| 17002 | CEFBS_HasSVE, // GLDFF1SB_D_SXTW = 435 |
| 17003 | CEFBS_HasSVE, // GLDFF1SB_D_UXTW = 436 |
| 17004 | CEFBS_HasSVE, // GLDFF1SB_S_IMM = 437 |
| 17005 | CEFBS_HasSVE, // GLDFF1SB_S_SXTW = 438 |
| 17006 | CEFBS_HasSVE, // GLDFF1SB_S_UXTW = 439 |
| 17007 | CEFBS_HasSVE, // GLDFF1SH_D = 440 |
| 17008 | CEFBS_HasSVE, // GLDFF1SH_D_IMM = 441 |
| 17009 | CEFBS_HasSVE, // GLDFF1SH_D_SCALED = 442 |
| 17010 | CEFBS_HasSVE, // GLDFF1SH_D_SXTW = 443 |
| 17011 | CEFBS_HasSVE, // GLDFF1SH_D_SXTW_SCALED = 444 |
| 17012 | CEFBS_HasSVE, // GLDFF1SH_D_UXTW = 445 |
| 17013 | CEFBS_HasSVE, // GLDFF1SH_D_UXTW_SCALED = 446 |
| 17014 | CEFBS_HasSVE, // GLDFF1SH_S_IMM = 447 |
| 17015 | CEFBS_HasSVE, // GLDFF1SH_S_SXTW = 448 |
| 17016 | CEFBS_HasSVE, // GLDFF1SH_S_SXTW_SCALED = 449 |
| 17017 | CEFBS_HasSVE, // GLDFF1SH_S_UXTW = 450 |
| 17018 | CEFBS_HasSVE, // GLDFF1SH_S_UXTW_SCALED = 451 |
| 17019 | CEFBS_HasSVE, // GLDFF1SW_D = 452 |
| 17020 | CEFBS_HasSVE, // GLDFF1SW_D_IMM = 453 |
| 17021 | CEFBS_HasSVE, // GLDFF1SW_D_SCALED = 454 |
| 17022 | CEFBS_HasSVE, // GLDFF1SW_D_SXTW = 455 |
| 17023 | CEFBS_HasSVE, // GLDFF1SW_D_SXTW_SCALED = 456 |
| 17024 | CEFBS_HasSVE, // GLDFF1SW_D_UXTW = 457 |
| 17025 | CEFBS_HasSVE, // GLDFF1SW_D_UXTW_SCALED = 458 |
| 17026 | CEFBS_HasSVE, // GLDFF1W_D = 459 |
| 17027 | CEFBS_HasSVE, // GLDFF1W_D_IMM = 460 |
| 17028 | CEFBS_HasSVE, // GLDFF1W_D_SCALED = 461 |
| 17029 | CEFBS_HasSVE, // GLDFF1W_D_SXTW = 462 |
| 17030 | CEFBS_HasSVE, // GLDFF1W_D_SXTW_SCALED = 463 |
| 17031 | CEFBS_HasSVE, // GLDFF1W_D_UXTW = 464 |
| 17032 | CEFBS_HasSVE, // GLDFF1W_D_UXTW_SCALED = 465 |
| 17033 | CEFBS_HasSVE, // GLDFF1W_IMM = 466 |
| 17034 | CEFBS_HasSVE, // GLDFF1W_SXTW = 467 |
| 17035 | CEFBS_HasSVE, // GLDFF1W_SXTW_SCALED = 468 |
| 17036 | CEFBS_HasSVE, // GLDFF1W_UXTW = 469 |
| 17037 | CEFBS_HasSVE, // GLDFF1W_UXTW_SCALED = 470 |
| 17038 | CEFBS_None, // G_ADD_LOW = 471 |
| 17039 | CEFBS_None, // G_DUP = 472 |
| 17040 | CEFBS_None, // G_DUPLANE16 = 473 |
| 17041 | CEFBS_None, // G_DUPLANE32 = 474 |
| 17042 | CEFBS_None, // G_DUPLANE64 = 475 |
| 17043 | CEFBS_None, // G_DUPLANE8 = 476 |
| 17044 | CEFBS_None, // G_EXT = 477 |
| 17045 | CEFBS_None, // G_REV16 = 478 |
| 17046 | CEFBS_None, // G_REV32 = 479 |
| 17047 | CEFBS_None, // G_REV64 = 480 |
| 17048 | CEFBS_None, // G_SITOF = 481 |
| 17049 | CEFBS_None, // G_TRN1 = 482 |
| 17050 | CEFBS_None, // G_TRN2 = 483 |
| 17051 | CEFBS_None, // G_UITOF = 484 |
| 17052 | CEFBS_None, // G_UZP1 = 485 |
| 17053 | CEFBS_None, // G_UZP2 = 486 |
| 17054 | CEFBS_None, // G_VASHR = 487 |
| 17055 | CEFBS_None, // G_VLSHR = 488 |
| 17056 | CEFBS_None, // G_ZIP1 = 489 |
| 17057 | CEFBS_None, // G_ZIP2 = 490 |
| 17058 | CEFBS_None, // HWASAN_CHECK_MEMACCESS = 491 |
| 17059 | CEFBS_None, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES = 492 |
| 17060 | CEFBS_HasMTE, // IRGstack = 493 |
| 17061 | CEFBS_None, // JumpTableDest16 = 494 |
| 17062 | CEFBS_None, // JumpTableDest32 = 495 |
| 17063 | CEFBS_None, // JumpTableDest8 = 496 |
| 17064 | CEFBS_HasSVE, // LD1B_D_IMM = 497 |
| 17065 | CEFBS_HasSVE, // LD1B_H_IMM = 498 |
| 17066 | CEFBS_HasSVE, // LD1B_IMM = 499 |
| 17067 | CEFBS_HasSVE, // LD1B_S_IMM = 500 |
| 17068 | CEFBS_HasSVE, // LD1D_IMM = 501 |
| 17069 | CEFBS_HasSVE, // LD1H_D_IMM = 502 |
| 17070 | CEFBS_HasSVE, // LD1H_IMM = 503 |
| 17071 | CEFBS_HasSVE, // LD1H_S_IMM = 504 |
| 17072 | CEFBS_HasSVE, // LD1SB_D_IMM = 505 |
| 17073 | CEFBS_HasSVE, // LD1SB_H_IMM = 506 |
| 17074 | CEFBS_HasSVE, // LD1SB_S_IMM = 507 |
| 17075 | CEFBS_HasSVE, // LD1SH_D_IMM = 508 |
| 17076 | CEFBS_HasSVE, // LD1SH_S_IMM = 509 |
| 17077 | CEFBS_HasSVE, // LD1SW_D_IMM = 510 |
| 17078 | CEFBS_HasSVE, // LD1W_D_IMM = 511 |
| 17079 | CEFBS_HasSVE, // LD1W_IMM = 512 |
| 17080 | CEFBS_HasSVE, // LDFF1B = 513 |
| 17081 | CEFBS_HasSVE, // LDFF1B_D = 514 |
| 17082 | CEFBS_HasSVE, // LDFF1B_H = 515 |
| 17083 | CEFBS_HasSVE, // LDFF1B_S = 516 |
| 17084 | CEFBS_HasSVE, // LDFF1D = 517 |
| 17085 | CEFBS_HasSVE, // LDFF1H = 518 |
| 17086 | CEFBS_HasSVE, // LDFF1H_D = 519 |
| 17087 | CEFBS_HasSVE, // LDFF1H_S = 520 |
| 17088 | CEFBS_HasSVE, // LDFF1SB_D = 521 |
| 17089 | CEFBS_HasSVE, // LDFF1SB_H = 522 |
| 17090 | CEFBS_HasSVE, // LDFF1SB_S = 523 |
| 17091 | CEFBS_HasSVE, // LDFF1SH_D = 524 |
| 17092 | CEFBS_HasSVE, // LDFF1SH_S = 525 |
| 17093 | CEFBS_HasSVE, // LDFF1SW_D = 526 |
| 17094 | CEFBS_HasSVE, // LDFF1W = 527 |
| 17095 | CEFBS_HasSVE, // LDFF1W_D = 528 |
| 17096 | CEFBS_HasSVE, // LDNF1B_D_IMM = 529 |
| 17097 | CEFBS_HasSVE, // LDNF1B_H_IMM = 530 |
| 17098 | CEFBS_HasSVE, // LDNF1B_IMM = 531 |
| 17099 | CEFBS_HasSVE, // LDNF1B_S_IMM = 532 |
| 17100 | CEFBS_HasSVE, // LDNF1D_IMM = 533 |
| 17101 | CEFBS_HasSVE, // LDNF1H_D_IMM = 534 |
| 17102 | CEFBS_HasSVE, // LDNF1H_IMM = 535 |
| 17103 | CEFBS_HasSVE, // LDNF1H_S_IMM = 536 |
| 17104 | CEFBS_HasSVE, // LDNF1SB_D_IMM = 537 |
| 17105 | CEFBS_HasSVE, // LDNF1SB_H_IMM = 538 |
| 17106 | CEFBS_HasSVE, // LDNF1SB_S_IMM = 539 |
| 17107 | CEFBS_HasSVE, // LDNF1SH_D_IMM = 540 |
| 17108 | CEFBS_HasSVE, // LDNF1SH_S_IMM = 541 |
| 17109 | CEFBS_HasSVE, // LDNF1SW_D_IMM = 542 |
| 17110 | CEFBS_HasSVE, // LDNF1W_D_IMM = 543 |
| 17111 | CEFBS_HasSVE, // LDNF1W_IMM = 544 |
| 17112 | CEFBS_HasSVE, // LDR_ZZXI = 545 |
| 17113 | CEFBS_HasSVE, // LDR_ZZZXI = 546 |
| 17114 | CEFBS_HasSVE, // LDR_ZZZZXI = 547 |
| 17115 | CEFBS_None, // LOADgot = 548 |
| 17116 | CEFBS_HasSVE, // LSL_ZPZI_UNDEF_B = 549 |
| 17117 | CEFBS_HasSVE, // LSL_ZPZI_UNDEF_D = 550 |
| 17118 | CEFBS_HasSVE, // LSL_ZPZI_UNDEF_H = 551 |
| 17119 | CEFBS_HasSVE, // LSL_ZPZI_UNDEF_S = 552 |
| 17120 | CEFBS_HasSVE, // LSL_ZPZZ_UNDEF_B = 553 |
| 17121 | CEFBS_HasSVE, // LSL_ZPZZ_UNDEF_D = 554 |
| 17122 | CEFBS_HasSVE, // LSL_ZPZZ_UNDEF_H = 555 |
| 17123 | CEFBS_HasSVE, // LSL_ZPZZ_UNDEF_S = 556 |
| 17124 | CEFBS_HasSVE, // LSL_ZPZZ_ZERO_B = 557 |
| 17125 | CEFBS_HasSVE, // LSL_ZPZZ_ZERO_D = 558 |
| 17126 | CEFBS_HasSVE, // LSL_ZPZZ_ZERO_H = 559 |
| 17127 | CEFBS_HasSVE, // LSL_ZPZZ_ZERO_S = 560 |
| 17128 | CEFBS_HasSVE, // LSR_ZPZI_UNDEF_B = 561 |
| 17129 | CEFBS_HasSVE, // LSR_ZPZI_UNDEF_D = 562 |
| 17130 | CEFBS_HasSVE, // LSR_ZPZI_UNDEF_H = 563 |
| 17131 | CEFBS_HasSVE, // LSR_ZPZI_UNDEF_S = 564 |
| 17132 | CEFBS_HasSVE, // LSR_ZPZZ_UNDEF_B = 565 |
| 17133 | CEFBS_HasSVE, // LSR_ZPZZ_UNDEF_D = 566 |
| 17134 | CEFBS_HasSVE, // LSR_ZPZZ_UNDEF_H = 567 |
| 17135 | CEFBS_HasSVE, // LSR_ZPZZ_UNDEF_S = 568 |
| 17136 | CEFBS_HasSVE, // LSR_ZPZZ_ZERO_B = 569 |
| 17137 | CEFBS_HasSVE, // LSR_ZPZZ_ZERO_D = 570 |
| 17138 | CEFBS_HasSVE, // LSR_ZPZZ_ZERO_H = 571 |
| 17139 | CEFBS_HasSVE, // LSR_ZPZZ_ZERO_S = 572 |
| 17140 | CEFBS_None, // MOVMCSym = 573 |
| 17141 | CEFBS_None, // MOVaddr = 574 |
| 17142 | CEFBS_None, // MOVaddrBA = 575 |
| 17143 | CEFBS_None, // MOVaddrCP = 576 |
| 17144 | CEFBS_None, // MOVaddrEXT = 577 |
| 17145 | CEFBS_None, // MOVaddrJT = 578 |
| 17146 | CEFBS_None, // MOVaddrTLS = 579 |
| 17147 | CEFBS_None, // MOVbaseTLS = 580 |
| 17148 | CEFBS_None, // MOVi32imm = 581 |
| 17149 | CEFBS_None, // MOVi64imm = 582 |
| 17150 | CEFBS_HasSVE, // MUL_ZPZZ_UNDEF_B = 583 |
| 17151 | CEFBS_HasSVE, // MUL_ZPZZ_UNDEF_D = 584 |
| 17152 | CEFBS_HasSVE, // MUL_ZPZZ_UNDEF_H = 585 |
| 17153 | CEFBS_HasSVE, // MUL_ZPZZ_UNDEF_S = 586 |
| 17154 | CEFBS_None, // ORNWrr = 587 |
| 17155 | CEFBS_None, // ORNXrr = 588 |
| 17156 | CEFBS_None, // ORRWrr = 589 |
| 17157 | CEFBS_None, // ORRXrr = 590 |
| 17158 | CEFBS_HasSVE, // RDFFR_P = 591 |
| 17159 | CEFBS_HasSVE, // RDFFR_PPz = 592 |
| 17160 | CEFBS_None, // RET_ReallyLR = 593 |
| 17161 | CEFBS_HasSVE, // SDIV_ZPZZ_UNDEF_D = 594 |
| 17162 | CEFBS_HasSVE, // SDIV_ZPZZ_UNDEF_S = 595 |
| 17163 | CEFBS_None, // SEH_AddFP = 596 |
| 17164 | CEFBS_None, // SEH_EpilogEnd = 597 |
| 17165 | CEFBS_None, // SEH_EpilogStart = 598 |
| 17166 | CEFBS_None, // SEH_Nop = 599 |
| 17167 | CEFBS_None, // SEH_PrologEnd = 600 |
| 17168 | CEFBS_None, // SEH_SaveFPLR = 601 |
| 17169 | CEFBS_None, // SEH_SaveFPLR_X = 602 |
| 17170 | CEFBS_None, // SEH_SaveFReg = 603 |
| 17171 | CEFBS_None, // SEH_SaveFRegP = 604 |
| 17172 | CEFBS_None, // SEH_SaveFRegP_X = 605 |
| 17173 | CEFBS_None, // SEH_SaveFReg_X = 606 |
| 17174 | CEFBS_None, // SEH_SaveReg = 607 |
| 17175 | CEFBS_None, // SEH_SaveRegP = 608 |
| 17176 | CEFBS_None, // SEH_SaveRegP_X = 609 |
| 17177 | CEFBS_None, // SEH_SaveReg_X = 610 |
| 17178 | CEFBS_None, // SEH_SetFP = 611 |
| 17179 | CEFBS_None, // SEH_StackAlloc = 612 |
| 17180 | CEFBS_HasSVE, // SMAX_ZPZZ_UNDEF_B = 613 |
| 17181 | CEFBS_HasSVE, // SMAX_ZPZZ_UNDEF_D = 614 |
| 17182 | CEFBS_HasSVE, // SMAX_ZPZZ_UNDEF_H = 615 |
| 17183 | CEFBS_HasSVE, // SMAX_ZPZZ_UNDEF_S = 616 |
| 17184 | CEFBS_HasSVE, // SMIN_ZPZZ_UNDEF_B = 617 |
| 17185 | CEFBS_HasSVE, // SMIN_ZPZZ_UNDEF_D = 618 |
| 17186 | CEFBS_HasSVE, // SMIN_ZPZZ_UNDEF_H = 619 |
| 17187 | CEFBS_HasSVE, // SMIN_ZPZZ_UNDEF_S = 620 |
| 17188 | CEFBS_None, // SPACE = 621 |
| 17189 | CEFBS_HasSVE2, // SQSHLU_ZPZI_ZERO_B = 622 |
| 17190 | CEFBS_HasSVE2, // SQSHLU_ZPZI_ZERO_D = 623 |
| 17191 | CEFBS_HasSVE2, // SQSHLU_ZPZI_ZERO_H = 624 |
| 17192 | CEFBS_HasSVE2, // SQSHLU_ZPZI_ZERO_S = 625 |
| 17193 | CEFBS_HasSVE2, // SQSHL_ZPZI_ZERO_B = 626 |
| 17194 | CEFBS_HasSVE2, // SQSHL_ZPZI_ZERO_D = 627 |
| 17195 | CEFBS_HasSVE2, // SQSHL_ZPZI_ZERO_H = 628 |
| 17196 | CEFBS_HasSVE2, // SQSHL_ZPZI_ZERO_S = 629 |
| 17197 | CEFBS_HasSVE2, // SRSHR_ZPZI_ZERO_B = 630 |
| 17198 | CEFBS_HasSVE2, // SRSHR_ZPZI_ZERO_D = 631 |
| 17199 | CEFBS_HasSVE2, // SRSHR_ZPZI_ZERO_H = 632 |
| 17200 | CEFBS_HasSVE2, // SRSHR_ZPZI_ZERO_S = 633 |
| 17201 | CEFBS_HasMTE, // STGloop = 634 |
| 17202 | CEFBS_HasMTE, // STGloop_wback = 635 |
| 17203 | CEFBS_HasSVE, // STR_ZZXI = 636 |
| 17204 | CEFBS_HasSVE, // STR_ZZZXI = 637 |
| 17205 | CEFBS_HasSVE, // STR_ZZZZXI = 638 |
| 17206 | CEFBS_HasMTE, // STZGloop = 639 |
| 17207 | CEFBS_HasMTE, // STZGloop_wback = 640 |
| 17208 | CEFBS_HasSVE, // SUBR_ZPZZ_ZERO_B = 641 |
| 17209 | CEFBS_HasSVE, // SUBR_ZPZZ_ZERO_D = 642 |
| 17210 | CEFBS_HasSVE, // SUBR_ZPZZ_ZERO_H = 643 |
| 17211 | CEFBS_HasSVE, // SUBR_ZPZZ_ZERO_S = 644 |
| 17212 | CEFBS_None, // SUBSWrr = 645 |
| 17213 | CEFBS_None, // SUBSXrr = 646 |
| 17214 | CEFBS_None, // SUBWrr = 647 |
| 17215 | CEFBS_None, // SUBXrr = 648 |
| 17216 | CEFBS_HasSVE, // SUB_ZPZZ_UNDEF_B = 649 |
| 17217 | CEFBS_HasSVE, // SUB_ZPZZ_UNDEF_D = 650 |
| 17218 | CEFBS_HasSVE, // SUB_ZPZZ_UNDEF_H = 651 |
| 17219 | CEFBS_HasSVE, // SUB_ZPZZ_UNDEF_S = 652 |
| 17220 | CEFBS_HasSVE, // SUB_ZPZZ_ZERO_B = 653 |
| 17221 | CEFBS_HasSVE, // SUB_ZPZZ_ZERO_D = 654 |
| 17222 | CEFBS_HasSVE, // SUB_ZPZZ_ZERO_H = 655 |
| 17223 | CEFBS_HasSVE, // SUB_ZPZZ_ZERO_S = 656 |
| 17224 | CEFBS_None, // SpeculationBarrierISBDSBEndBB = 657 |
| 17225 | CEFBS_None, // SpeculationBarrierSBEndBB = 658 |
| 17226 | CEFBS_None, // SpeculationSafeValueW = 659 |
| 17227 | CEFBS_None, // SpeculationSafeValueX = 660 |
| 17228 | CEFBS_HasMTE, // TAGPstack = 661 |
| 17229 | CEFBS_None, // TCRETURNdi = 662 |
| 17230 | CEFBS_None, // TCRETURNri = 663 |
| 17231 | CEFBS_None, // TCRETURNriALL = 664 |
| 17232 | CEFBS_None, // TCRETURNriBTI = 665 |
| 17233 | CEFBS_None, // TLSDESCCALL = 666 |
| 17234 | CEFBS_None, // TLSDESC_CALLSEQ = 667 |
| 17235 | CEFBS_HasSVE, // UDIV_ZPZZ_UNDEF_D = 668 |
| 17236 | CEFBS_HasSVE, // UDIV_ZPZZ_UNDEF_S = 669 |
| 17237 | CEFBS_HasSVE, // UMAX_ZPZZ_UNDEF_B = 670 |
| 17238 | CEFBS_HasSVE, // UMAX_ZPZZ_UNDEF_D = 671 |
| 17239 | CEFBS_HasSVE, // UMAX_ZPZZ_UNDEF_H = 672 |
| 17240 | CEFBS_HasSVE, // UMAX_ZPZZ_UNDEF_S = 673 |
| 17241 | CEFBS_HasSVE, // UMIN_ZPZZ_UNDEF_B = 674 |
| 17242 | CEFBS_HasSVE, // UMIN_ZPZZ_UNDEF_D = 675 |
| 17243 | CEFBS_HasSVE, // UMIN_ZPZZ_UNDEF_H = 676 |
| 17244 | CEFBS_HasSVE, // UMIN_ZPZZ_UNDEF_S = 677 |
| 17245 | CEFBS_HasSVE2, // UQSHL_ZPZI_ZERO_B = 678 |
| 17246 | CEFBS_HasSVE2, // UQSHL_ZPZI_ZERO_D = 679 |
| 17247 | CEFBS_HasSVE2, // UQSHL_ZPZI_ZERO_H = 680 |
| 17248 | CEFBS_HasSVE2, // UQSHL_ZPZI_ZERO_S = 681 |
| 17249 | CEFBS_HasSVE2, // URSHR_ZPZI_ZERO_B = 682 |
| 17250 | CEFBS_HasSVE2, // URSHR_ZPZI_ZERO_D = 683 |
| 17251 | CEFBS_HasSVE2, // URSHR_ZPZI_ZERO_H = 684 |
| 17252 | CEFBS_HasSVE2, // URSHR_ZPZI_ZERO_S = 685 |
| 17253 | CEFBS_HasSVE, // ABS_ZPmZ_B = 686 |
| 17254 | CEFBS_HasSVE, // ABS_ZPmZ_D = 687 |
| 17255 | CEFBS_HasSVE, // ABS_ZPmZ_H = 688 |
| 17256 | CEFBS_HasSVE, // ABS_ZPmZ_S = 689 |
| 17257 | CEFBS_HasNEON, // ABSv16i8 = 690 |
| 17258 | CEFBS_HasNEON, // ABSv1i64 = 691 |
| 17259 | CEFBS_HasNEON, // ABSv2i32 = 692 |
| 17260 | CEFBS_HasNEON, // ABSv2i64 = 693 |
| 17261 | CEFBS_HasNEON, // ABSv4i16 = 694 |
| 17262 | CEFBS_HasNEON, // ABSv4i32 = 695 |
| 17263 | CEFBS_HasNEON, // ABSv8i16 = 696 |
| 17264 | CEFBS_HasNEON, // ABSv8i8 = 697 |
| 17265 | CEFBS_HasSVE2, // ADCLB_ZZZ_D = 698 |
| 17266 | CEFBS_HasSVE2, // ADCLB_ZZZ_S = 699 |
| 17267 | CEFBS_HasSVE2, // ADCLT_ZZZ_D = 700 |
| 17268 | CEFBS_HasSVE2, // ADCLT_ZZZ_S = 701 |
| 17269 | CEFBS_None, // ADCSWr = 702 |
| 17270 | CEFBS_None, // ADCSXr = 703 |
| 17271 | CEFBS_None, // ADCWr = 704 |
| 17272 | CEFBS_None, // ADCXr = 705 |
| 17273 | CEFBS_HasMTE, // ADDG = 706 |
| 17274 | CEFBS_HasSVE2, // ADDHNB_ZZZ_B = 707 |
| 17275 | CEFBS_HasSVE2, // ADDHNB_ZZZ_H = 708 |
| 17276 | CEFBS_HasSVE2, // ADDHNB_ZZZ_S = 709 |
| 17277 | CEFBS_HasSVE2, // ADDHNT_ZZZ_B = 710 |
| 17278 | CEFBS_HasSVE2, // ADDHNT_ZZZ_H = 711 |
| 17279 | CEFBS_HasSVE2, // ADDHNT_ZZZ_S = 712 |
| 17280 | CEFBS_HasNEON, // ADDHNv2i64_v2i32 = 713 |
| 17281 | CEFBS_HasNEON, // ADDHNv2i64_v4i32 = 714 |
| 17282 | CEFBS_HasNEON, // ADDHNv4i32_v4i16 = 715 |
| 17283 | CEFBS_HasNEON, // ADDHNv4i32_v8i16 = 716 |
| 17284 | CEFBS_HasNEON, // ADDHNv8i16_v16i8 = 717 |
| 17285 | CEFBS_HasNEON, // ADDHNv8i16_v8i8 = 718 |
| 17286 | CEFBS_HasSVE, // ADDPL_XXI = 719 |
| 17287 | CEFBS_HasSVE2, // ADDP_ZPmZ_B = 720 |
| 17288 | CEFBS_HasSVE2, // ADDP_ZPmZ_D = 721 |
| 17289 | CEFBS_HasSVE2, // ADDP_ZPmZ_H = 722 |
| 17290 | CEFBS_HasSVE2, // ADDP_ZPmZ_S = 723 |
| 17291 | CEFBS_HasNEON, // ADDPv16i8 = 724 |
| 17292 | CEFBS_HasNEON, // ADDPv2i32 = 725 |
| 17293 | CEFBS_HasNEON, // ADDPv2i64 = 726 |
| 17294 | CEFBS_HasNEON, // ADDPv2i64p = 727 |
| 17295 | CEFBS_HasNEON, // ADDPv4i16 = 728 |
| 17296 | CEFBS_HasNEON, // ADDPv4i32 = 729 |
| 17297 | CEFBS_HasNEON, // ADDPv8i16 = 730 |
| 17298 | CEFBS_HasNEON, // ADDPv8i8 = 731 |
| 17299 | CEFBS_None, // ADDSWri = 732 |
| 17300 | CEFBS_None, // ADDSWrs = 733 |
| 17301 | CEFBS_None, // ADDSWrx = 734 |
| 17302 | CEFBS_None, // ADDSXri = 735 |
| 17303 | CEFBS_None, // ADDSXrs = 736 |
| 17304 | CEFBS_None, // ADDSXrx = 737 |
| 17305 | CEFBS_None, // ADDSXrx64 = 738 |
| 17306 | CEFBS_HasSVE, // ADDVL_XXI = 739 |
| 17307 | CEFBS_HasNEON, // ADDVv16i8v = 740 |
| 17308 | CEFBS_HasNEON, // ADDVv4i16v = 741 |
| 17309 | CEFBS_HasNEON, // ADDVv4i32v = 742 |
| 17310 | CEFBS_HasNEON, // ADDVv8i16v = 743 |
| 17311 | CEFBS_HasNEON, // ADDVv8i8v = 744 |
| 17312 | CEFBS_None, // ADDWri = 745 |
| 17313 | CEFBS_None, // ADDWrs = 746 |
| 17314 | CEFBS_None, // ADDWrx = 747 |
| 17315 | CEFBS_None, // ADDXri = 748 |
| 17316 | CEFBS_None, // ADDXrs = 749 |
| 17317 | CEFBS_None, // ADDXrx = 750 |
| 17318 | CEFBS_None, // ADDXrx64 = 751 |
| 17319 | CEFBS_HasSVE, // ADD_ZI_B = 752 |
| 17320 | CEFBS_HasSVE, // ADD_ZI_D = 753 |
| 17321 | CEFBS_HasSVE, // ADD_ZI_H = 754 |
| 17322 | CEFBS_HasSVE, // ADD_ZI_S = 755 |
| 17323 | CEFBS_HasSVE, // ADD_ZPmZ_B = 756 |
| 17324 | CEFBS_HasSVE, // ADD_ZPmZ_D = 757 |
| 17325 | CEFBS_HasSVE, // ADD_ZPmZ_H = 758 |
| 17326 | CEFBS_HasSVE, // ADD_ZPmZ_S = 759 |
| 17327 | CEFBS_HasSVE, // ADD_ZZZ_B = 760 |
| 17328 | CEFBS_HasSVE, // ADD_ZZZ_D = 761 |
| 17329 | CEFBS_HasSVE, // ADD_ZZZ_H = 762 |
| 17330 | CEFBS_HasSVE, // ADD_ZZZ_S = 763 |
| 17331 | CEFBS_HasNEON, // ADDv16i8 = 764 |
| 17332 | CEFBS_HasNEON, // ADDv1i64 = 765 |
| 17333 | CEFBS_HasNEON, // ADDv2i32 = 766 |
| 17334 | CEFBS_HasNEON, // ADDv2i64 = 767 |
| 17335 | CEFBS_HasNEON, // ADDv4i16 = 768 |
| 17336 | CEFBS_HasNEON, // ADDv4i32 = 769 |
| 17337 | CEFBS_HasNEON, // ADDv8i16 = 770 |
| 17338 | CEFBS_HasNEON, // ADDv8i8 = 771 |
| 17339 | CEFBS_None, // ADR = 772 |
| 17340 | CEFBS_None, // ADRP = 773 |
| 17341 | CEFBS_HasSVE, // ADR_LSL_ZZZ_D_0 = 774 |
| 17342 | CEFBS_HasSVE, // ADR_LSL_ZZZ_D_1 = 775 |
| 17343 | CEFBS_HasSVE, // ADR_LSL_ZZZ_D_2 = 776 |
| 17344 | CEFBS_HasSVE, // ADR_LSL_ZZZ_D_3 = 777 |
| 17345 | CEFBS_HasSVE, // ADR_LSL_ZZZ_S_0 = 778 |
| 17346 | CEFBS_HasSVE, // ADR_LSL_ZZZ_S_1 = 779 |
| 17347 | CEFBS_HasSVE, // ADR_LSL_ZZZ_S_2 = 780 |
| 17348 | CEFBS_HasSVE, // ADR_LSL_ZZZ_S_3 = 781 |
| 17349 | CEFBS_HasSVE, // ADR_SXTW_ZZZ_D_0 = 782 |
| 17350 | CEFBS_HasSVE, // ADR_SXTW_ZZZ_D_1 = 783 |
| 17351 | CEFBS_HasSVE, // ADR_SXTW_ZZZ_D_2 = 784 |
| 17352 | CEFBS_HasSVE, // ADR_SXTW_ZZZ_D_3 = 785 |
| 17353 | CEFBS_HasSVE, // ADR_UXTW_ZZZ_D_0 = 786 |
| 17354 | CEFBS_HasSVE, // ADR_UXTW_ZZZ_D_1 = 787 |
| 17355 | CEFBS_HasSVE, // ADR_UXTW_ZZZ_D_2 = 788 |
| 17356 | CEFBS_HasSVE, // ADR_UXTW_ZZZ_D_3 = 789 |
| 17357 | CEFBS_HasSVE2AES, // AESD_ZZZ_B = 790 |
| 17358 | CEFBS_HasAES, // AESDrr = 791 |
| 17359 | CEFBS_HasSVE2AES, // AESE_ZZZ_B = 792 |
| 17360 | CEFBS_HasAES, // AESErr = 793 |
| 17361 | CEFBS_HasSVE2AES, // AESIMC_ZZ_B = 794 |
| 17362 | CEFBS_HasAES, // AESIMCrr = 795 |
| 17363 | CEFBS_HasSVE2AES, // AESMC_ZZ_B = 796 |
| 17364 | CEFBS_HasAES, // AESMCrr = 797 |
| 17365 | CEFBS_None, // ANDSWri = 798 |
| 17366 | CEFBS_None, // ANDSWrs = 799 |
| 17367 | CEFBS_None, // ANDSXri = 800 |
| 17368 | CEFBS_None, // ANDSXrs = 801 |
| 17369 | CEFBS_HasSVE, // ANDS_PPzPP = 802 |
| 17370 | CEFBS_HasSVE, // ANDV_VPZ_B = 803 |
| 17371 | CEFBS_HasSVE, // ANDV_VPZ_D = 804 |
| 17372 | CEFBS_HasSVE, // ANDV_VPZ_H = 805 |
| 17373 | CEFBS_HasSVE, // ANDV_VPZ_S = 806 |
| 17374 | CEFBS_None, // ANDWri = 807 |
| 17375 | CEFBS_None, // ANDWrs = 808 |
| 17376 | CEFBS_None, // ANDXri = 809 |
| 17377 | CEFBS_None, // ANDXrs = 810 |
| 17378 | CEFBS_HasSVE, // AND_PPzPP = 811 |
| 17379 | CEFBS_HasSVE, // AND_ZI = 812 |
| 17380 | CEFBS_HasSVE, // AND_ZPmZ_B = 813 |
| 17381 | CEFBS_HasSVE, // AND_ZPmZ_D = 814 |
| 17382 | CEFBS_HasSVE, // AND_ZPmZ_H = 815 |
| 17383 | CEFBS_HasSVE, // AND_ZPmZ_S = 816 |
| 17384 | CEFBS_HasSVE, // AND_ZZZ = 817 |
| 17385 | CEFBS_HasNEON, // ANDv16i8 = 818 |
| 17386 | CEFBS_HasNEON, // ANDv8i8 = 819 |
| 17387 | CEFBS_HasSVE, // ASRD_ZPmI_B = 820 |
| 17388 | CEFBS_HasSVE, // ASRD_ZPmI_D = 821 |
| 17389 | CEFBS_HasSVE, // ASRD_ZPmI_H = 822 |
| 17390 | CEFBS_HasSVE, // ASRD_ZPmI_S = 823 |
| 17391 | CEFBS_HasSVE, // ASRR_ZPmZ_B = 824 |
| 17392 | CEFBS_HasSVE, // ASRR_ZPmZ_D = 825 |
| 17393 | CEFBS_HasSVE, // ASRR_ZPmZ_H = 826 |
| 17394 | CEFBS_HasSVE, // ASRR_ZPmZ_S = 827 |
| 17395 | CEFBS_None, // ASRVWr = 828 |
| 17396 | CEFBS_None, // ASRVXr = 829 |
| 17397 | CEFBS_HasSVE, // ASR_WIDE_ZPmZ_B = 830 |
| 17398 | CEFBS_HasSVE, // ASR_WIDE_ZPmZ_H = 831 |
| 17399 | CEFBS_HasSVE, // ASR_WIDE_ZPmZ_S = 832 |
| 17400 | CEFBS_HasSVE, // ASR_WIDE_ZZZ_B = 833 |
| 17401 | CEFBS_HasSVE, // ASR_WIDE_ZZZ_H = 834 |
| 17402 | CEFBS_HasSVE, // ASR_WIDE_ZZZ_S = 835 |
| 17403 | CEFBS_HasSVE, // ASR_ZPmI_B = 836 |
| 17404 | CEFBS_HasSVE, // ASR_ZPmI_D = 837 |
| 17405 | CEFBS_HasSVE, // ASR_ZPmI_H = 838 |
| 17406 | CEFBS_HasSVE, // ASR_ZPmI_S = 839 |
| 17407 | CEFBS_HasSVE, // ASR_ZPmZ_B = 840 |
| 17408 | CEFBS_HasSVE, // ASR_ZPmZ_D = 841 |
| 17409 | CEFBS_HasSVE, // ASR_ZPmZ_H = 842 |
| 17410 | CEFBS_HasSVE, // ASR_ZPmZ_S = 843 |
| 17411 | CEFBS_HasSVE, // ASR_ZZI_B = 844 |
| 17412 | CEFBS_HasSVE, // ASR_ZZI_D = 845 |
| 17413 | CEFBS_HasSVE, // ASR_ZZI_H = 846 |
| 17414 | CEFBS_HasSVE, // ASR_ZZI_S = 847 |
| 17415 | CEFBS_HasPAuth, // AUTDA = 848 |
| 17416 | CEFBS_HasPAuth, // AUTDB = 849 |
| 17417 | CEFBS_HasPAuth, // AUTDZA = 850 |
| 17418 | CEFBS_HasPAuth, // AUTDZB = 851 |
| 17419 | CEFBS_HasPAuth, // AUTIA = 852 |
| 17420 | CEFBS_None, // AUTIA1716 = 853 |
| 17421 | CEFBS_None, // AUTIASP = 854 |
| 17422 | CEFBS_None, // AUTIAZ = 855 |
| 17423 | CEFBS_HasPAuth, // AUTIB = 856 |
| 17424 | CEFBS_None, // AUTIB1716 = 857 |
| 17425 | CEFBS_None, // AUTIBSP = 858 |
| 17426 | CEFBS_None, // AUTIBZ = 859 |
| 17427 | CEFBS_HasPAuth, // AUTIZA = 860 |
| 17428 | CEFBS_HasPAuth, // AUTIZB = 861 |
| 17429 | CEFBS_HasAltNZCV, // AXFLAG = 862 |
| 17430 | CEFBS_None, // B = 863 |
| 17431 | CEFBS_HasSHA3, // BCAX = 864 |
| 17432 | CEFBS_HasSVE2, // BCAX_ZZZZ = 865 |
| 17433 | CEFBS_HasSVE2BitPerm, // BDEP_ZZZ_B = 866 |
| 17434 | CEFBS_HasSVE2BitPerm, // BDEP_ZZZ_D = 867 |
| 17435 | CEFBS_HasSVE2BitPerm, // BDEP_ZZZ_H = 868 |
| 17436 | CEFBS_HasSVE2BitPerm, // BDEP_ZZZ_S = 869 |
| 17437 | CEFBS_HasSVE2BitPerm, // BEXT_ZZZ_B = 870 |
| 17438 | CEFBS_HasSVE2BitPerm, // BEXT_ZZZ_D = 871 |
| 17439 | CEFBS_HasSVE2BitPerm, // BEXT_ZZZ_H = 872 |
| 17440 | CEFBS_HasSVE2BitPerm, // BEXT_ZZZ_S = 873 |
| 17441 | CEFBS_HasBF16, // BF16DOTlanev4bf16 = 874 |
| 17442 | CEFBS_HasBF16, // BF16DOTlanev8bf16 = 875 |
| 17443 | CEFBS_HasBF16, // BFCVT = 876 |
| 17444 | CEFBS_HasBF16, // BFCVTN = 877 |
| 17445 | CEFBS_HasBF16, // BFCVTN2 = 878 |
| 17446 | CEFBS_HasBF16_HasSVE, // BFCVTNT_ZPmZ = 879 |
| 17447 | CEFBS_HasBF16_HasSVE, // BFCVT_ZPmZ = 880 |
| 17448 | CEFBS_HasBF16_HasSVE, // BFDOT_ZZI = 881 |
| 17449 | CEFBS_HasBF16_HasSVE, // BFDOT_ZZZ = 882 |
| 17450 | CEFBS_HasBF16, // BFDOTv4bf16 = 883 |
| 17451 | CEFBS_HasBF16, // BFDOTv8bf16 = 884 |
| 17452 | CEFBS_HasBF16, // BFMLALB = 885 |
| 17453 | CEFBS_HasBF16, // BFMLALBIdx = 886 |
| 17454 | CEFBS_HasBF16, // BFMLALT = 887 |
| 17455 | CEFBS_HasBF16, // BFMLALTIdx = 888 |
| 17456 | CEFBS_HasBF16, // BFMMLA = 889 |
| 17457 | CEFBS_HasBF16_HasSVE, // BFMMLA_B_ZZI = 890 |
| 17458 | CEFBS_HasBF16_HasSVE, // BFMMLA_B_ZZZ = 891 |
| 17459 | CEFBS_HasBF16_HasSVE, // BFMMLA_T_ZZI = 892 |
| 17460 | CEFBS_HasBF16_HasSVE, // BFMMLA_T_ZZZ = 893 |
| 17461 | CEFBS_HasBF16_HasSVE, // BFMMLA_ZZZ = 894 |
| 17462 | CEFBS_None, // BFMWri = 895 |
| 17463 | CEFBS_None, // BFMXri = 896 |
| 17464 | CEFBS_HasSVE2BitPerm, // BGRP_ZZZ_B = 897 |
| 17465 | CEFBS_HasSVE2BitPerm, // BGRP_ZZZ_D = 898 |
| 17466 | CEFBS_HasSVE2BitPerm, // BGRP_ZZZ_H = 899 |
| 17467 | CEFBS_HasSVE2BitPerm, // BGRP_ZZZ_S = 900 |
| 17468 | CEFBS_None, // BICSWrs = 901 |
| 17469 | CEFBS_None, // BICSXrs = 902 |
| 17470 | CEFBS_HasSVE, // BICS_PPzPP = 903 |
| 17471 | CEFBS_None, // BICWrs = 904 |
| 17472 | CEFBS_None, // BICXrs = 905 |
| 17473 | CEFBS_HasSVE, // BIC_PPzPP = 906 |
| 17474 | CEFBS_HasSVE, // BIC_ZPmZ_B = 907 |
| 17475 | CEFBS_HasSVE, // BIC_ZPmZ_D = 908 |
| 17476 | CEFBS_HasSVE, // BIC_ZPmZ_H = 909 |
| 17477 | CEFBS_HasSVE, // BIC_ZPmZ_S = 910 |
| 17478 | CEFBS_HasSVE, // BIC_ZZZ = 911 |
| 17479 | CEFBS_HasNEON, // BICv16i8 = 912 |
| 17480 | CEFBS_HasNEON, // BICv2i32 = 913 |
| 17481 | CEFBS_HasNEON, // BICv4i16 = 914 |
| 17482 | CEFBS_HasNEON, // BICv4i32 = 915 |
| 17483 | CEFBS_HasNEON, // BICv8i16 = 916 |
| 17484 | CEFBS_HasNEON, // BICv8i8 = 917 |
| 17485 | CEFBS_HasNEON, // BIFv16i8 = 918 |
| 17486 | CEFBS_HasNEON, // BIFv8i8 = 919 |
| 17487 | CEFBS_HasNEON, // BITv16i8 = 920 |
| 17488 | CEFBS_HasNEON, // BITv8i8 = 921 |
| 17489 | CEFBS_None, // BL = 922 |
| 17490 | CEFBS_None, // BLR = 923 |
| 17491 | CEFBS_HasPAuth, // BLRAA = 924 |
| 17492 | CEFBS_HasPAuth, // BLRAAZ = 925 |
| 17493 | CEFBS_HasPAuth, // BLRAB = 926 |
| 17494 | CEFBS_HasPAuth, // BLRABZ = 927 |
| 17495 | CEFBS_None, // BR = 928 |
| 17496 | CEFBS_HasPAuth, // BRAA = 929 |
| 17497 | CEFBS_HasPAuth, // BRAAZ = 930 |
| 17498 | CEFBS_HasPAuth, // BRAB = 931 |
| 17499 | CEFBS_HasPAuth, // BRABZ = 932 |
| 17500 | CEFBS_HasBRBE, // BRB_IALL = 933 |
| 17501 | CEFBS_HasBRBE, // BRB_INJ = 934 |
| 17502 | CEFBS_None, // BRK = 935 |
| 17503 | CEFBS_HasSVE, // BRKAS_PPzP = 936 |
| 17504 | CEFBS_HasSVE, // BRKA_PPmP = 937 |
| 17505 | CEFBS_HasSVE, // BRKA_PPzP = 938 |
| 17506 | CEFBS_HasSVE, // BRKBS_PPzP = 939 |
| 17507 | CEFBS_HasSVE, // BRKB_PPmP = 940 |
| 17508 | CEFBS_HasSVE, // BRKB_PPzP = 941 |
| 17509 | CEFBS_HasSVE, // BRKNS_PPzP = 942 |
| 17510 | CEFBS_HasSVE, // BRKN_PPzP = 943 |
| 17511 | CEFBS_HasSVE, // BRKPAS_PPzPP = 944 |
| 17512 | CEFBS_HasSVE, // BRKPA_PPzPP = 945 |
| 17513 | CEFBS_HasSVE, // BRKPBS_PPzPP = 946 |
| 17514 | CEFBS_HasSVE, // BRKPB_PPzPP = 947 |
| 17515 | CEFBS_HasSVE2, // BSL1N_ZZZZ = 948 |
| 17516 | CEFBS_HasSVE2, // BSL2N_ZZZZ = 949 |
| 17517 | CEFBS_HasSVE2, // BSL_ZZZZ = 950 |
| 17518 | CEFBS_HasNEON, // BSLv16i8 = 951 |
| 17519 | CEFBS_HasNEON, // BSLv8i8 = 952 |
| 17520 | CEFBS_None, // Bcc = 953 |
| 17521 | CEFBS_HasSVE2, // CADD_ZZI_B = 954 |
| 17522 | CEFBS_HasSVE2, // CADD_ZZI_D = 955 |
| 17523 | CEFBS_HasSVE2, // CADD_ZZI_H = 956 |
| 17524 | CEFBS_HasSVE2, // CADD_ZZI_S = 957 |
| 17525 | CEFBS_HasLSE, // CASAB = 958 |
| 17526 | CEFBS_HasLSE, // CASAH = 959 |
| 17527 | CEFBS_HasLSE, // CASALB = 960 |
| 17528 | CEFBS_HasLSE, // CASALH = 961 |
| 17529 | CEFBS_HasLSE, // CASALW = 962 |
| 17530 | CEFBS_HasLSE, // CASALX = 963 |
| 17531 | CEFBS_HasLSE, // CASAW = 964 |
| 17532 | CEFBS_HasLSE, // CASAX = 965 |
| 17533 | CEFBS_HasLSE, // CASB = 966 |
| 17534 | CEFBS_HasLSE, // CASH = 967 |
| 17535 | CEFBS_HasLSE, // CASLB = 968 |
| 17536 | CEFBS_HasLSE, // CASLH = 969 |
| 17537 | CEFBS_HasLSE, // CASLW = 970 |
| 17538 | CEFBS_HasLSE, // CASLX = 971 |
| 17539 | CEFBS_HasLSE, // CASPALW = 972 |
| 17540 | CEFBS_HasLSE, // CASPALX = 973 |
| 17541 | CEFBS_HasLSE, // CASPAW = 974 |
| 17542 | CEFBS_HasLSE, // CASPAX = 975 |
| 17543 | CEFBS_HasLSE, // CASPLW = 976 |
| 17544 | CEFBS_HasLSE, // CASPLX = 977 |
| 17545 | CEFBS_HasLSE, // CASPW = 978 |
| 17546 | CEFBS_HasLSE, // CASPX = 979 |
| 17547 | CEFBS_HasLSE, // CASW = 980 |
| 17548 | CEFBS_HasLSE, // CASX = 981 |
| 17549 | CEFBS_None, // CBNZW = 982 |
| 17550 | CEFBS_None, // CBNZX = 983 |
| 17551 | CEFBS_None, // CBZW = 984 |
| 17552 | CEFBS_None, // CBZX = 985 |
| 17553 | CEFBS_None, // CCMNWi = 986 |
| 17554 | CEFBS_None, // CCMNWr = 987 |
| 17555 | CEFBS_None, // CCMNXi = 988 |
| 17556 | CEFBS_None, // CCMNXr = 989 |
| 17557 | CEFBS_None, // CCMPWi = 990 |
| 17558 | CEFBS_None, // CCMPWr = 991 |
| 17559 | CEFBS_None, // CCMPXi = 992 |
| 17560 | CEFBS_None, // CCMPXr = 993 |
| 17561 | CEFBS_HasSVE2, // CDOT_ZZZI_D = 994 |
| 17562 | CEFBS_HasSVE2, // CDOT_ZZZI_S = 995 |
| 17563 | CEFBS_HasSVE2, // CDOT_ZZZ_D = 996 |
| 17564 | CEFBS_HasSVE2, // CDOT_ZZZ_S = 997 |
| 17565 | CEFBS_HasFlagM, // CFINV = 998 |
| 17566 | CEFBS_HasSVE, // CLASTA_RPZ_B = 999 |
| 17567 | CEFBS_HasSVE, // CLASTA_RPZ_D = 1000 |
| 17568 | CEFBS_HasSVE, // CLASTA_RPZ_H = 1001 |
| 17569 | CEFBS_HasSVE, // CLASTA_RPZ_S = 1002 |
| 17570 | CEFBS_HasSVE, // CLASTA_VPZ_B = 1003 |
| 17571 | CEFBS_HasSVE, // CLASTA_VPZ_D = 1004 |
| 17572 | CEFBS_HasSVE, // CLASTA_VPZ_H = 1005 |
| 17573 | CEFBS_HasSVE, // CLASTA_VPZ_S = 1006 |
| 17574 | CEFBS_HasSVE, // CLASTA_ZPZ_B = 1007 |
| 17575 | CEFBS_HasSVE, // CLASTA_ZPZ_D = 1008 |
| 17576 | CEFBS_HasSVE, // CLASTA_ZPZ_H = 1009 |
| 17577 | CEFBS_HasSVE, // CLASTA_ZPZ_S = 1010 |
| 17578 | CEFBS_HasSVE, // CLASTB_RPZ_B = 1011 |
| 17579 | CEFBS_HasSVE, // CLASTB_RPZ_D = 1012 |
| 17580 | CEFBS_HasSVE, // CLASTB_RPZ_H = 1013 |
| 17581 | CEFBS_HasSVE, // CLASTB_RPZ_S = 1014 |
| 17582 | CEFBS_HasSVE, // CLASTB_VPZ_B = 1015 |
| 17583 | CEFBS_HasSVE, // CLASTB_VPZ_D = 1016 |
| 17584 | CEFBS_HasSVE, // CLASTB_VPZ_H = 1017 |
| 17585 | CEFBS_HasSVE, // CLASTB_VPZ_S = 1018 |
| 17586 | CEFBS_HasSVE, // CLASTB_ZPZ_B = 1019 |
| 17587 | CEFBS_HasSVE, // CLASTB_ZPZ_D = 1020 |
| 17588 | CEFBS_HasSVE, // CLASTB_ZPZ_H = 1021 |
| 17589 | CEFBS_HasSVE, // CLASTB_ZPZ_S = 1022 |
| 17590 | CEFBS_None, // CLREX = 1023 |
| 17591 | CEFBS_None, // CLSWr = 1024 |
| 17592 | CEFBS_None, // CLSXr = 1025 |
| 17593 | CEFBS_HasSVE, // CLS_ZPmZ_B = 1026 |
| 17594 | CEFBS_HasSVE, // CLS_ZPmZ_D = 1027 |
| 17595 | CEFBS_HasSVE, // CLS_ZPmZ_H = 1028 |
| 17596 | CEFBS_HasSVE, // CLS_ZPmZ_S = 1029 |
| 17597 | CEFBS_HasNEON, // CLSv16i8 = 1030 |
| 17598 | CEFBS_HasNEON, // CLSv2i32 = 1031 |
| 17599 | CEFBS_HasNEON, // CLSv4i16 = 1032 |
| 17600 | CEFBS_HasNEON, // CLSv4i32 = 1033 |
| 17601 | CEFBS_HasNEON, // CLSv8i16 = 1034 |
| 17602 | CEFBS_HasNEON, // CLSv8i8 = 1035 |
| 17603 | CEFBS_None, // CLZWr = 1036 |
| 17604 | CEFBS_None, // CLZXr = 1037 |
| 17605 | CEFBS_HasSVE, // CLZ_ZPmZ_B = 1038 |
| 17606 | CEFBS_HasSVE, // CLZ_ZPmZ_D = 1039 |
| 17607 | CEFBS_HasSVE, // CLZ_ZPmZ_H = 1040 |
| 17608 | CEFBS_HasSVE, // CLZ_ZPmZ_S = 1041 |
| 17609 | CEFBS_HasNEON, // CLZv16i8 = 1042 |
| 17610 | CEFBS_HasNEON, // CLZv2i32 = 1043 |
| 17611 | CEFBS_HasNEON, // CLZv4i16 = 1044 |
| 17612 | CEFBS_HasNEON, // CLZv4i32 = 1045 |
| 17613 | CEFBS_HasNEON, // CLZv8i16 = 1046 |
| 17614 | CEFBS_HasNEON, // CLZv8i8 = 1047 |
| 17615 | CEFBS_HasNEON, // CMEQv16i8 = 1048 |
| 17616 | CEFBS_HasNEON, // CMEQv16i8rz = 1049 |
| 17617 | CEFBS_HasNEON, // CMEQv1i64 = 1050 |
| 17618 | CEFBS_HasNEON, // CMEQv1i64rz = 1051 |
| 17619 | CEFBS_HasNEON, // CMEQv2i32 = 1052 |
| 17620 | CEFBS_HasNEON, // CMEQv2i32rz = 1053 |
| 17621 | CEFBS_HasNEON, // CMEQv2i64 = 1054 |
| 17622 | CEFBS_HasNEON, // CMEQv2i64rz = 1055 |
| 17623 | CEFBS_HasNEON, // CMEQv4i16 = 1056 |
| 17624 | CEFBS_HasNEON, // CMEQv4i16rz = 1057 |
| 17625 | CEFBS_HasNEON, // CMEQv4i32 = 1058 |
| 17626 | CEFBS_HasNEON, // CMEQv4i32rz = 1059 |
| 17627 | CEFBS_HasNEON, // CMEQv8i16 = 1060 |
| 17628 | CEFBS_HasNEON, // CMEQv8i16rz = 1061 |
| 17629 | CEFBS_HasNEON, // CMEQv8i8 = 1062 |
| 17630 | CEFBS_HasNEON, // CMEQv8i8rz = 1063 |
| 17631 | CEFBS_HasNEON, // CMGEv16i8 = 1064 |
| 17632 | CEFBS_HasNEON, // CMGEv16i8rz = 1065 |
| 17633 | CEFBS_HasNEON, // CMGEv1i64 = 1066 |
| 17634 | CEFBS_HasNEON, // CMGEv1i64rz = 1067 |
| 17635 | CEFBS_HasNEON, // CMGEv2i32 = 1068 |
| 17636 | CEFBS_HasNEON, // CMGEv2i32rz = 1069 |
| 17637 | CEFBS_HasNEON, // CMGEv2i64 = 1070 |
| 17638 | CEFBS_HasNEON, // CMGEv2i64rz = 1071 |
| 17639 | CEFBS_HasNEON, // CMGEv4i16 = 1072 |
| 17640 | CEFBS_HasNEON, // CMGEv4i16rz = 1073 |
| 17641 | CEFBS_HasNEON, // CMGEv4i32 = 1074 |
| 17642 | CEFBS_HasNEON, // CMGEv4i32rz = 1075 |
| 17643 | CEFBS_HasNEON, // CMGEv8i16 = 1076 |
| 17644 | CEFBS_HasNEON, // CMGEv8i16rz = 1077 |
| 17645 | CEFBS_HasNEON, // CMGEv8i8 = 1078 |
| 17646 | CEFBS_HasNEON, // CMGEv8i8rz = 1079 |
| 17647 | CEFBS_HasNEON, // CMGTv16i8 = 1080 |
| 17648 | CEFBS_HasNEON, // CMGTv16i8rz = 1081 |
| 17649 | CEFBS_HasNEON, // CMGTv1i64 = 1082 |
| 17650 | CEFBS_HasNEON, // CMGTv1i64rz = 1083 |
| 17651 | CEFBS_HasNEON, // CMGTv2i32 = 1084 |
| 17652 | CEFBS_HasNEON, // CMGTv2i32rz = 1085 |
| 17653 | CEFBS_HasNEON, // CMGTv2i64 = 1086 |
| 17654 | CEFBS_HasNEON, // CMGTv2i64rz = 1087 |
| 17655 | CEFBS_HasNEON, // CMGTv4i16 = 1088 |
| 17656 | CEFBS_HasNEON, // CMGTv4i16rz = 1089 |
| 17657 | CEFBS_HasNEON, // CMGTv4i32 = 1090 |
| 17658 | CEFBS_HasNEON, // CMGTv4i32rz = 1091 |
| 17659 | CEFBS_HasNEON, // CMGTv8i16 = 1092 |
| 17660 | CEFBS_HasNEON, // CMGTv8i16rz = 1093 |
| 17661 | CEFBS_HasNEON, // CMGTv8i8 = 1094 |
| 17662 | CEFBS_HasNEON, // CMGTv8i8rz = 1095 |
| 17663 | CEFBS_HasNEON, // CMHIv16i8 = 1096 |
| 17664 | CEFBS_HasNEON, // CMHIv1i64 = 1097 |
| 17665 | CEFBS_HasNEON, // CMHIv2i32 = 1098 |
| 17666 | CEFBS_HasNEON, // CMHIv2i64 = 1099 |
| 17667 | CEFBS_HasNEON, // CMHIv4i16 = 1100 |
| 17668 | CEFBS_HasNEON, // CMHIv4i32 = 1101 |
| 17669 | CEFBS_HasNEON, // CMHIv8i16 = 1102 |
| 17670 | CEFBS_HasNEON, // CMHIv8i8 = 1103 |
| 17671 | CEFBS_HasNEON, // CMHSv16i8 = 1104 |
| 17672 | CEFBS_HasNEON, // CMHSv1i64 = 1105 |
| 17673 | CEFBS_HasNEON, // CMHSv2i32 = 1106 |
| 17674 | CEFBS_HasNEON, // CMHSv2i64 = 1107 |
| 17675 | CEFBS_HasNEON, // CMHSv4i16 = 1108 |
| 17676 | CEFBS_HasNEON, // CMHSv4i32 = 1109 |
| 17677 | CEFBS_HasNEON, // CMHSv8i16 = 1110 |
| 17678 | CEFBS_HasNEON, // CMHSv8i8 = 1111 |
| 17679 | CEFBS_HasSVE2, // CMLA_ZZZI_H = 1112 |
| 17680 | CEFBS_HasSVE2, // CMLA_ZZZI_S = 1113 |
| 17681 | CEFBS_HasSVE2, // CMLA_ZZZ_B = 1114 |
| 17682 | CEFBS_HasSVE2, // CMLA_ZZZ_D = 1115 |
| 17683 | CEFBS_HasSVE2, // CMLA_ZZZ_H = 1116 |
| 17684 | CEFBS_HasSVE2, // CMLA_ZZZ_S = 1117 |
| 17685 | CEFBS_HasNEON, // CMLEv16i8rz = 1118 |
| 17686 | CEFBS_HasNEON, // CMLEv1i64rz = 1119 |
| 17687 | CEFBS_HasNEON, // CMLEv2i32rz = 1120 |
| 17688 | CEFBS_HasNEON, // CMLEv2i64rz = 1121 |
| 17689 | CEFBS_HasNEON, // CMLEv4i16rz = 1122 |
| 17690 | CEFBS_HasNEON, // CMLEv4i32rz = 1123 |
| 17691 | CEFBS_HasNEON, // CMLEv8i16rz = 1124 |
| 17692 | CEFBS_HasNEON, // CMLEv8i8rz = 1125 |
| 17693 | CEFBS_HasNEON, // CMLTv16i8rz = 1126 |
| 17694 | CEFBS_HasNEON, // CMLTv1i64rz = 1127 |
| 17695 | CEFBS_HasNEON, // CMLTv2i32rz = 1128 |
| 17696 | CEFBS_HasNEON, // CMLTv2i64rz = 1129 |
| 17697 | CEFBS_HasNEON, // CMLTv4i16rz = 1130 |
| 17698 | CEFBS_HasNEON, // CMLTv4i32rz = 1131 |
| 17699 | CEFBS_HasNEON, // CMLTv8i16rz = 1132 |
| 17700 | CEFBS_HasNEON, // CMLTv8i8rz = 1133 |
| 17701 | CEFBS_HasSVE, // CMPEQ_PPzZI_B = 1134 |
| 17702 | CEFBS_HasSVE, // CMPEQ_PPzZI_D = 1135 |
| 17703 | CEFBS_HasSVE, // CMPEQ_PPzZI_H = 1136 |
| 17704 | CEFBS_HasSVE, // CMPEQ_PPzZI_S = 1137 |
| 17705 | CEFBS_HasSVE, // CMPEQ_PPzZZ_B = 1138 |
| 17706 | CEFBS_HasSVE, // CMPEQ_PPzZZ_D = 1139 |
| 17707 | CEFBS_HasSVE, // CMPEQ_PPzZZ_H = 1140 |
| 17708 | CEFBS_HasSVE, // CMPEQ_PPzZZ_S = 1141 |
| 17709 | CEFBS_HasSVE, // CMPEQ_WIDE_PPzZZ_B = 1142 |
| 17710 | CEFBS_HasSVE, // CMPEQ_WIDE_PPzZZ_H = 1143 |
| 17711 | CEFBS_HasSVE, // CMPEQ_WIDE_PPzZZ_S = 1144 |
| 17712 | CEFBS_HasSVE, // CMPGE_PPzZI_B = 1145 |
| 17713 | CEFBS_HasSVE, // CMPGE_PPzZI_D = 1146 |
| 17714 | CEFBS_HasSVE, // CMPGE_PPzZI_H = 1147 |
| 17715 | CEFBS_HasSVE, // CMPGE_PPzZI_S = 1148 |
| 17716 | CEFBS_HasSVE, // CMPGE_PPzZZ_B = 1149 |
| 17717 | CEFBS_HasSVE, // CMPGE_PPzZZ_D = 1150 |
| 17718 | CEFBS_HasSVE, // CMPGE_PPzZZ_H = 1151 |
| 17719 | CEFBS_HasSVE, // CMPGE_PPzZZ_S = 1152 |
| 17720 | CEFBS_HasSVE, // CMPGE_WIDE_PPzZZ_B = 1153 |
| 17721 | CEFBS_HasSVE, // CMPGE_WIDE_PPzZZ_H = 1154 |
| 17722 | CEFBS_HasSVE, // CMPGE_WIDE_PPzZZ_S = 1155 |
| 17723 | CEFBS_HasSVE, // CMPGT_PPzZI_B = 1156 |
| 17724 | CEFBS_HasSVE, // CMPGT_PPzZI_D = 1157 |
| 17725 | CEFBS_HasSVE, // CMPGT_PPzZI_H = 1158 |
| 17726 | CEFBS_HasSVE, // CMPGT_PPzZI_S = 1159 |
| 17727 | CEFBS_HasSVE, // CMPGT_PPzZZ_B = 1160 |
| 17728 | CEFBS_HasSVE, // CMPGT_PPzZZ_D = 1161 |
| 17729 | CEFBS_HasSVE, // CMPGT_PPzZZ_H = 1162 |
| 17730 | CEFBS_HasSVE, // CMPGT_PPzZZ_S = 1163 |
| 17731 | CEFBS_HasSVE, // CMPGT_WIDE_PPzZZ_B = 1164 |
| 17732 | CEFBS_HasSVE, // CMPGT_WIDE_PPzZZ_H = 1165 |
| 17733 | CEFBS_HasSVE, // CMPGT_WIDE_PPzZZ_S = 1166 |
| 17734 | CEFBS_HasSVE, // CMPHI_PPzZI_B = 1167 |
| 17735 | CEFBS_HasSVE, // CMPHI_PPzZI_D = 1168 |
| 17736 | CEFBS_HasSVE, // CMPHI_PPzZI_H = 1169 |
| 17737 | CEFBS_HasSVE, // CMPHI_PPzZI_S = 1170 |
| 17738 | CEFBS_HasSVE, // CMPHI_PPzZZ_B = 1171 |
| 17739 | CEFBS_HasSVE, // CMPHI_PPzZZ_D = 1172 |
| 17740 | CEFBS_HasSVE, // CMPHI_PPzZZ_H = 1173 |
| 17741 | CEFBS_HasSVE, // CMPHI_PPzZZ_S = 1174 |
| 17742 | CEFBS_HasSVE, // CMPHI_WIDE_PPzZZ_B = 1175 |
| 17743 | CEFBS_HasSVE, // CMPHI_WIDE_PPzZZ_H = 1176 |
| 17744 | CEFBS_HasSVE, // CMPHI_WIDE_PPzZZ_S = 1177 |
| 17745 | CEFBS_HasSVE, // CMPHS_PPzZI_B = 1178 |
| 17746 | CEFBS_HasSVE, // CMPHS_PPzZI_D = 1179 |
| 17747 | CEFBS_HasSVE, // CMPHS_PPzZI_H = 1180 |
| 17748 | CEFBS_HasSVE, // CMPHS_PPzZI_S = 1181 |
| 17749 | CEFBS_HasSVE, // CMPHS_PPzZZ_B = 1182 |
| 17750 | CEFBS_HasSVE, // CMPHS_PPzZZ_D = 1183 |
| 17751 | CEFBS_HasSVE, // CMPHS_PPzZZ_H = 1184 |
| 17752 | CEFBS_HasSVE, // CMPHS_PPzZZ_S = 1185 |
| 17753 | CEFBS_HasSVE, // CMPHS_WIDE_PPzZZ_B = 1186 |
| 17754 | CEFBS_HasSVE, // CMPHS_WIDE_PPzZZ_H = 1187 |
| 17755 | CEFBS_HasSVE, // CMPHS_WIDE_PPzZZ_S = 1188 |
| 17756 | CEFBS_HasSVE, // CMPLE_PPzZI_B = 1189 |
| 17757 | CEFBS_HasSVE, // CMPLE_PPzZI_D = 1190 |
| 17758 | CEFBS_HasSVE, // CMPLE_PPzZI_H = 1191 |
| 17759 | CEFBS_HasSVE, // CMPLE_PPzZI_S = 1192 |
| 17760 | CEFBS_HasSVE, // CMPLE_WIDE_PPzZZ_B = 1193 |
| 17761 | CEFBS_HasSVE, // CMPLE_WIDE_PPzZZ_H = 1194 |
| 17762 | CEFBS_HasSVE, // CMPLE_WIDE_PPzZZ_S = 1195 |
| 17763 | CEFBS_HasSVE, // CMPLO_PPzZI_B = 1196 |
| 17764 | CEFBS_HasSVE, // CMPLO_PPzZI_D = 1197 |
| 17765 | CEFBS_HasSVE, // CMPLO_PPzZI_H = 1198 |
| 17766 | CEFBS_HasSVE, // CMPLO_PPzZI_S = 1199 |
| 17767 | CEFBS_HasSVE, // CMPLO_WIDE_PPzZZ_B = 1200 |
| 17768 | CEFBS_HasSVE, // CMPLO_WIDE_PPzZZ_H = 1201 |
| 17769 | CEFBS_HasSVE, // CMPLO_WIDE_PPzZZ_S = 1202 |
| 17770 | CEFBS_HasSVE, // CMPLS_PPzZI_B = 1203 |
| 17771 | CEFBS_HasSVE, // CMPLS_PPzZI_D = 1204 |
| 17772 | CEFBS_HasSVE, // CMPLS_PPzZI_H = 1205 |
| 17773 | CEFBS_HasSVE, // CMPLS_PPzZI_S = 1206 |
| 17774 | CEFBS_HasSVE, // CMPLS_WIDE_PPzZZ_B = 1207 |
| 17775 | CEFBS_HasSVE, // CMPLS_WIDE_PPzZZ_H = 1208 |
| 17776 | CEFBS_HasSVE, // CMPLS_WIDE_PPzZZ_S = 1209 |
| 17777 | CEFBS_HasSVE, // CMPLT_PPzZI_B = 1210 |
| 17778 | CEFBS_HasSVE, // CMPLT_PPzZI_D = 1211 |
| 17779 | CEFBS_HasSVE, // CMPLT_PPzZI_H = 1212 |
| 17780 | CEFBS_HasSVE, // CMPLT_PPzZI_S = 1213 |
| 17781 | CEFBS_HasSVE, // CMPLT_WIDE_PPzZZ_B = 1214 |
| 17782 | CEFBS_HasSVE, // CMPLT_WIDE_PPzZZ_H = 1215 |
| 17783 | CEFBS_HasSVE, // CMPLT_WIDE_PPzZZ_S = 1216 |
| 17784 | CEFBS_HasSVE, // CMPNE_PPzZI_B = 1217 |
| 17785 | CEFBS_HasSVE, // CMPNE_PPzZI_D = 1218 |
| 17786 | CEFBS_HasSVE, // CMPNE_PPzZI_H = 1219 |
| 17787 | CEFBS_HasSVE, // CMPNE_PPzZI_S = 1220 |
| 17788 | CEFBS_HasSVE, // CMPNE_PPzZZ_B = 1221 |
| 17789 | CEFBS_HasSVE, // CMPNE_PPzZZ_D = 1222 |
| 17790 | CEFBS_HasSVE, // CMPNE_PPzZZ_H = 1223 |
| 17791 | CEFBS_HasSVE, // CMPNE_PPzZZ_S = 1224 |
| 17792 | CEFBS_HasSVE, // CMPNE_WIDE_PPzZZ_B = 1225 |
| 17793 | CEFBS_HasSVE, // CMPNE_WIDE_PPzZZ_H = 1226 |
| 17794 | CEFBS_HasSVE, // CMPNE_WIDE_PPzZZ_S = 1227 |
| 17795 | CEFBS_HasNEON, // CMTSTv16i8 = 1228 |
| 17796 | CEFBS_HasNEON, // CMTSTv1i64 = 1229 |
| 17797 | CEFBS_HasNEON, // CMTSTv2i32 = 1230 |
| 17798 | CEFBS_HasNEON, // CMTSTv2i64 = 1231 |
| 17799 | CEFBS_HasNEON, // CMTSTv4i16 = 1232 |
| 17800 | CEFBS_HasNEON, // CMTSTv4i32 = 1233 |
| 17801 | CEFBS_HasNEON, // CMTSTv8i16 = 1234 |
| 17802 | CEFBS_HasNEON, // CMTSTv8i8 = 1235 |
| 17803 | CEFBS_HasSVE, // CNOT_ZPmZ_B = 1236 |
| 17804 | CEFBS_HasSVE, // CNOT_ZPmZ_D = 1237 |
| 17805 | CEFBS_HasSVE, // CNOT_ZPmZ_H = 1238 |
| 17806 | CEFBS_HasSVE, // CNOT_ZPmZ_S = 1239 |
| 17807 | CEFBS_HasSVE, // CNTB_XPiI = 1240 |
| 17808 | CEFBS_HasSVE, // CNTD_XPiI = 1241 |
| 17809 | CEFBS_HasSVE, // CNTH_XPiI = 1242 |
| 17810 | CEFBS_HasSVE, // CNTP_XPP_B = 1243 |
| 17811 | CEFBS_HasSVE, // CNTP_XPP_D = 1244 |
| 17812 | CEFBS_HasSVE, // CNTP_XPP_H = 1245 |
| 17813 | CEFBS_HasSVE, // CNTP_XPP_S = 1246 |
| 17814 | CEFBS_HasSVE, // CNTW_XPiI = 1247 |
| 17815 | CEFBS_HasSVE, // CNT_ZPmZ_B = 1248 |
| 17816 | CEFBS_HasSVE, // CNT_ZPmZ_D = 1249 |
| 17817 | CEFBS_HasSVE, // CNT_ZPmZ_H = 1250 |
| 17818 | CEFBS_HasSVE, // CNT_ZPmZ_S = 1251 |
| 17819 | CEFBS_HasNEON, // CNTv16i8 = 1252 |
| 17820 | CEFBS_HasNEON, // CNTv8i8 = 1253 |
| 17821 | CEFBS_HasSVE, // COMPACT_ZPZ_D = 1254 |
| 17822 | CEFBS_HasSVE, // COMPACT_ZPZ_S = 1255 |
| 17823 | CEFBS_HasSVE, // CPY_ZPmI_B = 1256 |
| 17824 | CEFBS_HasSVE, // CPY_ZPmI_D = 1257 |
| 17825 | CEFBS_HasSVE, // CPY_ZPmI_H = 1258 |
| 17826 | CEFBS_HasSVE, // CPY_ZPmI_S = 1259 |
| 17827 | CEFBS_HasSVE, // CPY_ZPmR_B = 1260 |
| 17828 | CEFBS_HasSVE, // CPY_ZPmR_D = 1261 |
| 17829 | CEFBS_HasSVE, // CPY_ZPmR_H = 1262 |
| 17830 | CEFBS_HasSVE, // CPY_ZPmR_S = 1263 |
| 17831 | CEFBS_HasSVE, // CPY_ZPmV_B = 1264 |
| 17832 | CEFBS_HasSVE, // CPY_ZPmV_D = 1265 |
| 17833 | CEFBS_HasSVE, // CPY_ZPmV_H = 1266 |
| 17834 | CEFBS_HasSVE, // CPY_ZPmV_S = 1267 |
| 17835 | CEFBS_HasSVE, // CPY_ZPzI_B = 1268 |
| 17836 | CEFBS_HasSVE, // CPY_ZPzI_D = 1269 |
| 17837 | CEFBS_HasSVE, // CPY_ZPzI_H = 1270 |
| 17838 | CEFBS_HasSVE, // CPY_ZPzI_S = 1271 |
| 17839 | CEFBS_HasNEON, // CPYi16 = 1272 |
| 17840 | CEFBS_HasNEON, // CPYi32 = 1273 |
| 17841 | CEFBS_HasNEON, // CPYi64 = 1274 |
| 17842 | CEFBS_HasNEON, // CPYi8 = 1275 |
| 17843 | CEFBS_HasCRC, // CRC32Brr = 1276 |
| 17844 | CEFBS_HasCRC, // CRC32CBrr = 1277 |
| 17845 | CEFBS_HasCRC, // CRC32CHrr = 1278 |
| 17846 | CEFBS_HasCRC, // CRC32CWrr = 1279 |
| 17847 | CEFBS_HasCRC, // CRC32CXrr = 1280 |
| 17848 | CEFBS_HasCRC, // CRC32Hrr = 1281 |
| 17849 | CEFBS_HasCRC, // CRC32Wrr = 1282 |
| 17850 | CEFBS_HasCRC, // CRC32Xrr = 1283 |
| 17851 | CEFBS_None, // CSELWr = 1284 |
| 17852 | CEFBS_None, // CSELXr = 1285 |
| 17853 | CEFBS_None, // CSINCWr = 1286 |
| 17854 | CEFBS_None, // CSINCXr = 1287 |
| 17855 | CEFBS_None, // CSINVWr = 1288 |
| 17856 | CEFBS_None, // CSINVXr = 1289 |
| 17857 | CEFBS_None, // CSNEGWr = 1290 |
| 17858 | CEFBS_None, // CSNEGXr = 1291 |
| 17859 | CEFBS_HasSVE, // CTERMEQ_WW = 1292 |
| 17860 | CEFBS_HasSVE, // CTERMEQ_XX = 1293 |
| 17861 | CEFBS_HasSVE, // CTERMNE_WW = 1294 |
| 17862 | CEFBS_HasSVE, // CTERMNE_XX = 1295 |
| 17863 | CEFBS_None, // DCPS1 = 1296 |
| 17864 | CEFBS_None, // DCPS2 = 1297 |
| 17865 | CEFBS_None, // DCPS3 = 1298 |
| 17866 | CEFBS_HasSVE, // DECB_XPiI = 1299 |
| 17867 | CEFBS_HasSVE, // DECD_XPiI = 1300 |
| 17868 | CEFBS_HasSVE, // DECD_ZPiI = 1301 |
| 17869 | CEFBS_HasSVE, // DECH_XPiI = 1302 |
| 17870 | CEFBS_HasSVE, // DECH_ZPiI = 1303 |
| 17871 | CEFBS_HasSVE, // DECP_XP_B = 1304 |
| 17872 | CEFBS_HasSVE, // DECP_XP_D = 1305 |
| 17873 | CEFBS_HasSVE, // DECP_XP_H = 1306 |
| 17874 | CEFBS_HasSVE, // DECP_XP_S = 1307 |
| 17875 | CEFBS_HasSVE, // DECP_ZP_D = 1308 |
| 17876 | CEFBS_HasSVE, // DECP_ZP_H = 1309 |
| 17877 | CEFBS_HasSVE, // DECP_ZP_S = 1310 |
| 17878 | CEFBS_HasSVE, // DECW_XPiI = 1311 |
| 17879 | CEFBS_HasSVE, // DECW_ZPiI = 1312 |
| 17880 | CEFBS_None, // DMB = 1313 |
| 17881 | CEFBS_None, // DRPS = 1314 |
| 17882 | CEFBS_None, // DSB = 1315 |
| 17883 | CEFBS_HasXS, // DSBnXS = 1316 |
| 17884 | CEFBS_HasSVE, // DUPM_ZI = 1317 |
| 17885 | CEFBS_HasSVE, // DUP_ZI_B = 1318 |
| 17886 | CEFBS_HasSVE, // DUP_ZI_D = 1319 |
| 17887 | CEFBS_HasSVE, // DUP_ZI_H = 1320 |
| 17888 | CEFBS_HasSVE, // DUP_ZI_S = 1321 |
| 17889 | CEFBS_HasSVE, // DUP_ZR_B = 1322 |
| 17890 | CEFBS_HasSVE, // DUP_ZR_D = 1323 |
| 17891 | CEFBS_HasSVE, // DUP_ZR_H = 1324 |
| 17892 | CEFBS_HasSVE, // DUP_ZR_S = 1325 |
| 17893 | CEFBS_HasSVE, // DUP_ZZI_B = 1326 |
| 17894 | CEFBS_HasSVE, // DUP_ZZI_D = 1327 |
| 17895 | CEFBS_HasSVE, // DUP_ZZI_H = 1328 |
| 17896 | CEFBS_HasSVE, // DUP_ZZI_Q = 1329 |
| 17897 | CEFBS_HasSVE, // DUP_ZZI_S = 1330 |
| 17898 | CEFBS_HasNEON, // DUPv16i8gpr = 1331 |
| 17899 | CEFBS_HasNEON, // DUPv16i8lane = 1332 |
| 17900 | CEFBS_HasNEON, // DUPv2i32gpr = 1333 |
| 17901 | CEFBS_HasNEON, // DUPv2i32lane = 1334 |
| 17902 | CEFBS_HasNEON, // DUPv2i64gpr = 1335 |
| 17903 | CEFBS_HasNEON, // DUPv2i64lane = 1336 |
| 17904 | CEFBS_HasNEON, // DUPv4i16gpr = 1337 |
| 17905 | CEFBS_HasNEON, // DUPv4i16lane = 1338 |
| 17906 | CEFBS_HasNEON, // DUPv4i32gpr = 1339 |
| 17907 | CEFBS_HasNEON, // DUPv4i32lane = 1340 |
| 17908 | CEFBS_HasNEON, // DUPv8i16gpr = 1341 |
| 17909 | CEFBS_HasNEON, // DUPv8i16lane = 1342 |
| 17910 | CEFBS_HasNEON, // DUPv8i8gpr = 1343 |
| 17911 | CEFBS_HasNEON, // DUPv8i8lane = 1344 |
| 17912 | CEFBS_None, // EONWrs = 1345 |
| 17913 | CEFBS_None, // EONXrs = 1346 |
| 17914 | CEFBS_HasSHA3, // EOR3 = 1347 |
| 17915 | CEFBS_HasSVE2, // EOR3_ZZZZ = 1348 |
| 17916 | CEFBS_HasSVE2, // EORBT_ZZZ_B = 1349 |
| 17917 | CEFBS_HasSVE2, // EORBT_ZZZ_D = 1350 |
| 17918 | CEFBS_HasSVE2, // EORBT_ZZZ_H = 1351 |
| 17919 | CEFBS_HasSVE2, // EORBT_ZZZ_S = 1352 |
| 17920 | CEFBS_HasSVE, // EORS_PPzPP = 1353 |
| 17921 | CEFBS_HasSVE2, // EORTB_ZZZ_B = 1354 |
| 17922 | CEFBS_HasSVE2, // EORTB_ZZZ_D = 1355 |
| 17923 | CEFBS_HasSVE2, // EORTB_ZZZ_H = 1356 |
| 17924 | CEFBS_HasSVE2, // EORTB_ZZZ_S = 1357 |
| 17925 | CEFBS_HasSVE, // EORV_VPZ_B = 1358 |
| 17926 | CEFBS_HasSVE, // EORV_VPZ_D = 1359 |
| 17927 | CEFBS_HasSVE, // EORV_VPZ_H = 1360 |
| 17928 | CEFBS_HasSVE, // EORV_VPZ_S = 1361 |
| 17929 | CEFBS_None, // EORWri = 1362 |
| 17930 | CEFBS_None, // EORWrs = 1363 |
| 17931 | CEFBS_None, // EORXri = 1364 |
| 17932 | CEFBS_None, // EORXrs = 1365 |
| 17933 | CEFBS_HasSVE, // EOR_PPzPP = 1366 |
| 17934 | CEFBS_HasSVE, // EOR_ZI = 1367 |
| 17935 | CEFBS_HasSVE, // EOR_ZPmZ_B = 1368 |
| 17936 | CEFBS_HasSVE, // EOR_ZPmZ_D = 1369 |
| 17937 | CEFBS_HasSVE, // EOR_ZPmZ_H = 1370 |
| 17938 | CEFBS_HasSVE, // EOR_ZPmZ_S = 1371 |
| 17939 | CEFBS_HasSVE, // EOR_ZZZ = 1372 |
| 17940 | CEFBS_HasNEON, // EORv16i8 = 1373 |
| 17941 | CEFBS_HasNEON, // EORv8i8 = 1374 |
| 17942 | CEFBS_None, // ERET = 1375 |
| 17943 | CEFBS_HasPAuth, // ERETAA = 1376 |
| 17944 | CEFBS_HasPAuth, // ERETAB = 1377 |
| 17945 | CEFBS_None, // EXTRWrri = 1378 |
| 17946 | CEFBS_None, // EXTRXrri = 1379 |
| 17947 | CEFBS_HasSVE, // EXT_ZZI = 1380 |
| 17948 | CEFBS_HasSVE2, // EXT_ZZI_B = 1381 |
| 17949 | CEFBS_HasNEON, // EXTv16i8 = 1382 |
| 17950 | CEFBS_HasNEON, // EXTv8i8 = 1383 |
| 17951 | CEFBS_HasNEON_HasFullFP16, // FABD16 = 1384 |
| 17952 | CEFBS_HasNEON, // FABD32 = 1385 |
| 17953 | CEFBS_HasNEON, // FABD64 = 1386 |
| 17954 | CEFBS_HasSVE, // FABD_ZPmZ_D = 1387 |
| 17955 | CEFBS_HasSVE, // FABD_ZPmZ_H = 1388 |
| 17956 | CEFBS_HasSVE, // FABD_ZPmZ_S = 1389 |
| 17957 | CEFBS_HasNEON, // FABDv2f32 = 1390 |
| 17958 | CEFBS_HasNEON, // FABDv2f64 = 1391 |
| 17959 | CEFBS_HasNEON_HasFullFP16, // FABDv4f16 = 1392 |
| 17960 | CEFBS_HasNEON, // FABDv4f32 = 1393 |
| 17961 | CEFBS_HasNEON_HasFullFP16, // FABDv8f16 = 1394 |
| 17962 | CEFBS_HasFPARMv8, // FABSDr = 1395 |
| 17963 | CEFBS_HasFullFP16, // FABSHr = 1396 |
| 17964 | CEFBS_HasFPARMv8, // FABSSr = 1397 |
| 17965 | CEFBS_HasSVE, // FABS_ZPmZ_D = 1398 |
| 17966 | CEFBS_HasSVE, // FABS_ZPmZ_H = 1399 |
| 17967 | CEFBS_HasSVE, // FABS_ZPmZ_S = 1400 |
| 17968 | CEFBS_HasNEON, // FABSv2f32 = 1401 |
| 17969 | CEFBS_HasNEON, // FABSv2f64 = 1402 |
| 17970 | CEFBS_HasNEON_HasFullFP16, // FABSv4f16 = 1403 |
| 17971 | CEFBS_HasNEON, // FABSv4f32 = 1404 |
| 17972 | CEFBS_HasNEON_HasFullFP16, // FABSv8f16 = 1405 |
| 17973 | CEFBS_HasNEON_HasFullFP16, // FACGE16 = 1406 |
| 17974 | CEFBS_HasNEON, // FACGE32 = 1407 |
| 17975 | CEFBS_HasNEON, // FACGE64 = 1408 |
| 17976 | CEFBS_HasSVE, // FACGE_PPzZZ_D = 1409 |
| 17977 | CEFBS_HasSVE, // FACGE_PPzZZ_H = 1410 |
| 17978 | CEFBS_HasSVE, // FACGE_PPzZZ_S = 1411 |
| 17979 | CEFBS_HasNEON, // FACGEv2f32 = 1412 |
| 17980 | CEFBS_HasNEON, // FACGEv2f64 = 1413 |
| 17981 | CEFBS_HasNEON_HasFullFP16, // FACGEv4f16 = 1414 |
| 17982 | CEFBS_HasNEON, // FACGEv4f32 = 1415 |
| 17983 | CEFBS_HasNEON_HasFullFP16, // FACGEv8f16 = 1416 |
| 17984 | CEFBS_HasNEON_HasFullFP16, // FACGT16 = 1417 |
| 17985 | CEFBS_HasNEON, // FACGT32 = 1418 |
| 17986 | CEFBS_HasNEON, // FACGT64 = 1419 |
| 17987 | CEFBS_HasSVE, // FACGT_PPzZZ_D = 1420 |
| 17988 | CEFBS_HasSVE, // FACGT_PPzZZ_H = 1421 |
| 17989 | CEFBS_HasSVE, // FACGT_PPzZZ_S = 1422 |
| 17990 | CEFBS_HasNEON, // FACGTv2f32 = 1423 |
| 17991 | CEFBS_HasNEON, // FACGTv2f64 = 1424 |
| 17992 | CEFBS_HasNEON_HasFullFP16, // FACGTv4f16 = 1425 |
| 17993 | CEFBS_HasNEON, // FACGTv4f32 = 1426 |
| 17994 | CEFBS_HasNEON_HasFullFP16, // FACGTv8f16 = 1427 |
| 17995 | CEFBS_HasSVE, // FADDA_VPZ_D = 1428 |
| 17996 | CEFBS_HasSVE, // FADDA_VPZ_H = 1429 |
| 17997 | CEFBS_HasSVE, // FADDA_VPZ_S = 1430 |
| 17998 | CEFBS_HasFPARMv8, // FADDDrr = 1431 |
| 17999 | CEFBS_HasFullFP16, // FADDHrr = 1432 |
| 18000 | CEFBS_HasSVE2, // FADDP_ZPmZZ_D = 1433 |
| 18001 | CEFBS_HasSVE2, // FADDP_ZPmZZ_H = 1434 |
| 18002 | CEFBS_HasSVE2, // FADDP_ZPmZZ_S = 1435 |
| 18003 | CEFBS_HasNEON, // FADDPv2f32 = 1436 |
| 18004 | CEFBS_HasNEON, // FADDPv2f64 = 1437 |
| 18005 | CEFBS_HasNEON_HasFullFP16, // FADDPv2i16p = 1438 |
| 18006 | CEFBS_HasNEON, // FADDPv2i32p = 1439 |
| 18007 | CEFBS_HasNEON, // FADDPv2i64p = 1440 |
| 18008 | CEFBS_HasNEON_HasFullFP16, // FADDPv4f16 = 1441 |
| 18009 | CEFBS_HasNEON, // FADDPv4f32 = 1442 |
| 18010 | CEFBS_HasNEON_HasFullFP16, // FADDPv8f16 = 1443 |
| 18011 | CEFBS_HasFPARMv8, // FADDSrr = 1444 |
| 18012 | CEFBS_HasSVE, // FADDV_VPZ_D = 1445 |
| 18013 | CEFBS_HasSVE, // FADDV_VPZ_H = 1446 |
| 18014 | CEFBS_HasSVE, // FADDV_VPZ_S = 1447 |
| 18015 | CEFBS_HasSVE, // FADD_ZPmI_D = 1448 |
| 18016 | CEFBS_HasSVE, // FADD_ZPmI_H = 1449 |
| 18017 | CEFBS_HasSVE, // FADD_ZPmI_S = 1450 |
| 18018 | CEFBS_HasSVE, // FADD_ZPmZ_D = 1451 |
| 18019 | CEFBS_HasSVE, // FADD_ZPmZ_H = 1452 |
| 18020 | CEFBS_HasSVE, // FADD_ZPmZ_S = 1453 |
| 18021 | CEFBS_HasSVE, // FADD_ZZZ_D = 1454 |
| 18022 | CEFBS_HasSVE, // FADD_ZZZ_H = 1455 |
| 18023 | CEFBS_HasSVE, // FADD_ZZZ_S = 1456 |
| 18024 | CEFBS_HasNEON, // FADDv2f32 = 1457 |
| 18025 | CEFBS_HasNEON, // FADDv2f64 = 1458 |
| 18026 | CEFBS_HasNEON_HasFullFP16, // FADDv4f16 = 1459 |
| 18027 | CEFBS_HasNEON, // FADDv4f32 = 1460 |
| 18028 | CEFBS_HasNEON_HasFullFP16, // FADDv8f16 = 1461 |
| 18029 | CEFBS_HasSVE, // FCADD_ZPmZ_D = 1462 |
| 18030 | CEFBS_HasSVE, // FCADD_ZPmZ_H = 1463 |
| 18031 | CEFBS_HasSVE, // FCADD_ZPmZ_S = 1464 |
| 18032 | CEFBS_HasComplxNum_HasNEON, // FCADDv2f32 = 1465 |
| 18033 | CEFBS_HasComplxNum_HasNEON, // FCADDv2f64 = 1466 |
| 18034 | CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCADDv4f16 = 1467 |
| 18035 | CEFBS_HasComplxNum_HasNEON, // FCADDv4f32 = 1468 |
| 18036 | CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCADDv8f16 = 1469 |
| 18037 | CEFBS_HasFPARMv8, // FCCMPDrr = 1470 |
| 18038 | CEFBS_HasFPARMv8, // FCCMPEDrr = 1471 |
| 18039 | CEFBS_HasFullFP16, // FCCMPEHrr = 1472 |
| 18040 | CEFBS_HasFPARMv8, // FCCMPESrr = 1473 |
| 18041 | CEFBS_HasFullFP16, // FCCMPHrr = 1474 |
| 18042 | CEFBS_HasFPARMv8, // FCCMPSrr = 1475 |
| 18043 | CEFBS_HasNEON_HasFullFP16, // FCMEQ16 = 1476 |
| 18044 | CEFBS_HasNEON, // FCMEQ32 = 1477 |
| 18045 | CEFBS_HasNEON, // FCMEQ64 = 1478 |
| 18046 | CEFBS_HasSVE, // FCMEQ_PPzZ0_D = 1479 |
| 18047 | CEFBS_HasSVE, // FCMEQ_PPzZ0_H = 1480 |
| 18048 | CEFBS_HasSVE, // FCMEQ_PPzZ0_S = 1481 |
| 18049 | CEFBS_HasSVE, // FCMEQ_PPzZZ_D = 1482 |
| 18050 | CEFBS_HasSVE, // FCMEQ_PPzZZ_H = 1483 |
| 18051 | CEFBS_HasSVE, // FCMEQ_PPzZZ_S = 1484 |
| 18052 | CEFBS_HasNEON_HasFullFP16, // FCMEQv1i16rz = 1485 |
| 18053 | CEFBS_HasNEON, // FCMEQv1i32rz = 1486 |
| 18054 | CEFBS_HasNEON, // FCMEQv1i64rz = 1487 |
| 18055 | CEFBS_HasNEON, // FCMEQv2f32 = 1488 |
| 18056 | CEFBS_HasNEON, // FCMEQv2f64 = 1489 |
| 18057 | CEFBS_HasNEON, // FCMEQv2i32rz = 1490 |
| 18058 | CEFBS_HasNEON, // FCMEQv2i64rz = 1491 |
| 18059 | CEFBS_HasNEON_HasFullFP16, // FCMEQv4f16 = 1492 |
| 18060 | CEFBS_HasNEON, // FCMEQv4f32 = 1493 |
| 18061 | CEFBS_HasNEON_HasFullFP16, // FCMEQv4i16rz = 1494 |
| 18062 | CEFBS_HasNEON, // FCMEQv4i32rz = 1495 |
| 18063 | CEFBS_HasNEON_HasFullFP16, // FCMEQv8f16 = 1496 |
| 18064 | CEFBS_HasNEON_HasFullFP16, // FCMEQv8i16rz = 1497 |
| 18065 | CEFBS_HasNEON_HasFullFP16, // FCMGE16 = 1498 |
| 18066 | CEFBS_HasNEON, // FCMGE32 = 1499 |
| 18067 | CEFBS_HasNEON, // FCMGE64 = 1500 |
| 18068 | CEFBS_HasSVE, // FCMGE_PPzZ0_D = 1501 |
| 18069 | CEFBS_HasSVE, // FCMGE_PPzZ0_H = 1502 |
| 18070 | CEFBS_HasSVE, // FCMGE_PPzZ0_S = 1503 |
| 18071 | CEFBS_HasSVE, // FCMGE_PPzZZ_D = 1504 |
| 18072 | CEFBS_HasSVE, // FCMGE_PPzZZ_H = 1505 |
| 18073 | CEFBS_HasSVE, // FCMGE_PPzZZ_S = 1506 |
| 18074 | CEFBS_HasNEON_HasFullFP16, // FCMGEv1i16rz = 1507 |
| 18075 | CEFBS_HasNEON, // FCMGEv1i32rz = 1508 |
| 18076 | CEFBS_HasNEON, // FCMGEv1i64rz = 1509 |
| 18077 | CEFBS_HasNEON, // FCMGEv2f32 = 1510 |
| 18078 | CEFBS_HasNEON, // FCMGEv2f64 = 1511 |
| 18079 | CEFBS_HasNEON, // FCMGEv2i32rz = 1512 |
| 18080 | CEFBS_HasNEON, // FCMGEv2i64rz = 1513 |
| 18081 | CEFBS_HasNEON_HasFullFP16, // FCMGEv4f16 = 1514 |
| 18082 | CEFBS_HasNEON, // FCMGEv4f32 = 1515 |
| 18083 | CEFBS_HasNEON_HasFullFP16, // FCMGEv4i16rz = 1516 |
| 18084 | CEFBS_HasNEON, // FCMGEv4i32rz = 1517 |
| 18085 | CEFBS_HasNEON_HasFullFP16, // FCMGEv8f16 = 1518 |
| 18086 | CEFBS_HasNEON_HasFullFP16, // FCMGEv8i16rz = 1519 |
| 18087 | CEFBS_HasNEON_HasFullFP16, // FCMGT16 = 1520 |
| 18088 | CEFBS_HasNEON, // FCMGT32 = 1521 |
| 18089 | CEFBS_HasNEON, // FCMGT64 = 1522 |
| 18090 | CEFBS_HasSVE, // FCMGT_PPzZ0_D = 1523 |
| 18091 | CEFBS_HasSVE, // FCMGT_PPzZ0_H = 1524 |
| 18092 | CEFBS_HasSVE, // FCMGT_PPzZ0_S = 1525 |
| 18093 | CEFBS_HasSVE, // FCMGT_PPzZZ_D = 1526 |
| 18094 | CEFBS_HasSVE, // FCMGT_PPzZZ_H = 1527 |
| 18095 | CEFBS_HasSVE, // FCMGT_PPzZZ_S = 1528 |
| 18096 | CEFBS_HasNEON_HasFullFP16, // FCMGTv1i16rz = 1529 |
| 18097 | CEFBS_HasNEON, // FCMGTv1i32rz = 1530 |
| 18098 | CEFBS_HasNEON, // FCMGTv1i64rz = 1531 |
| 18099 | CEFBS_HasNEON, // FCMGTv2f32 = 1532 |
| 18100 | CEFBS_HasNEON, // FCMGTv2f64 = 1533 |
| 18101 | CEFBS_HasNEON, // FCMGTv2i32rz = 1534 |
| 18102 | CEFBS_HasNEON, // FCMGTv2i64rz = 1535 |
| 18103 | CEFBS_HasNEON_HasFullFP16, // FCMGTv4f16 = 1536 |
| 18104 | CEFBS_HasNEON, // FCMGTv4f32 = 1537 |
| 18105 | CEFBS_HasNEON_HasFullFP16, // FCMGTv4i16rz = 1538 |
| 18106 | CEFBS_HasNEON, // FCMGTv4i32rz = 1539 |
| 18107 | CEFBS_HasNEON_HasFullFP16, // FCMGTv8f16 = 1540 |
| 18108 | CEFBS_HasNEON_HasFullFP16, // FCMGTv8i16rz = 1541 |
| 18109 | CEFBS_HasSVE, // FCMLA_ZPmZZ_D = 1542 |
| 18110 | CEFBS_HasSVE, // FCMLA_ZPmZZ_H = 1543 |
| 18111 | CEFBS_HasSVE, // FCMLA_ZPmZZ_S = 1544 |
| 18112 | CEFBS_HasSVE, // FCMLA_ZZZI_H = 1545 |
| 18113 | CEFBS_HasSVE, // FCMLA_ZZZI_S = 1546 |
| 18114 | CEFBS_HasComplxNum_HasNEON, // FCMLAv2f32 = 1547 |
| 18115 | CEFBS_HasComplxNum_HasNEON, // FCMLAv2f64 = 1548 |
| 18116 | CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCMLAv4f16 = 1549 |
| 18117 | CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCMLAv4f16_indexed = 1550 |
| 18118 | CEFBS_HasComplxNum_HasNEON, // FCMLAv4f32 = 1551 |
| 18119 | CEFBS_HasComplxNum_HasNEON, // FCMLAv4f32_indexed = 1552 |
| 18120 | CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCMLAv8f16 = 1553 |
| 18121 | CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCMLAv8f16_indexed = 1554 |
| 18122 | CEFBS_HasSVE, // FCMLE_PPzZ0_D = 1555 |
| 18123 | CEFBS_HasSVE, // FCMLE_PPzZ0_H = 1556 |
| 18124 | CEFBS_HasSVE, // FCMLE_PPzZ0_S = 1557 |
| 18125 | CEFBS_HasNEON_HasFullFP16, // FCMLEv1i16rz = 1558 |
| 18126 | CEFBS_HasNEON, // FCMLEv1i32rz = 1559 |
| 18127 | CEFBS_HasNEON, // FCMLEv1i64rz = 1560 |
| 18128 | CEFBS_HasNEON, // FCMLEv2i32rz = 1561 |
| 18129 | CEFBS_HasNEON, // FCMLEv2i64rz = 1562 |
| 18130 | CEFBS_HasNEON_HasFullFP16, // FCMLEv4i16rz = 1563 |
| 18131 | CEFBS_HasNEON, // FCMLEv4i32rz = 1564 |
| 18132 | CEFBS_HasNEON_HasFullFP16, // FCMLEv8i16rz = 1565 |
| 18133 | CEFBS_HasSVE, // FCMLT_PPzZ0_D = 1566 |
| 18134 | CEFBS_HasSVE, // FCMLT_PPzZ0_H = 1567 |
| 18135 | CEFBS_HasSVE, // FCMLT_PPzZ0_S = 1568 |
| 18136 | CEFBS_HasNEON_HasFullFP16, // FCMLTv1i16rz = 1569 |
| 18137 | CEFBS_HasNEON, // FCMLTv1i32rz = 1570 |
| 18138 | CEFBS_HasNEON, // FCMLTv1i64rz = 1571 |
| 18139 | CEFBS_HasNEON, // FCMLTv2i32rz = 1572 |
| 18140 | CEFBS_HasNEON, // FCMLTv2i64rz = 1573 |
| 18141 | CEFBS_HasNEON_HasFullFP16, // FCMLTv4i16rz = 1574 |
| 18142 | CEFBS_HasNEON, // FCMLTv4i32rz = 1575 |
| 18143 | CEFBS_HasNEON_HasFullFP16, // FCMLTv8i16rz = 1576 |
| 18144 | CEFBS_HasSVE, // FCMNE_PPzZ0_D = 1577 |
| 18145 | CEFBS_HasSVE, // FCMNE_PPzZ0_H = 1578 |
| 18146 | CEFBS_HasSVE, // FCMNE_PPzZ0_S = 1579 |
| 18147 | CEFBS_HasSVE, // FCMNE_PPzZZ_D = 1580 |
| 18148 | CEFBS_HasSVE, // FCMNE_PPzZZ_H = 1581 |
| 18149 | CEFBS_HasSVE, // FCMNE_PPzZZ_S = 1582 |
| 18150 | CEFBS_HasFPARMv8, // FCMPDri = 1583 |
| 18151 | CEFBS_HasFPARMv8, // FCMPDrr = 1584 |
| 18152 | CEFBS_HasFPARMv8, // FCMPEDri = 1585 |
| 18153 | CEFBS_HasFPARMv8, // FCMPEDrr = 1586 |
| 18154 | CEFBS_HasFullFP16, // FCMPEHri = 1587 |
| 18155 | CEFBS_HasFullFP16, // FCMPEHrr = 1588 |
| 18156 | CEFBS_HasFPARMv8, // FCMPESri = 1589 |
| 18157 | CEFBS_HasFPARMv8, // FCMPESrr = 1590 |
| 18158 | CEFBS_HasFullFP16, // FCMPHri = 1591 |
| 18159 | CEFBS_HasFullFP16, // FCMPHrr = 1592 |
| 18160 | CEFBS_HasFPARMv8, // FCMPSri = 1593 |
| 18161 | CEFBS_HasFPARMv8, // FCMPSrr = 1594 |
| 18162 | CEFBS_HasSVE, // FCMUO_PPzZZ_D = 1595 |
| 18163 | CEFBS_HasSVE, // FCMUO_PPzZZ_H = 1596 |
| 18164 | CEFBS_HasSVE, // FCMUO_PPzZZ_S = 1597 |
| 18165 | CEFBS_HasSVE, // FCPY_ZPmI_D = 1598 |
| 18166 | CEFBS_HasSVE, // FCPY_ZPmI_H = 1599 |
| 18167 | CEFBS_HasSVE, // FCPY_ZPmI_S = 1600 |
| 18168 | CEFBS_HasFPARMv8, // FCSELDrrr = 1601 |
| 18169 | CEFBS_HasFullFP16, // FCSELHrrr = 1602 |
| 18170 | CEFBS_HasFPARMv8, // FCSELSrrr = 1603 |
| 18171 | CEFBS_HasFPARMv8, // FCVTASUWDr = 1604 |
| 18172 | CEFBS_HasFullFP16, // FCVTASUWHr = 1605 |
| 18173 | CEFBS_HasFPARMv8, // FCVTASUWSr = 1606 |
| 18174 | CEFBS_HasFPARMv8, // FCVTASUXDr = 1607 |
| 18175 | CEFBS_HasFullFP16, // FCVTASUXHr = 1608 |
| 18176 | CEFBS_HasFPARMv8, // FCVTASUXSr = 1609 |
| 18177 | CEFBS_HasNEON_HasFullFP16, // FCVTASv1f16 = 1610 |
| 18178 | CEFBS_HasNEON, // FCVTASv1i32 = 1611 |
| 18179 | CEFBS_HasNEON, // FCVTASv1i64 = 1612 |
| 18180 | CEFBS_HasNEON, // FCVTASv2f32 = 1613 |
| 18181 | CEFBS_HasNEON, // FCVTASv2f64 = 1614 |
| 18182 | CEFBS_HasNEON_HasFullFP16, // FCVTASv4f16 = 1615 |
| 18183 | CEFBS_HasNEON, // FCVTASv4f32 = 1616 |
| 18184 | CEFBS_HasNEON_HasFullFP16, // FCVTASv8f16 = 1617 |
| 18185 | CEFBS_HasFPARMv8, // FCVTAUUWDr = 1618 |
| 18186 | CEFBS_HasFullFP16, // FCVTAUUWHr = 1619 |
| 18187 | CEFBS_HasFPARMv8, // FCVTAUUWSr = 1620 |
| 18188 | CEFBS_HasFPARMv8, // FCVTAUUXDr = 1621 |
| 18189 | CEFBS_HasFullFP16, // FCVTAUUXHr = 1622 |
| 18190 | CEFBS_HasFPARMv8, // FCVTAUUXSr = 1623 |
| 18191 | CEFBS_HasNEON_HasFullFP16, // FCVTAUv1f16 = 1624 |
| 18192 | CEFBS_HasNEON, // FCVTAUv1i32 = 1625 |
| 18193 | CEFBS_HasNEON, // FCVTAUv1i64 = 1626 |
| 18194 | CEFBS_HasNEON, // FCVTAUv2f32 = 1627 |
| 18195 | CEFBS_HasNEON, // FCVTAUv2f64 = 1628 |
| 18196 | CEFBS_HasNEON_HasFullFP16, // FCVTAUv4f16 = 1629 |
| 18197 | CEFBS_HasNEON, // FCVTAUv4f32 = 1630 |
| 18198 | CEFBS_HasNEON_HasFullFP16, // FCVTAUv8f16 = 1631 |
| 18199 | CEFBS_HasFPARMv8, // FCVTDHr = 1632 |
| 18200 | CEFBS_HasFPARMv8, // FCVTDSr = 1633 |
| 18201 | CEFBS_HasFPARMv8, // FCVTHDr = 1634 |
| 18202 | CEFBS_HasFPARMv8, // FCVTHSr = 1635 |
| 18203 | CEFBS_HasSVE2, // FCVTLT_ZPmZ_HtoS = 1636 |
| 18204 | CEFBS_HasSVE2, // FCVTLT_ZPmZ_StoD = 1637 |
| 18205 | CEFBS_HasNEON, // FCVTLv2i32 = 1638 |
| 18206 | CEFBS_HasNEON, // FCVTLv4i16 = 1639 |
| 18207 | CEFBS_HasNEON, // FCVTLv4i32 = 1640 |
| 18208 | CEFBS_HasNEON, // FCVTLv8i16 = 1641 |
| 18209 | CEFBS_HasFPARMv8, // FCVTMSUWDr = 1642 |
| 18210 | CEFBS_HasFullFP16, // FCVTMSUWHr = 1643 |
| 18211 | CEFBS_HasFPARMv8, // FCVTMSUWSr = 1644 |
| 18212 | CEFBS_HasFPARMv8, // FCVTMSUXDr = 1645 |
| 18213 | CEFBS_HasFullFP16, // FCVTMSUXHr = 1646 |
| 18214 | CEFBS_HasFPARMv8, // FCVTMSUXSr = 1647 |
| 18215 | CEFBS_HasNEON_HasFullFP16, // FCVTMSv1f16 = 1648 |
| 18216 | CEFBS_HasNEON, // FCVTMSv1i32 = 1649 |
| 18217 | CEFBS_HasNEON, // FCVTMSv1i64 = 1650 |
| 18218 | CEFBS_HasNEON, // FCVTMSv2f32 = 1651 |
| 18219 | CEFBS_HasNEON, // FCVTMSv2f64 = 1652 |
| 18220 | CEFBS_HasNEON_HasFullFP16, // FCVTMSv4f16 = 1653 |
| 18221 | CEFBS_HasNEON, // FCVTMSv4f32 = 1654 |
| 18222 | CEFBS_HasNEON_HasFullFP16, // FCVTMSv8f16 = 1655 |
| 18223 | CEFBS_HasFPARMv8, // FCVTMUUWDr = 1656 |
| 18224 | CEFBS_HasFullFP16, // FCVTMUUWHr = 1657 |
| 18225 | CEFBS_HasFPARMv8, // FCVTMUUWSr = 1658 |
| 18226 | CEFBS_HasFPARMv8, // FCVTMUUXDr = 1659 |
| 18227 | CEFBS_HasFullFP16, // FCVTMUUXHr = 1660 |
| 18228 | CEFBS_HasFPARMv8, // FCVTMUUXSr = 1661 |
| 18229 | CEFBS_HasNEON_HasFullFP16, // FCVTMUv1f16 = 1662 |
| 18230 | CEFBS_HasNEON, // FCVTMUv1i32 = 1663 |
| 18231 | CEFBS_HasNEON, // FCVTMUv1i64 = 1664 |
| 18232 | CEFBS_HasNEON, // FCVTMUv2f32 = 1665 |
| 18233 | CEFBS_HasNEON, // FCVTMUv2f64 = 1666 |
| 18234 | CEFBS_HasNEON_HasFullFP16, // FCVTMUv4f16 = 1667 |
| 18235 | CEFBS_HasNEON, // FCVTMUv4f32 = 1668 |
| 18236 | CEFBS_HasNEON_HasFullFP16, // FCVTMUv8f16 = 1669 |
| 18237 | CEFBS_HasFPARMv8, // FCVTNSUWDr = 1670 |
| 18238 | CEFBS_HasFullFP16, // FCVTNSUWHr = 1671 |
| 18239 | CEFBS_HasFPARMv8, // FCVTNSUWSr = 1672 |
| 18240 | CEFBS_HasFPARMv8, // FCVTNSUXDr = 1673 |
| 18241 | CEFBS_HasFullFP16, // FCVTNSUXHr = 1674 |
| 18242 | CEFBS_HasFPARMv8, // FCVTNSUXSr = 1675 |
| 18243 | CEFBS_HasNEON_HasFullFP16, // FCVTNSv1f16 = 1676 |
| 18244 | CEFBS_HasNEON, // FCVTNSv1i32 = 1677 |
| 18245 | CEFBS_HasNEON, // FCVTNSv1i64 = 1678 |
| 18246 | CEFBS_HasNEON, // FCVTNSv2f32 = 1679 |
| 18247 | CEFBS_HasNEON, // FCVTNSv2f64 = 1680 |
| 18248 | CEFBS_HasNEON_HasFullFP16, // FCVTNSv4f16 = 1681 |
| 18249 | CEFBS_HasNEON, // FCVTNSv4f32 = 1682 |
| 18250 | CEFBS_HasNEON_HasFullFP16, // FCVTNSv8f16 = 1683 |
| 18251 | CEFBS_HasSVE2, // FCVTNT_ZPmZ_DtoS = 1684 |
| 18252 | CEFBS_HasSVE2, // FCVTNT_ZPmZ_StoH = 1685 |
| 18253 | CEFBS_HasFPARMv8, // FCVTNUUWDr = 1686 |
| 18254 | CEFBS_HasFullFP16, // FCVTNUUWHr = 1687 |
| 18255 | CEFBS_HasFPARMv8, // FCVTNUUWSr = 1688 |
| 18256 | CEFBS_HasFPARMv8, // FCVTNUUXDr = 1689 |
| 18257 | CEFBS_HasFullFP16, // FCVTNUUXHr = 1690 |
| 18258 | CEFBS_HasFPARMv8, // FCVTNUUXSr = 1691 |
| 18259 | CEFBS_HasNEON_HasFullFP16, // FCVTNUv1f16 = 1692 |
| 18260 | CEFBS_HasNEON, // FCVTNUv1i32 = 1693 |
| 18261 | CEFBS_HasNEON, // FCVTNUv1i64 = 1694 |
| 18262 | CEFBS_HasNEON, // FCVTNUv2f32 = 1695 |
| 18263 | CEFBS_HasNEON, // FCVTNUv2f64 = 1696 |
| 18264 | CEFBS_HasNEON_HasFullFP16, // FCVTNUv4f16 = 1697 |
| 18265 | CEFBS_HasNEON, // FCVTNUv4f32 = 1698 |
| 18266 | CEFBS_HasNEON_HasFullFP16, // FCVTNUv8f16 = 1699 |
| 18267 | CEFBS_HasNEON, // FCVTNv2i32 = 1700 |
| 18268 | CEFBS_HasNEON, // FCVTNv4i16 = 1701 |
| 18269 | CEFBS_HasNEON, // FCVTNv4i32 = 1702 |
| 18270 | CEFBS_HasNEON, // FCVTNv8i16 = 1703 |
| 18271 | CEFBS_HasFPARMv8, // FCVTPSUWDr = 1704 |
| 18272 | CEFBS_HasFullFP16, // FCVTPSUWHr = 1705 |
| 18273 | CEFBS_HasFPARMv8, // FCVTPSUWSr = 1706 |
| 18274 | CEFBS_HasFPARMv8, // FCVTPSUXDr = 1707 |
| 18275 | CEFBS_HasFullFP16, // FCVTPSUXHr = 1708 |
| 18276 | CEFBS_HasFPARMv8, // FCVTPSUXSr = 1709 |
| 18277 | CEFBS_HasNEON_HasFullFP16, // FCVTPSv1f16 = 1710 |
| 18278 | CEFBS_HasNEON, // FCVTPSv1i32 = 1711 |
| 18279 | CEFBS_HasNEON, // FCVTPSv1i64 = 1712 |
| 18280 | CEFBS_HasNEON, // FCVTPSv2f32 = 1713 |
| 18281 | CEFBS_HasNEON, // FCVTPSv2f64 = 1714 |
| 18282 | CEFBS_HasNEON_HasFullFP16, // FCVTPSv4f16 = 1715 |
| 18283 | CEFBS_HasNEON, // FCVTPSv4f32 = 1716 |
| 18284 | CEFBS_HasNEON_HasFullFP16, // FCVTPSv8f16 = 1717 |
| 18285 | CEFBS_HasFPARMv8, // FCVTPUUWDr = 1718 |
| 18286 | CEFBS_HasFullFP16, // FCVTPUUWHr = 1719 |
| 18287 | CEFBS_HasFPARMv8, // FCVTPUUWSr = 1720 |
| 18288 | CEFBS_HasFPARMv8, // FCVTPUUXDr = 1721 |
| 18289 | CEFBS_HasFullFP16, // FCVTPUUXHr = 1722 |
| 18290 | CEFBS_HasFPARMv8, // FCVTPUUXSr = 1723 |
| 18291 | CEFBS_HasNEON_HasFullFP16, // FCVTPUv1f16 = 1724 |
| 18292 | CEFBS_HasNEON, // FCVTPUv1i32 = 1725 |
| 18293 | CEFBS_HasNEON, // FCVTPUv1i64 = 1726 |
| 18294 | CEFBS_HasNEON, // FCVTPUv2f32 = 1727 |
| 18295 | CEFBS_HasNEON, // FCVTPUv2f64 = 1728 |
| 18296 | CEFBS_HasNEON_HasFullFP16, // FCVTPUv4f16 = 1729 |
| 18297 | CEFBS_HasNEON, // FCVTPUv4f32 = 1730 |
| 18298 | CEFBS_HasNEON_HasFullFP16, // FCVTPUv8f16 = 1731 |
| 18299 | CEFBS_HasFPARMv8, // FCVTSDr = 1732 |
| 18300 | CEFBS_HasFPARMv8, // FCVTSHr = 1733 |
| 18301 | CEFBS_HasSVE2, // FCVTXNT_ZPmZ_DtoS = 1734 |
| 18302 | CEFBS_HasNEON, // FCVTXNv1i64 = 1735 |
| 18303 | CEFBS_HasNEON, // FCVTXNv2f32 = 1736 |
| 18304 | CEFBS_HasNEON, // FCVTXNv4f32 = 1737 |
| 18305 | CEFBS_HasSVE2, // FCVTX_ZPmZ_DtoS = 1738 |
| 18306 | CEFBS_HasFPARMv8, // FCVTZSSWDri = 1739 |
| 18307 | CEFBS_HasFullFP16, // FCVTZSSWHri = 1740 |
| 18308 | CEFBS_HasFPARMv8, // FCVTZSSWSri = 1741 |
| 18309 | CEFBS_HasFPARMv8, // FCVTZSSXDri = 1742 |
| 18310 | CEFBS_HasFullFP16, // FCVTZSSXHri = 1743 |
| 18311 | CEFBS_HasFPARMv8, // FCVTZSSXSri = 1744 |
| 18312 | CEFBS_HasFPARMv8, // FCVTZSUWDr = 1745 |
| 18313 | CEFBS_HasFullFP16, // FCVTZSUWHr = 1746 |
| 18314 | CEFBS_HasFPARMv8, // FCVTZSUWSr = 1747 |
| 18315 | CEFBS_HasFPARMv8, // FCVTZSUXDr = 1748 |
| 18316 | CEFBS_HasFullFP16, // FCVTZSUXHr = 1749 |
| 18317 | CEFBS_HasFPARMv8, // FCVTZSUXSr = 1750 |
| 18318 | CEFBS_HasSVE, // FCVTZS_ZPmZ_DtoD = 1751 |
| 18319 | CEFBS_HasSVE, // FCVTZS_ZPmZ_DtoS = 1752 |
| 18320 | CEFBS_HasSVE, // FCVTZS_ZPmZ_HtoD = 1753 |
| 18321 | CEFBS_HasSVE, // FCVTZS_ZPmZ_HtoH = 1754 |
| 18322 | CEFBS_HasSVE, // FCVTZS_ZPmZ_HtoS = 1755 |
| 18323 | CEFBS_HasSVE, // FCVTZS_ZPmZ_StoD = 1756 |
| 18324 | CEFBS_HasSVE, // FCVTZS_ZPmZ_StoS = 1757 |
| 18325 | CEFBS_HasNEON, // FCVTZSd = 1758 |
| 18326 | CEFBS_HasNEON_HasFullFP16, // FCVTZSh = 1759 |
| 18327 | CEFBS_HasNEON, // FCVTZSs = 1760 |
| 18328 | CEFBS_HasNEON_HasFullFP16, // FCVTZSv1f16 = 1761 |
| 18329 | CEFBS_HasNEON, // FCVTZSv1i32 = 1762 |
| 18330 | CEFBS_HasNEON, // FCVTZSv1i64 = 1763 |
| 18331 | CEFBS_HasNEON, // FCVTZSv2f32 = 1764 |
| 18332 | CEFBS_HasNEON, // FCVTZSv2f64 = 1765 |
| 18333 | CEFBS_HasNEON, // FCVTZSv2i32_shift = 1766 |
| 18334 | CEFBS_HasNEON, // FCVTZSv2i64_shift = 1767 |
| 18335 | CEFBS_HasNEON_HasFullFP16, // FCVTZSv4f16 = 1768 |
| 18336 | CEFBS_HasNEON, // FCVTZSv4f32 = 1769 |
| 18337 | CEFBS_HasNEON_HasFullFP16, // FCVTZSv4i16_shift = 1770 |
| 18338 | CEFBS_HasNEON, // FCVTZSv4i32_shift = 1771 |
| 18339 | CEFBS_HasNEON_HasFullFP16, // FCVTZSv8f16 = 1772 |
| 18340 | CEFBS_HasNEON_HasFullFP16, // FCVTZSv8i16_shift = 1773 |
| 18341 | CEFBS_HasFPARMv8, // FCVTZUSWDri = 1774 |
| 18342 | CEFBS_HasFullFP16, // FCVTZUSWHri = 1775 |
| 18343 | CEFBS_HasFPARMv8, // FCVTZUSWSri = 1776 |
| 18344 | CEFBS_HasFPARMv8, // FCVTZUSXDri = 1777 |
| 18345 | CEFBS_HasFullFP16, // FCVTZUSXHri = 1778 |
| 18346 | CEFBS_HasFPARMv8, // FCVTZUSXSri = 1779 |
| 18347 | CEFBS_HasFPARMv8, // FCVTZUUWDr = 1780 |
| 18348 | CEFBS_HasFullFP16, // FCVTZUUWHr = 1781 |
| 18349 | CEFBS_HasFPARMv8, // FCVTZUUWSr = 1782 |
| 18350 | CEFBS_HasFPARMv8, // FCVTZUUXDr = 1783 |
| 18351 | CEFBS_HasFullFP16, // FCVTZUUXHr = 1784 |
| 18352 | CEFBS_HasFPARMv8, // FCVTZUUXSr = 1785 |
| 18353 | CEFBS_HasSVE, // FCVTZU_ZPmZ_DtoD = 1786 |
| 18354 | CEFBS_HasSVE, // FCVTZU_ZPmZ_DtoS = 1787 |
| 18355 | CEFBS_HasSVE, // FCVTZU_ZPmZ_HtoD = 1788 |
| 18356 | CEFBS_HasSVE, // FCVTZU_ZPmZ_HtoH = 1789 |
| 18357 | CEFBS_HasSVE, // FCVTZU_ZPmZ_HtoS = 1790 |
| 18358 | CEFBS_HasSVE, // FCVTZU_ZPmZ_StoD = 1791 |
| 18359 | CEFBS_HasSVE, // FCVTZU_ZPmZ_StoS = 1792 |
| 18360 | CEFBS_HasNEON, // FCVTZUd = 1793 |
| 18361 | CEFBS_HasNEON_HasFullFP16, // FCVTZUh = 1794 |
| 18362 | CEFBS_HasNEON, // FCVTZUs = 1795 |
| 18363 | CEFBS_HasNEON_HasFullFP16, // FCVTZUv1f16 = 1796 |
| 18364 | CEFBS_HasNEON, // FCVTZUv1i32 = 1797 |
| 18365 | CEFBS_HasNEON, // FCVTZUv1i64 = 1798 |
| 18366 | CEFBS_HasNEON, // FCVTZUv2f32 = 1799 |
| 18367 | CEFBS_HasNEON, // FCVTZUv2f64 = 1800 |
| 18368 | CEFBS_HasNEON, // FCVTZUv2i32_shift = 1801 |
| 18369 | CEFBS_HasNEON, // FCVTZUv2i64_shift = 1802 |
| 18370 | CEFBS_HasNEON_HasFullFP16, // FCVTZUv4f16 = 1803 |
| 18371 | CEFBS_HasNEON, // FCVTZUv4f32 = 1804 |
| 18372 | CEFBS_HasNEON_HasFullFP16, // FCVTZUv4i16_shift = 1805 |
| 18373 | CEFBS_HasNEON, // FCVTZUv4i32_shift = 1806 |
| 18374 | CEFBS_HasNEON_HasFullFP16, // FCVTZUv8f16 = 1807 |
| 18375 | CEFBS_HasNEON_HasFullFP16, // FCVTZUv8i16_shift = 1808 |
| 18376 | CEFBS_HasSVE, // FCVT_ZPmZ_DtoH = 1809 |
| 18377 | CEFBS_HasSVE, // FCVT_ZPmZ_DtoS = 1810 |
| 18378 | CEFBS_HasSVE, // FCVT_ZPmZ_HtoD = 1811 |
| 18379 | CEFBS_HasSVE, // FCVT_ZPmZ_HtoS = 1812 |
| 18380 | CEFBS_HasSVE, // FCVT_ZPmZ_StoD = 1813 |
| 18381 | CEFBS_HasSVE, // FCVT_ZPmZ_StoH = 1814 |
| 18382 | CEFBS_HasFPARMv8, // FDIVDrr = 1815 |
| 18383 | CEFBS_HasFullFP16, // FDIVHrr = 1816 |
| 18384 | CEFBS_HasSVE, // FDIVR_ZPmZ_D = 1817 |
| 18385 | CEFBS_HasSVE, // FDIVR_ZPmZ_H = 1818 |
| 18386 | CEFBS_HasSVE, // FDIVR_ZPmZ_S = 1819 |
| 18387 | CEFBS_HasFPARMv8, // FDIVSrr = 1820 |
| 18388 | CEFBS_HasSVE, // FDIV_ZPmZ_D = 1821 |
| 18389 | CEFBS_HasSVE, // FDIV_ZPmZ_H = 1822 |
| 18390 | CEFBS_HasSVE, // FDIV_ZPmZ_S = 1823 |
| 18391 | CEFBS_HasNEON, // FDIVv2f32 = 1824 |
| 18392 | CEFBS_HasNEON, // FDIVv2f64 = 1825 |
| 18393 | CEFBS_HasNEON_HasFullFP16, // FDIVv4f16 = 1826 |
| 18394 | CEFBS_HasNEON, // FDIVv4f32 = 1827 |
| 18395 | CEFBS_HasNEON_HasFullFP16, // FDIVv8f16 = 1828 |
| 18396 | CEFBS_HasSVE, // FDUP_ZI_D = 1829 |
| 18397 | CEFBS_HasSVE, // FDUP_ZI_H = 1830 |
| 18398 | CEFBS_HasSVE, // FDUP_ZI_S = 1831 |
| 18399 | CEFBS_HasSVE, // FEXPA_ZZ_D = 1832 |
| 18400 | CEFBS_HasSVE, // FEXPA_ZZ_H = 1833 |
| 18401 | CEFBS_HasSVE, // FEXPA_ZZ_S = 1834 |
| 18402 | CEFBS_HasJS_HasFPARMv8, // FJCVTZS = 1835 |
| 18403 | CEFBS_HasSVE2, // FLOGB_ZPmZ_D = 1836 |
| 18404 | CEFBS_HasSVE2, // FLOGB_ZPmZ_H = 1837 |
| 18405 | CEFBS_HasSVE2, // FLOGB_ZPmZ_S = 1838 |
| 18406 | CEFBS_HasFPARMv8, // FMADDDrrr = 1839 |
| 18407 | CEFBS_HasFullFP16, // FMADDHrrr = 1840 |
| 18408 | CEFBS_HasFPARMv8, // FMADDSrrr = 1841 |
| 18409 | CEFBS_HasSVE, // FMAD_ZPmZZ_D = 1842 |
| 18410 | CEFBS_HasSVE, // FMAD_ZPmZZ_H = 1843 |
| 18411 | CEFBS_HasSVE, // FMAD_ZPmZZ_S = 1844 |
| 18412 | CEFBS_HasFPARMv8, // FMAXDrr = 1845 |
| 18413 | CEFBS_HasFullFP16, // FMAXHrr = 1846 |
| 18414 | CEFBS_HasFPARMv8, // FMAXNMDrr = 1847 |
| 18415 | CEFBS_HasFullFP16, // FMAXNMHrr = 1848 |
| 18416 | CEFBS_HasSVE2, // FMAXNMP_ZPmZZ_D = 1849 |
| 18417 | CEFBS_HasSVE2, // FMAXNMP_ZPmZZ_H = 1850 |
| 18418 | CEFBS_HasSVE2, // FMAXNMP_ZPmZZ_S = 1851 |
| 18419 | CEFBS_HasNEON, // FMAXNMPv2f32 = 1852 |
| 18420 | CEFBS_HasNEON, // FMAXNMPv2f64 = 1853 |
| 18421 | CEFBS_HasNEON_HasFullFP16, // FMAXNMPv2i16p = 1854 |
| 18422 | CEFBS_HasNEON, // FMAXNMPv2i32p = 1855 |
| 18423 | CEFBS_HasNEON, // FMAXNMPv2i64p = 1856 |
| 18424 | CEFBS_HasNEON_HasFullFP16, // FMAXNMPv4f16 = 1857 |
| 18425 | CEFBS_HasNEON, // FMAXNMPv4f32 = 1858 |
| 18426 | CEFBS_HasNEON_HasFullFP16, // FMAXNMPv8f16 = 1859 |
| 18427 | CEFBS_HasFPARMv8, // FMAXNMSrr = 1860 |
| 18428 | CEFBS_HasSVE, // FMAXNMV_VPZ_D = 1861 |
| 18429 | CEFBS_HasSVE, // FMAXNMV_VPZ_H = 1862 |
| 18430 | CEFBS_HasSVE, // FMAXNMV_VPZ_S = 1863 |
| 18431 | CEFBS_HasNEON_HasFullFP16, // FMAXNMVv4i16v = 1864 |
| 18432 | CEFBS_HasNEON, // FMAXNMVv4i32v = 1865 |
| 18433 | CEFBS_HasNEON_HasFullFP16, // FMAXNMVv8i16v = 1866 |
| 18434 | CEFBS_HasSVE, // FMAXNM_ZPmI_D = 1867 |
| 18435 | CEFBS_HasSVE, // FMAXNM_ZPmI_H = 1868 |
| 18436 | CEFBS_HasSVE, // FMAXNM_ZPmI_S = 1869 |
| 18437 | CEFBS_HasSVE, // FMAXNM_ZPmZ_D = 1870 |
| 18438 | CEFBS_HasSVE, // FMAXNM_ZPmZ_H = 1871 |
| 18439 | CEFBS_HasSVE, // FMAXNM_ZPmZ_S = 1872 |
| 18440 | CEFBS_HasNEON, // FMAXNMv2f32 = 1873 |
| 18441 | CEFBS_HasNEON, // FMAXNMv2f64 = 1874 |
| 18442 | CEFBS_HasNEON_HasFullFP16, // FMAXNMv4f16 = 1875 |
| 18443 | CEFBS_HasNEON, // FMAXNMv4f32 = 1876 |
| 18444 | CEFBS_HasNEON_HasFullFP16, // FMAXNMv8f16 = 1877 |
| 18445 | CEFBS_HasSVE2, // FMAXP_ZPmZZ_D = 1878 |
| 18446 | CEFBS_HasSVE2, // FMAXP_ZPmZZ_H = 1879 |
| 18447 | CEFBS_HasSVE2, // FMAXP_ZPmZZ_S = 1880 |
| 18448 | CEFBS_HasNEON, // FMAXPv2f32 = 1881 |
| 18449 | CEFBS_HasNEON, // FMAXPv2f64 = 1882 |
| 18450 | CEFBS_HasNEON_HasFullFP16, // FMAXPv2i16p = 1883 |
| 18451 | CEFBS_HasNEON, // FMAXPv2i32p = 1884 |
| 18452 | CEFBS_HasNEON, // FMAXPv2i64p = 1885 |
| 18453 | CEFBS_HasNEON_HasFullFP16, // FMAXPv4f16 = 1886 |
| 18454 | CEFBS_HasNEON, // FMAXPv4f32 = 1887 |
| 18455 | CEFBS_HasNEON_HasFullFP16, // FMAXPv8f16 = 1888 |
| 18456 | CEFBS_HasFPARMv8, // FMAXSrr = 1889 |
| 18457 | CEFBS_HasSVE, // FMAXV_VPZ_D = 1890 |
| 18458 | CEFBS_HasSVE, // FMAXV_VPZ_H = 1891 |
| 18459 | CEFBS_HasSVE, // FMAXV_VPZ_S = 1892 |
| 18460 | CEFBS_HasNEON_HasFullFP16, // FMAXVv4i16v = 1893 |
| 18461 | CEFBS_HasNEON, // FMAXVv4i32v = 1894 |
| 18462 | CEFBS_HasNEON_HasFullFP16, // FMAXVv8i16v = 1895 |
| 18463 | CEFBS_HasSVE, // FMAX_ZPmI_D = 1896 |
| 18464 | CEFBS_HasSVE, // FMAX_ZPmI_H = 1897 |
| 18465 | CEFBS_HasSVE, // FMAX_ZPmI_S = 1898 |
| 18466 | CEFBS_HasSVE, // FMAX_ZPmZ_D = 1899 |
| 18467 | CEFBS_HasSVE, // FMAX_ZPmZ_H = 1900 |
| 18468 | CEFBS_HasSVE, // FMAX_ZPmZ_S = 1901 |
| 18469 | CEFBS_HasNEON, // FMAXv2f32 = 1902 |
| 18470 | CEFBS_HasNEON, // FMAXv2f64 = 1903 |
| 18471 | CEFBS_HasNEON_HasFullFP16, // FMAXv4f16 = 1904 |
| 18472 | CEFBS_HasNEON, // FMAXv4f32 = 1905 |
| 18473 | CEFBS_HasNEON_HasFullFP16, // FMAXv8f16 = 1906 |
| 18474 | CEFBS_HasFPARMv8, // FMINDrr = 1907 |
| 18475 | CEFBS_HasFullFP16, // FMINHrr = 1908 |
| 18476 | CEFBS_HasFPARMv8, // FMINNMDrr = 1909 |
| 18477 | CEFBS_HasFullFP16, // FMINNMHrr = 1910 |
| 18478 | CEFBS_HasSVE2, // FMINNMP_ZPmZZ_D = 1911 |
| 18479 | CEFBS_HasSVE2, // FMINNMP_ZPmZZ_H = 1912 |
| 18480 | CEFBS_HasSVE2, // FMINNMP_ZPmZZ_S = 1913 |
| 18481 | CEFBS_HasNEON, // FMINNMPv2f32 = 1914 |
| 18482 | CEFBS_HasNEON, // FMINNMPv2f64 = 1915 |
| 18483 | CEFBS_HasNEON_HasFullFP16, // FMINNMPv2i16p = 1916 |
| 18484 | CEFBS_HasNEON, // FMINNMPv2i32p = 1917 |
| 18485 | CEFBS_HasNEON, // FMINNMPv2i64p = 1918 |
| 18486 | CEFBS_HasNEON_HasFullFP16, // FMINNMPv4f16 = 1919 |
| 18487 | CEFBS_HasNEON, // FMINNMPv4f32 = 1920 |
| 18488 | CEFBS_HasNEON_HasFullFP16, // FMINNMPv8f16 = 1921 |
| 18489 | CEFBS_HasFPARMv8, // FMINNMSrr = 1922 |
| 18490 | CEFBS_HasSVE, // FMINNMV_VPZ_D = 1923 |
| 18491 | CEFBS_HasSVE, // FMINNMV_VPZ_H = 1924 |
| 18492 | CEFBS_HasSVE, // FMINNMV_VPZ_S = 1925 |
| 18493 | CEFBS_HasNEON_HasFullFP16, // FMINNMVv4i16v = 1926 |
| 18494 | CEFBS_HasNEON, // FMINNMVv4i32v = 1927 |
| 18495 | CEFBS_HasNEON_HasFullFP16, // FMINNMVv8i16v = 1928 |
| 18496 | CEFBS_HasSVE, // FMINNM_ZPmI_D = 1929 |
| 18497 | CEFBS_HasSVE, // FMINNM_ZPmI_H = 1930 |
| 18498 | CEFBS_HasSVE, // FMINNM_ZPmI_S = 1931 |
| 18499 | CEFBS_HasSVE, // FMINNM_ZPmZ_D = 1932 |
| 18500 | CEFBS_HasSVE, // FMINNM_ZPmZ_H = 1933 |
| 18501 | CEFBS_HasSVE, // FMINNM_ZPmZ_S = 1934 |
| 18502 | CEFBS_HasNEON, // FMINNMv2f32 = 1935 |
| 18503 | CEFBS_HasNEON, // FMINNMv2f64 = 1936 |
| 18504 | CEFBS_HasNEON_HasFullFP16, // FMINNMv4f16 = 1937 |
| 18505 | CEFBS_HasNEON, // FMINNMv4f32 = 1938 |
| 18506 | CEFBS_HasNEON_HasFullFP16, // FMINNMv8f16 = 1939 |
| 18507 | CEFBS_HasSVE2, // FMINP_ZPmZZ_D = 1940 |
| 18508 | CEFBS_HasSVE2, // FMINP_ZPmZZ_H = 1941 |
| 18509 | CEFBS_HasSVE2, // FMINP_ZPmZZ_S = 1942 |
| 18510 | CEFBS_HasNEON, // FMINPv2f32 = 1943 |
| 18511 | CEFBS_HasNEON, // FMINPv2f64 = 1944 |
| 18512 | CEFBS_HasNEON_HasFullFP16, // FMINPv2i16p = 1945 |
| 18513 | CEFBS_HasNEON, // FMINPv2i32p = 1946 |
| 18514 | CEFBS_HasNEON, // FMINPv2i64p = 1947 |
| 18515 | CEFBS_HasNEON_HasFullFP16, // FMINPv4f16 = 1948 |
| 18516 | CEFBS_HasNEON, // FMINPv4f32 = 1949 |
| 18517 | CEFBS_HasNEON_HasFullFP16, // FMINPv8f16 = 1950 |
| 18518 | CEFBS_HasFPARMv8, // FMINSrr = 1951 |
| 18519 | CEFBS_HasSVE, // FMINV_VPZ_D = 1952 |
| 18520 | CEFBS_HasSVE, // FMINV_VPZ_H = 1953 |
| 18521 | CEFBS_HasSVE, // FMINV_VPZ_S = 1954 |
| 18522 | CEFBS_HasNEON_HasFullFP16, // FMINVv4i16v = 1955 |
| 18523 | CEFBS_HasNEON, // FMINVv4i32v = 1956 |
| 18524 | CEFBS_HasNEON_HasFullFP16, // FMINVv8i16v = 1957 |
| 18525 | CEFBS_HasSVE, // FMIN_ZPmI_D = 1958 |
| 18526 | CEFBS_HasSVE, // FMIN_ZPmI_H = 1959 |
| 18527 | CEFBS_HasSVE, // FMIN_ZPmI_S = 1960 |
| 18528 | CEFBS_HasSVE, // FMIN_ZPmZ_D = 1961 |
| 18529 | CEFBS_HasSVE, // FMIN_ZPmZ_H = 1962 |
| 18530 | CEFBS_HasSVE, // FMIN_ZPmZ_S = 1963 |
| 18531 | CEFBS_HasNEON, // FMINv2f32 = 1964 |
| 18532 | CEFBS_HasNEON, // FMINv2f64 = 1965 |
| 18533 | CEFBS_HasNEON_HasFullFP16, // FMINv4f16 = 1966 |
| 18534 | CEFBS_HasNEON, // FMINv4f32 = 1967 |
| 18535 | CEFBS_HasNEON_HasFullFP16, // FMINv8f16 = 1968 |
| 18536 | CEFBS_HasNEON_HasFP16FML, // FMLAL2lanev4f16 = 1969 |
| 18537 | CEFBS_HasNEON_HasFP16FML, // FMLAL2lanev8f16 = 1970 |
| 18538 | CEFBS_HasNEON_HasFP16FML, // FMLAL2v4f16 = 1971 |
| 18539 | CEFBS_HasNEON_HasFP16FML, // FMLAL2v8f16 = 1972 |
| 18540 | CEFBS_HasSVE2, // FMLALB_ZZZI_SHH = 1973 |
| 18541 | CEFBS_HasSVE2, // FMLALB_ZZZ_SHH = 1974 |
| 18542 | CEFBS_HasSVE2, // FMLALT_ZZZI_SHH = 1975 |
| 18543 | CEFBS_HasSVE2, // FMLALT_ZZZ_SHH = 1976 |
| 18544 | CEFBS_HasNEON_HasFP16FML, // FMLALlanev4f16 = 1977 |
| 18545 | CEFBS_HasNEON_HasFP16FML, // FMLALlanev8f16 = 1978 |
| 18546 | CEFBS_HasNEON_HasFP16FML, // FMLALv4f16 = 1979 |
| 18547 | CEFBS_HasNEON_HasFP16FML, // FMLALv8f16 = 1980 |
| 18548 | CEFBS_HasSVE, // FMLA_ZPmZZ_D = 1981 |
| 18549 | CEFBS_HasSVE, // FMLA_ZPmZZ_H = 1982 |
| 18550 | CEFBS_HasSVE, // FMLA_ZPmZZ_S = 1983 |
| 18551 | CEFBS_HasSVE, // FMLA_ZZZI_D = 1984 |
| 18552 | CEFBS_HasSVE, // FMLA_ZZZI_H = 1985 |
| 18553 | CEFBS_HasSVE, // FMLA_ZZZI_S = 1986 |
| 18554 | CEFBS_HasNEON_HasFullFP16, // FMLAv1i16_indexed = 1987 |
| 18555 | CEFBS_HasNEON, // FMLAv1i32_indexed = 1988 |
| 18556 | CEFBS_HasNEON, // FMLAv1i64_indexed = 1989 |
| 18557 | CEFBS_HasNEON, // FMLAv2f32 = 1990 |
| 18558 | CEFBS_HasNEON, // FMLAv2f64 = 1991 |
| 18559 | CEFBS_HasNEON, // FMLAv2i32_indexed = 1992 |
| 18560 | CEFBS_HasNEON, // FMLAv2i64_indexed = 1993 |
| 18561 | CEFBS_HasNEON_HasFullFP16, // FMLAv4f16 = 1994 |
| 18562 | CEFBS_HasNEON, // FMLAv4f32 = 1995 |
| 18563 | CEFBS_HasNEON_HasFullFP16, // FMLAv4i16_indexed = 1996 |
| 18564 | CEFBS_HasNEON, // FMLAv4i32_indexed = 1997 |
| 18565 | CEFBS_HasNEON_HasFullFP16, // FMLAv8f16 = 1998 |
| 18566 | CEFBS_HasNEON_HasFullFP16, // FMLAv8i16_indexed = 1999 |
| 18567 | CEFBS_HasNEON_HasFP16FML, // FMLSL2lanev4f16 = 2000 |
| 18568 | CEFBS_HasNEON_HasFP16FML, // FMLSL2lanev8f16 = 2001 |
| 18569 | CEFBS_HasNEON_HasFP16FML, // FMLSL2v4f16 = 2002 |
| 18570 | CEFBS_HasNEON_HasFP16FML, // FMLSL2v8f16 = 2003 |
| 18571 | CEFBS_HasSVE2, // FMLSLB_ZZZI_SHH = 2004 |
| 18572 | CEFBS_HasSVE2, // FMLSLB_ZZZ_SHH = 2005 |
| 18573 | CEFBS_HasSVE2, // FMLSLT_ZZZI_SHH = 2006 |
| 18574 | CEFBS_HasSVE2, // FMLSLT_ZZZ_SHH = 2007 |
| 18575 | CEFBS_HasNEON_HasFP16FML, // FMLSLlanev4f16 = 2008 |
| 18576 | CEFBS_HasNEON_HasFP16FML, // FMLSLlanev8f16 = 2009 |
| 18577 | CEFBS_HasNEON_HasFP16FML, // FMLSLv4f16 = 2010 |
| 18578 | CEFBS_HasNEON_HasFP16FML, // FMLSLv8f16 = 2011 |
| 18579 | CEFBS_HasSVE, // FMLS_ZPmZZ_D = 2012 |
| 18580 | CEFBS_HasSVE, // FMLS_ZPmZZ_H = 2013 |
| 18581 | CEFBS_HasSVE, // FMLS_ZPmZZ_S = 2014 |
| 18582 | CEFBS_HasSVE, // FMLS_ZZZI_D = 2015 |
| 18583 | CEFBS_HasSVE, // FMLS_ZZZI_H = 2016 |
| 18584 | CEFBS_HasSVE, // FMLS_ZZZI_S = 2017 |
| 18585 | CEFBS_HasNEON_HasFullFP16, // FMLSv1i16_indexed = 2018 |
| 18586 | CEFBS_HasNEON, // FMLSv1i32_indexed = 2019 |
| 18587 | CEFBS_HasNEON, // FMLSv1i64_indexed = 2020 |
| 18588 | CEFBS_HasNEON, // FMLSv2f32 = 2021 |
| 18589 | CEFBS_HasNEON, // FMLSv2f64 = 2022 |
| 18590 | CEFBS_HasNEON, // FMLSv2i32_indexed = 2023 |
| 18591 | CEFBS_HasNEON, // FMLSv2i64_indexed = 2024 |
| 18592 | CEFBS_HasNEON_HasFullFP16, // FMLSv4f16 = 2025 |
| 18593 | CEFBS_HasNEON, // FMLSv4f32 = 2026 |
| 18594 | CEFBS_HasNEON_HasFullFP16, // FMLSv4i16_indexed = 2027 |
| 18595 | CEFBS_HasNEON, // FMLSv4i32_indexed = 2028 |
| 18596 | CEFBS_HasNEON_HasFullFP16, // FMLSv8f16 = 2029 |
| 18597 | CEFBS_HasNEON_HasFullFP16, // FMLSv8i16_indexed = 2030 |
| 18598 | CEFBS_HasSVE_HasMatMulFP64, // FMMLA_ZZZ_D = 2031 |
| 18599 | CEFBS_HasSVE_HasMatMulFP32, // FMMLA_ZZZ_S = 2032 |
| 18600 | CEFBS_HasFPARMv8, // FMOVDXHighr = 2033 |
| 18601 | CEFBS_HasFPARMv8, // FMOVDXr = 2034 |
| 18602 | CEFBS_HasFPARMv8, // FMOVDi = 2035 |
| 18603 | CEFBS_HasFPARMv8, // FMOVDr = 2036 |
| 18604 | CEFBS_HasFullFP16, // FMOVHWr = 2037 |
| 18605 | CEFBS_HasFullFP16, // FMOVHXr = 2038 |
| 18606 | CEFBS_HasFullFP16, // FMOVHi = 2039 |
| 18607 | CEFBS_HasFullFP16, // FMOVHr = 2040 |
| 18608 | CEFBS_HasFPARMv8, // FMOVSWr = 2041 |
| 18609 | CEFBS_HasFPARMv8, // FMOVSi = 2042 |
| 18610 | CEFBS_HasFPARMv8, // FMOVSr = 2043 |
| 18611 | CEFBS_HasFullFP16, // FMOVWHr = 2044 |
| 18612 | CEFBS_HasFPARMv8, // FMOVWSr = 2045 |
| 18613 | CEFBS_HasFPARMv8, // FMOVXDHighr = 2046 |
| 18614 | CEFBS_HasFPARMv8, // FMOVXDr = 2047 |
| 18615 | CEFBS_HasFullFP16, // FMOVXHr = 2048 |
| 18616 | CEFBS_HasNEON, // FMOVv2f32_ns = 2049 |
| 18617 | CEFBS_HasNEON, // FMOVv2f64_ns = 2050 |
| 18618 | CEFBS_HasNEON_HasFullFP16, // FMOVv4f16_ns = 2051 |
| 18619 | CEFBS_HasNEON, // FMOVv4f32_ns = 2052 |
| 18620 | CEFBS_HasNEON_HasFullFP16, // FMOVv8f16_ns = 2053 |
| 18621 | CEFBS_HasSVE, // FMSB_ZPmZZ_D = 2054 |
| 18622 | CEFBS_HasSVE, // FMSB_ZPmZZ_H = 2055 |
| 18623 | CEFBS_HasSVE, // FMSB_ZPmZZ_S = 2056 |
| 18624 | CEFBS_HasFPARMv8, // FMSUBDrrr = 2057 |
| 18625 | CEFBS_HasFullFP16, // FMSUBHrrr = 2058 |
| 18626 | CEFBS_HasFPARMv8, // FMSUBSrrr = 2059 |
| 18627 | CEFBS_HasFPARMv8, // FMULDrr = 2060 |
| 18628 | CEFBS_HasFullFP16, // FMULHrr = 2061 |
| 18629 | CEFBS_HasFPARMv8, // FMULSrr = 2062 |
| 18630 | CEFBS_HasNEON_HasFullFP16, // FMULX16 = 2063 |
| 18631 | CEFBS_HasNEON, // FMULX32 = 2064 |
| 18632 | CEFBS_HasNEON, // FMULX64 = 2065 |
| 18633 | CEFBS_HasSVE, // FMULX_ZPmZ_D = 2066 |
| 18634 | CEFBS_HasSVE, // FMULX_ZPmZ_H = 2067 |
| 18635 | CEFBS_HasSVE, // FMULX_ZPmZ_S = 2068 |
| 18636 | CEFBS_HasNEON_HasFullFP16, // FMULXv1i16_indexed = 2069 |
| 18637 | CEFBS_HasNEON, // FMULXv1i32_indexed = 2070 |
| 18638 | CEFBS_HasNEON, // FMULXv1i64_indexed = 2071 |
| 18639 | CEFBS_HasNEON, // FMULXv2f32 = 2072 |
| 18640 | CEFBS_HasNEON, // FMULXv2f64 = 2073 |
| 18641 | CEFBS_HasNEON, // FMULXv2i32_indexed = 2074 |
| 18642 | CEFBS_HasNEON, // FMULXv2i64_indexed = 2075 |
| 18643 | CEFBS_HasNEON_HasFullFP16, // FMULXv4f16 = 2076 |
| 18644 | CEFBS_HasNEON, // FMULXv4f32 = 2077 |
| 18645 | CEFBS_HasNEON_HasFullFP16, // FMULXv4i16_indexed = 2078 |
| 18646 | CEFBS_HasNEON, // FMULXv4i32_indexed = 2079 |
| 18647 | CEFBS_HasNEON_HasFullFP16, // FMULXv8f16 = 2080 |
| 18648 | CEFBS_HasNEON_HasFullFP16, // FMULXv8i16_indexed = 2081 |
| 18649 | CEFBS_HasSVE, // FMUL_ZPmI_D = 2082 |
| 18650 | CEFBS_HasSVE, // FMUL_ZPmI_H = 2083 |
| 18651 | CEFBS_HasSVE, // FMUL_ZPmI_S = 2084 |
| 18652 | CEFBS_HasSVE, // FMUL_ZPmZ_D = 2085 |
| 18653 | CEFBS_HasSVE, // FMUL_ZPmZ_H = 2086 |
| 18654 | CEFBS_HasSVE, // FMUL_ZPmZ_S = 2087 |
| 18655 | CEFBS_HasSVE, // FMUL_ZZZI_D = 2088 |
| 18656 | CEFBS_HasSVE, // FMUL_ZZZI_H = 2089 |
| 18657 | CEFBS_HasSVE, // FMUL_ZZZI_S = 2090 |
| 18658 | CEFBS_HasSVE, // FMUL_ZZZ_D = 2091 |
| 18659 | CEFBS_HasSVE, // FMUL_ZZZ_H = 2092 |
| 18660 | CEFBS_HasSVE, // FMUL_ZZZ_S = 2093 |
| 18661 | CEFBS_HasNEON_HasFullFP16, // FMULv1i16_indexed = 2094 |
| 18662 | CEFBS_HasNEON, // FMULv1i32_indexed = 2095 |
| 18663 | CEFBS_HasNEON, // FMULv1i64_indexed = 2096 |
| 18664 | CEFBS_HasNEON, // FMULv2f32 = 2097 |
| 18665 | CEFBS_HasNEON, // FMULv2f64 = 2098 |
| 18666 | CEFBS_HasNEON, // FMULv2i32_indexed = 2099 |
| 18667 | CEFBS_HasNEON, // FMULv2i64_indexed = 2100 |
| 18668 | CEFBS_HasNEON_HasFullFP16, // FMULv4f16 = 2101 |
| 18669 | CEFBS_HasNEON, // FMULv4f32 = 2102 |
| 18670 | CEFBS_HasNEON_HasFullFP16, // FMULv4i16_indexed = 2103 |
| 18671 | CEFBS_HasNEON, // FMULv4i32_indexed = 2104 |
| 18672 | CEFBS_HasNEON_HasFullFP16, // FMULv8f16 = 2105 |
| 18673 | CEFBS_HasNEON_HasFullFP16, // FMULv8i16_indexed = 2106 |
| 18674 | CEFBS_HasFPARMv8, // FNEGDr = 2107 |
| 18675 | CEFBS_HasFullFP16, // FNEGHr = 2108 |
| 18676 | CEFBS_HasFPARMv8, // FNEGSr = 2109 |
| 18677 | CEFBS_HasSVE, // FNEG_ZPmZ_D = 2110 |
| 18678 | CEFBS_HasSVE, // FNEG_ZPmZ_H = 2111 |
| 18679 | CEFBS_HasSVE, // FNEG_ZPmZ_S = 2112 |
| 18680 | CEFBS_HasNEON, // FNEGv2f32 = 2113 |
| 18681 | CEFBS_HasNEON, // FNEGv2f64 = 2114 |
| 18682 | CEFBS_HasNEON_HasFullFP16, // FNEGv4f16 = 2115 |
| 18683 | CEFBS_HasNEON, // FNEGv4f32 = 2116 |
| 18684 | CEFBS_HasNEON_HasFullFP16, // FNEGv8f16 = 2117 |
| 18685 | CEFBS_HasFPARMv8, // FNMADDDrrr = 2118 |
| 18686 | CEFBS_HasFullFP16, // FNMADDHrrr = 2119 |
| 18687 | CEFBS_HasFPARMv8, // FNMADDSrrr = 2120 |
| 18688 | CEFBS_HasSVE, // FNMAD_ZPmZZ_D = 2121 |
| 18689 | CEFBS_HasSVE, // FNMAD_ZPmZZ_H = 2122 |
| 18690 | CEFBS_HasSVE, // FNMAD_ZPmZZ_S = 2123 |
| 18691 | CEFBS_HasSVE, // FNMLA_ZPmZZ_D = 2124 |
| 18692 | CEFBS_HasSVE, // FNMLA_ZPmZZ_H = 2125 |
| 18693 | CEFBS_HasSVE, // FNMLA_ZPmZZ_S = 2126 |
| 18694 | CEFBS_HasSVE, // FNMLS_ZPmZZ_D = 2127 |
| 18695 | CEFBS_HasSVE, // FNMLS_ZPmZZ_H = 2128 |
| 18696 | CEFBS_HasSVE, // FNMLS_ZPmZZ_S = 2129 |
| 18697 | CEFBS_HasSVE, // FNMSB_ZPmZZ_D = 2130 |
| 18698 | CEFBS_HasSVE, // FNMSB_ZPmZZ_H = 2131 |
| 18699 | CEFBS_HasSVE, // FNMSB_ZPmZZ_S = 2132 |
| 18700 | CEFBS_HasFPARMv8, // FNMSUBDrrr = 2133 |
| 18701 | CEFBS_HasFullFP16, // FNMSUBHrrr = 2134 |
| 18702 | CEFBS_HasFPARMv8, // FNMSUBSrrr = 2135 |
| 18703 | CEFBS_HasFPARMv8, // FNMULDrr = 2136 |
| 18704 | CEFBS_HasFullFP16, // FNMULHrr = 2137 |
| 18705 | CEFBS_HasFPARMv8, // FNMULSrr = 2138 |
| 18706 | CEFBS_HasSVE, // FRECPE_ZZ_D = 2139 |
| 18707 | CEFBS_HasSVE, // FRECPE_ZZ_H = 2140 |
| 18708 | CEFBS_HasSVE, // FRECPE_ZZ_S = 2141 |
| 18709 | CEFBS_HasNEON_HasFullFP16, // FRECPEv1f16 = 2142 |
| 18710 | CEFBS_HasNEON, // FRECPEv1i32 = 2143 |
| 18711 | CEFBS_HasNEON, // FRECPEv1i64 = 2144 |
| 18712 | CEFBS_HasNEON, // FRECPEv2f32 = 2145 |
| 18713 | CEFBS_HasNEON, // FRECPEv2f64 = 2146 |
| 18714 | CEFBS_HasNEON_HasFullFP16, // FRECPEv4f16 = 2147 |
| 18715 | CEFBS_HasNEON, // FRECPEv4f32 = 2148 |
| 18716 | CEFBS_HasNEON_HasFullFP16, // FRECPEv8f16 = 2149 |
| 18717 | CEFBS_HasNEON_HasFullFP16, // FRECPS16 = 2150 |
| 18718 | CEFBS_HasNEON, // FRECPS32 = 2151 |
| 18719 | CEFBS_HasNEON, // FRECPS64 = 2152 |
| 18720 | CEFBS_HasSVE, // FRECPS_ZZZ_D = 2153 |
| 18721 | CEFBS_HasSVE, // FRECPS_ZZZ_H = 2154 |
| 18722 | CEFBS_HasSVE, // FRECPS_ZZZ_S = 2155 |
| 18723 | CEFBS_HasNEON, // FRECPSv2f32 = 2156 |
| 18724 | CEFBS_HasNEON, // FRECPSv2f64 = 2157 |
| 18725 | CEFBS_HasNEON_HasFullFP16, // FRECPSv4f16 = 2158 |
| 18726 | CEFBS_HasNEON, // FRECPSv4f32 = 2159 |
| 18727 | CEFBS_HasNEON_HasFullFP16, // FRECPSv8f16 = 2160 |
| 18728 | CEFBS_HasSVE, // FRECPX_ZPmZ_D = 2161 |
| 18729 | CEFBS_HasSVE, // FRECPX_ZPmZ_H = 2162 |
| 18730 | CEFBS_HasSVE, // FRECPX_ZPmZ_S = 2163 |
| 18731 | CEFBS_HasNEON_HasFullFP16, // FRECPXv1f16 = 2164 |
| 18732 | CEFBS_HasNEON, // FRECPXv1i32 = 2165 |
| 18733 | CEFBS_HasNEON, // FRECPXv1i64 = 2166 |
| 18734 | CEFBS_HasFRInt3264, // FRINT32XDr = 2167 |
| 18735 | CEFBS_HasFRInt3264, // FRINT32XSr = 2168 |
| 18736 | CEFBS_HasFRInt3264, // FRINT32Xv2f32 = 2169 |
| 18737 | CEFBS_HasFRInt3264, // FRINT32Xv2f64 = 2170 |
| 18738 | CEFBS_HasFRInt3264, // FRINT32Xv4f32 = 2171 |
| 18739 | CEFBS_HasFRInt3264, // FRINT32ZDr = 2172 |
| 18740 | CEFBS_HasFRInt3264, // FRINT32ZSr = 2173 |
| 18741 | CEFBS_HasFRInt3264, // FRINT32Zv2f32 = 2174 |
| 18742 | CEFBS_HasFRInt3264, // FRINT32Zv2f64 = 2175 |
| 18743 | CEFBS_HasFRInt3264, // FRINT32Zv4f32 = 2176 |
| 18744 | CEFBS_HasFRInt3264, // FRINT64XDr = 2177 |
| 18745 | CEFBS_HasFRInt3264, // FRINT64XSr = 2178 |
| 18746 | CEFBS_HasFRInt3264, // FRINT64Xv2f32 = 2179 |
| 18747 | CEFBS_HasFRInt3264, // FRINT64Xv2f64 = 2180 |
| 18748 | CEFBS_HasFRInt3264, // FRINT64Xv4f32 = 2181 |
| 18749 | CEFBS_HasFRInt3264, // FRINT64ZDr = 2182 |
| 18750 | CEFBS_HasFRInt3264, // FRINT64ZSr = 2183 |
| 18751 | CEFBS_HasFRInt3264, // FRINT64Zv2f32 = 2184 |
| 18752 | CEFBS_HasFRInt3264, // FRINT64Zv2f64 = 2185 |
| 18753 | CEFBS_HasFRInt3264, // FRINT64Zv4f32 = 2186 |
| 18754 | CEFBS_HasFPARMv8, // FRINTADr = 2187 |
| 18755 | CEFBS_HasFullFP16, // FRINTAHr = 2188 |
| 18756 | CEFBS_HasFPARMv8, // FRINTASr = 2189 |
| 18757 | CEFBS_HasSVE, // FRINTA_ZPmZ_D = 2190 |
| 18758 | CEFBS_HasSVE, // FRINTA_ZPmZ_H = 2191 |
| 18759 | CEFBS_HasSVE, // FRINTA_ZPmZ_S = 2192 |
| 18760 | CEFBS_HasNEON, // FRINTAv2f32 = 2193 |
| 18761 | CEFBS_HasNEON, // FRINTAv2f64 = 2194 |
| 18762 | CEFBS_HasNEON_HasFullFP16, // FRINTAv4f16 = 2195 |
| 18763 | CEFBS_HasNEON, // FRINTAv4f32 = 2196 |
| 18764 | CEFBS_HasNEON_HasFullFP16, // FRINTAv8f16 = 2197 |
| 18765 | CEFBS_HasFPARMv8, // FRINTIDr = 2198 |
| 18766 | CEFBS_HasFullFP16, // FRINTIHr = 2199 |
| 18767 | CEFBS_HasFPARMv8, // FRINTISr = 2200 |
| 18768 | CEFBS_HasSVE, // FRINTI_ZPmZ_D = 2201 |
| 18769 | CEFBS_HasSVE, // FRINTI_ZPmZ_H = 2202 |
| 18770 | CEFBS_HasSVE, // FRINTI_ZPmZ_S = 2203 |
| 18771 | CEFBS_HasNEON, // FRINTIv2f32 = 2204 |
| 18772 | CEFBS_HasNEON, // FRINTIv2f64 = 2205 |
| 18773 | CEFBS_HasNEON_HasFullFP16, // FRINTIv4f16 = 2206 |
| 18774 | CEFBS_HasNEON, // FRINTIv4f32 = 2207 |
| 18775 | CEFBS_HasNEON_HasFullFP16, // FRINTIv8f16 = 2208 |
| 18776 | CEFBS_HasFPARMv8, // FRINTMDr = 2209 |
| 18777 | CEFBS_HasFullFP16, // FRINTMHr = 2210 |
| 18778 | CEFBS_HasFPARMv8, // FRINTMSr = 2211 |
| 18779 | CEFBS_HasSVE, // FRINTM_ZPmZ_D = 2212 |
| 18780 | CEFBS_HasSVE, // FRINTM_ZPmZ_H = 2213 |
| 18781 | CEFBS_HasSVE, // FRINTM_ZPmZ_S = 2214 |
| 18782 | CEFBS_HasNEON, // FRINTMv2f32 = 2215 |
| 18783 | CEFBS_HasNEON, // FRINTMv2f64 = 2216 |
| 18784 | CEFBS_HasNEON_HasFullFP16, // FRINTMv4f16 = 2217 |
| 18785 | CEFBS_HasNEON, // FRINTMv4f32 = 2218 |
| 18786 | CEFBS_HasNEON_HasFullFP16, // FRINTMv8f16 = 2219 |
| 18787 | CEFBS_HasFPARMv8, // FRINTNDr = 2220 |
| 18788 | CEFBS_HasFullFP16, // FRINTNHr = 2221 |
| 18789 | CEFBS_HasFPARMv8, // FRINTNSr = 2222 |
| 18790 | CEFBS_HasSVE, // FRINTN_ZPmZ_D = 2223 |
| 18791 | CEFBS_HasSVE, // FRINTN_ZPmZ_H = 2224 |
| 18792 | CEFBS_HasSVE, // FRINTN_ZPmZ_S = 2225 |
| 18793 | CEFBS_HasNEON, // FRINTNv2f32 = 2226 |
| 18794 | CEFBS_HasNEON, // FRINTNv2f64 = 2227 |
| 18795 | CEFBS_HasNEON_HasFullFP16, // FRINTNv4f16 = 2228 |
| 18796 | CEFBS_HasNEON, // FRINTNv4f32 = 2229 |
| 18797 | CEFBS_HasNEON_HasFullFP16, // FRINTNv8f16 = 2230 |
| 18798 | CEFBS_HasFPARMv8, // FRINTPDr = 2231 |
| 18799 | CEFBS_HasFullFP16, // FRINTPHr = 2232 |
| 18800 | CEFBS_HasFPARMv8, // FRINTPSr = 2233 |
| 18801 | CEFBS_HasSVE, // FRINTP_ZPmZ_D = 2234 |
| 18802 | CEFBS_HasSVE, // FRINTP_ZPmZ_H = 2235 |
| 18803 | CEFBS_HasSVE, // FRINTP_ZPmZ_S = 2236 |
| 18804 | CEFBS_HasNEON, // FRINTPv2f32 = 2237 |
| 18805 | CEFBS_HasNEON, // FRINTPv2f64 = 2238 |
| 18806 | CEFBS_HasNEON_HasFullFP16, // FRINTPv4f16 = 2239 |
| 18807 | CEFBS_HasNEON, // FRINTPv4f32 = 2240 |
| 18808 | CEFBS_HasNEON_HasFullFP16, // FRINTPv8f16 = 2241 |
| 18809 | CEFBS_HasFPARMv8, // FRINTXDr = 2242 |
| 18810 | CEFBS_HasFullFP16, // FRINTXHr = 2243 |
| 18811 | CEFBS_HasFPARMv8, // FRINTXSr = 2244 |
| 18812 | CEFBS_HasSVE, // FRINTX_ZPmZ_D = 2245 |
| 18813 | CEFBS_HasSVE, // FRINTX_ZPmZ_H = 2246 |
| 18814 | CEFBS_HasSVE, // FRINTX_ZPmZ_S = 2247 |
| 18815 | CEFBS_HasNEON, // FRINTXv2f32 = 2248 |
| 18816 | CEFBS_HasNEON, // FRINTXv2f64 = 2249 |
| 18817 | CEFBS_HasNEON_HasFullFP16, // FRINTXv4f16 = 2250 |
| 18818 | CEFBS_HasNEON, // FRINTXv4f32 = 2251 |
| 18819 | CEFBS_HasNEON_HasFullFP16, // FRINTXv8f16 = 2252 |
| 18820 | CEFBS_HasFPARMv8, // FRINTZDr = 2253 |
| 18821 | CEFBS_HasFullFP16, // FRINTZHr = 2254 |
| 18822 | CEFBS_HasFPARMv8, // FRINTZSr = 2255 |
| 18823 | CEFBS_HasSVE, // FRINTZ_ZPmZ_D = 2256 |
| 18824 | CEFBS_HasSVE, // FRINTZ_ZPmZ_H = 2257 |
| 18825 | CEFBS_HasSVE, // FRINTZ_ZPmZ_S = 2258 |
| 18826 | CEFBS_HasNEON, // FRINTZv2f32 = 2259 |
| 18827 | CEFBS_HasNEON, // FRINTZv2f64 = 2260 |
| 18828 | CEFBS_HasNEON_HasFullFP16, // FRINTZv4f16 = 2261 |
| 18829 | CEFBS_HasNEON, // FRINTZv4f32 = 2262 |
| 18830 | CEFBS_HasNEON_HasFullFP16, // FRINTZv8f16 = 2263 |
| 18831 | CEFBS_HasSVE, // FRSQRTE_ZZ_D = 2264 |
| 18832 | CEFBS_HasSVE, // FRSQRTE_ZZ_H = 2265 |
| 18833 | CEFBS_HasSVE, // FRSQRTE_ZZ_S = 2266 |
| 18834 | CEFBS_HasNEON_HasFullFP16, // FRSQRTEv1f16 = 2267 |
| 18835 | CEFBS_HasNEON, // FRSQRTEv1i32 = 2268 |
| 18836 | CEFBS_HasNEON, // FRSQRTEv1i64 = 2269 |
| 18837 | CEFBS_HasNEON, // FRSQRTEv2f32 = 2270 |
| 18838 | CEFBS_HasNEON, // FRSQRTEv2f64 = 2271 |
| 18839 | CEFBS_HasNEON_HasFullFP16, // FRSQRTEv4f16 = 2272 |
| 18840 | CEFBS_HasNEON, // FRSQRTEv4f32 = 2273 |
| 18841 | CEFBS_HasNEON_HasFullFP16, // FRSQRTEv8f16 = 2274 |
| 18842 | CEFBS_HasNEON_HasFullFP16, // FRSQRTS16 = 2275 |
| 18843 | CEFBS_HasNEON, // FRSQRTS32 = 2276 |
| 18844 | CEFBS_HasNEON, // FRSQRTS64 = 2277 |
| 18845 | CEFBS_HasSVE, // FRSQRTS_ZZZ_D = 2278 |
| 18846 | CEFBS_HasSVE, // FRSQRTS_ZZZ_H = 2279 |
| 18847 | CEFBS_HasSVE, // FRSQRTS_ZZZ_S = 2280 |
| 18848 | CEFBS_HasNEON, // FRSQRTSv2f32 = 2281 |
| 18849 | CEFBS_HasNEON, // FRSQRTSv2f64 = 2282 |
| 18850 | CEFBS_HasNEON_HasFullFP16, // FRSQRTSv4f16 = 2283 |
| 18851 | CEFBS_HasNEON, // FRSQRTSv4f32 = 2284 |
| 18852 | CEFBS_HasNEON_HasFullFP16, // FRSQRTSv8f16 = 2285 |
| 18853 | CEFBS_HasSVE, // FSCALE_ZPmZ_D = 2286 |
| 18854 | CEFBS_HasSVE, // FSCALE_ZPmZ_H = 2287 |
| 18855 | CEFBS_HasSVE, // FSCALE_ZPmZ_S = 2288 |
| 18856 | CEFBS_HasFPARMv8, // FSQRTDr = 2289 |
| 18857 | CEFBS_HasFullFP16, // FSQRTHr = 2290 |
| 18858 | CEFBS_HasFPARMv8, // FSQRTSr = 2291 |
| 18859 | CEFBS_HasSVE, // FSQRT_ZPmZ_D = 2292 |
| 18860 | CEFBS_HasSVE, // FSQRT_ZPmZ_H = 2293 |
| 18861 | CEFBS_HasSVE, // FSQRT_ZPmZ_S = 2294 |
| 18862 | CEFBS_HasNEON, // FSQRTv2f32 = 2295 |
| 18863 | CEFBS_HasNEON, // FSQRTv2f64 = 2296 |
| 18864 | CEFBS_HasNEON_HasFullFP16, // FSQRTv4f16 = 2297 |
| 18865 | CEFBS_HasNEON, // FSQRTv4f32 = 2298 |
| 18866 | CEFBS_HasNEON_HasFullFP16, // FSQRTv8f16 = 2299 |
| 18867 | CEFBS_HasFPARMv8, // FSUBDrr = 2300 |
| 18868 | CEFBS_HasFullFP16, // FSUBHrr = 2301 |
| 18869 | CEFBS_HasSVE, // FSUBR_ZPmI_D = 2302 |
| 18870 | CEFBS_HasSVE, // FSUBR_ZPmI_H = 2303 |
| 18871 | CEFBS_HasSVE, // FSUBR_ZPmI_S = 2304 |
| 18872 | CEFBS_HasSVE, // FSUBR_ZPmZ_D = 2305 |
| 18873 | CEFBS_HasSVE, // FSUBR_ZPmZ_H = 2306 |
| 18874 | CEFBS_HasSVE, // FSUBR_ZPmZ_S = 2307 |
| 18875 | CEFBS_HasFPARMv8, // FSUBSrr = 2308 |
| 18876 | CEFBS_HasSVE, // FSUB_ZPmI_D = 2309 |
| 18877 | CEFBS_HasSVE, // FSUB_ZPmI_H = 2310 |
| 18878 | CEFBS_HasSVE, // FSUB_ZPmI_S = 2311 |
| 18879 | CEFBS_HasSVE, // FSUB_ZPmZ_D = 2312 |
| 18880 | CEFBS_HasSVE, // FSUB_ZPmZ_H = 2313 |
| 18881 | CEFBS_HasSVE, // FSUB_ZPmZ_S = 2314 |
| 18882 | CEFBS_HasSVE, // FSUB_ZZZ_D = 2315 |
| 18883 | CEFBS_HasSVE, // FSUB_ZZZ_H = 2316 |
| 18884 | CEFBS_HasSVE, // FSUB_ZZZ_S = 2317 |
| 18885 | CEFBS_HasNEON, // FSUBv2f32 = 2318 |
| 18886 | CEFBS_HasNEON, // FSUBv2f64 = 2319 |
| 18887 | CEFBS_HasNEON_HasFullFP16, // FSUBv4f16 = 2320 |
| 18888 | CEFBS_HasNEON, // FSUBv4f32 = 2321 |
| 18889 | CEFBS_HasNEON_HasFullFP16, // FSUBv8f16 = 2322 |
| 18890 | CEFBS_HasSVE, // FTMAD_ZZI_D = 2323 |
| 18891 | CEFBS_HasSVE, // FTMAD_ZZI_H = 2324 |
| 18892 | CEFBS_HasSVE, // FTMAD_ZZI_S = 2325 |
| 18893 | CEFBS_HasSVE, // FTSMUL_ZZZ_D = 2326 |
| 18894 | CEFBS_HasSVE, // FTSMUL_ZZZ_H = 2327 |
| 18895 | CEFBS_HasSVE, // FTSMUL_ZZZ_S = 2328 |
| 18896 | CEFBS_HasSVE, // FTSSEL_ZZZ_D = 2329 |
| 18897 | CEFBS_HasSVE, // FTSSEL_ZZZ_H = 2330 |
| 18898 | CEFBS_HasSVE, // FTSSEL_ZZZ_S = 2331 |
| 18899 | CEFBS_HasSVE, // GLD1B_D_IMM_REAL = 2332 |
| 18900 | CEFBS_HasSVE, // GLD1B_D_REAL = 2333 |
| 18901 | CEFBS_HasSVE, // GLD1B_D_SXTW_REAL = 2334 |
| 18902 | CEFBS_HasSVE, // GLD1B_D_UXTW_REAL = 2335 |
| 18903 | CEFBS_HasSVE, // GLD1B_S_IMM_REAL = 2336 |
| 18904 | CEFBS_HasSVE, // GLD1B_S_SXTW_REAL = 2337 |
| 18905 | CEFBS_HasSVE, // GLD1B_S_UXTW_REAL = 2338 |
| 18906 | CEFBS_HasSVE, // GLD1D_IMM_REAL = 2339 |
| 18907 | CEFBS_HasSVE, // GLD1D_REAL = 2340 |
| 18908 | CEFBS_HasSVE, // GLD1D_SCALED_REAL = 2341 |
| 18909 | CEFBS_HasSVE, // GLD1D_SXTW_REAL = 2342 |
| 18910 | CEFBS_HasSVE, // GLD1D_SXTW_SCALED_REAL = 2343 |
| 18911 | CEFBS_HasSVE, // GLD1D_UXTW_REAL = 2344 |
| 18912 | CEFBS_HasSVE, // GLD1D_UXTW_SCALED_REAL = 2345 |
| 18913 | CEFBS_HasSVE, // GLD1H_D_IMM_REAL = 2346 |
| 18914 | CEFBS_HasSVE, // GLD1H_D_REAL = 2347 |
| 18915 | CEFBS_HasSVE, // GLD1H_D_SCALED_REAL = 2348 |
| 18916 | CEFBS_HasSVE, // GLD1H_D_SXTW_REAL = 2349 |
| 18917 | CEFBS_HasSVE, // GLD1H_D_SXTW_SCALED_REAL = 2350 |
| 18918 | CEFBS_HasSVE, // GLD1H_D_UXTW_REAL = 2351 |
| 18919 | CEFBS_HasSVE, // GLD1H_D_UXTW_SCALED_REAL = 2352 |
| 18920 | CEFBS_HasSVE, // GLD1H_S_IMM_REAL = 2353 |
| 18921 | CEFBS_HasSVE, // GLD1H_S_SXTW_REAL = 2354 |
| 18922 | CEFBS_HasSVE, // GLD1H_S_SXTW_SCALED_REAL = 2355 |
| 18923 | CEFBS_HasSVE, // GLD1H_S_UXTW_REAL = 2356 |
| 18924 | CEFBS_HasSVE, // GLD1H_S_UXTW_SCALED_REAL = 2357 |
| 18925 | CEFBS_HasSVE, // GLD1SB_D_IMM_REAL = 2358 |
| 18926 | CEFBS_HasSVE, // GLD1SB_D_REAL = 2359 |
| 18927 | CEFBS_HasSVE, // GLD1SB_D_SXTW_REAL = 2360 |
| 18928 | CEFBS_HasSVE, // GLD1SB_D_UXTW_REAL = 2361 |
| 18929 | CEFBS_HasSVE, // GLD1SB_S_IMM_REAL = 2362 |
| 18930 | CEFBS_HasSVE, // GLD1SB_S_SXTW_REAL = 2363 |
| 18931 | CEFBS_HasSVE, // GLD1SB_S_UXTW_REAL = 2364 |
| 18932 | CEFBS_HasSVE, // GLD1SH_D_IMM_REAL = 2365 |
| 18933 | CEFBS_HasSVE, // GLD1SH_D_REAL = 2366 |
| 18934 | CEFBS_HasSVE, // GLD1SH_D_SCALED_REAL = 2367 |
| 18935 | CEFBS_HasSVE, // GLD1SH_D_SXTW_REAL = 2368 |
| 18936 | CEFBS_HasSVE, // GLD1SH_D_SXTW_SCALED_REAL = 2369 |
| 18937 | CEFBS_HasSVE, // GLD1SH_D_UXTW_REAL = 2370 |
| 18938 | CEFBS_HasSVE, // GLD1SH_D_UXTW_SCALED_REAL = 2371 |
| 18939 | CEFBS_HasSVE, // GLD1SH_S_IMM_REAL = 2372 |
| 18940 | CEFBS_HasSVE, // GLD1SH_S_SXTW_REAL = 2373 |
| 18941 | CEFBS_HasSVE, // GLD1SH_S_SXTW_SCALED_REAL = 2374 |
| 18942 | CEFBS_HasSVE, // GLD1SH_S_UXTW_REAL = 2375 |
| 18943 | CEFBS_HasSVE, // GLD1SH_S_UXTW_SCALED_REAL = 2376 |
| 18944 | CEFBS_HasSVE, // GLD1SW_D_IMM_REAL = 2377 |
| 18945 | CEFBS_HasSVE, // GLD1SW_D_REAL = 2378 |
| 18946 | CEFBS_HasSVE, // GLD1SW_D_SCALED_REAL = 2379 |
| 18947 | CEFBS_HasSVE, // GLD1SW_D_SXTW_REAL = 2380 |
| 18948 | CEFBS_HasSVE, // GLD1SW_D_SXTW_SCALED_REAL = 2381 |
| 18949 | CEFBS_HasSVE, // GLD1SW_D_UXTW_REAL = 2382 |
| 18950 | CEFBS_HasSVE, // GLD1SW_D_UXTW_SCALED_REAL = 2383 |
| 18951 | CEFBS_HasSVE, // GLD1W_D_IMM_REAL = 2384 |
| 18952 | CEFBS_HasSVE, // GLD1W_D_REAL = 2385 |
| 18953 | CEFBS_HasSVE, // GLD1W_D_SCALED_REAL = 2386 |
| 18954 | CEFBS_HasSVE, // GLD1W_D_SXTW_REAL = 2387 |
| 18955 | CEFBS_HasSVE, // GLD1W_D_SXTW_SCALED_REAL = 2388 |
| 18956 | CEFBS_HasSVE, // GLD1W_D_UXTW_REAL = 2389 |
| 18957 | CEFBS_HasSVE, // GLD1W_D_UXTW_SCALED_REAL = 2390 |
| 18958 | CEFBS_HasSVE, // GLD1W_IMM_REAL = 2391 |
| 18959 | CEFBS_HasSVE, // GLD1W_SXTW_REAL = 2392 |
| 18960 | CEFBS_HasSVE, // GLD1W_SXTW_SCALED_REAL = 2393 |
| 18961 | CEFBS_HasSVE, // GLD1W_UXTW_REAL = 2394 |
| 18962 | CEFBS_HasSVE, // GLD1W_UXTW_SCALED_REAL = 2395 |
| 18963 | CEFBS_HasSVE, // GLDFF1B_D_IMM_REAL = 2396 |
| 18964 | CEFBS_HasSVE, // GLDFF1B_D_REAL = 2397 |
| 18965 | CEFBS_HasSVE, // GLDFF1B_D_SXTW_REAL = 2398 |
| 18966 | CEFBS_HasSVE, // GLDFF1B_D_UXTW_REAL = 2399 |
| 18967 | CEFBS_HasSVE, // GLDFF1B_S_IMM_REAL = 2400 |
| 18968 | CEFBS_HasSVE, // GLDFF1B_S_SXTW_REAL = 2401 |
| 18969 | CEFBS_HasSVE, // GLDFF1B_S_UXTW_REAL = 2402 |
| 18970 | CEFBS_HasSVE, // GLDFF1D_IMM_REAL = 2403 |
| 18971 | CEFBS_HasSVE, // GLDFF1D_REAL = 2404 |
| 18972 | CEFBS_HasSVE, // GLDFF1D_SCALED_REAL = 2405 |
| 18973 | CEFBS_HasSVE, // GLDFF1D_SXTW_REAL = 2406 |
| 18974 | CEFBS_HasSVE, // GLDFF1D_SXTW_SCALED_REAL = 2407 |
| 18975 | CEFBS_HasSVE, // GLDFF1D_UXTW_REAL = 2408 |
| 18976 | CEFBS_HasSVE, // GLDFF1D_UXTW_SCALED_REAL = 2409 |
| 18977 | CEFBS_HasSVE, // GLDFF1H_D_IMM_REAL = 2410 |
| 18978 | CEFBS_HasSVE, // GLDFF1H_D_REAL = 2411 |
| 18979 | CEFBS_HasSVE, // GLDFF1H_D_SCALED_REAL = 2412 |
| 18980 | CEFBS_HasSVE, // GLDFF1H_D_SXTW_REAL = 2413 |
| 18981 | CEFBS_HasSVE, // GLDFF1H_D_SXTW_SCALED_REAL = 2414 |
| 18982 | CEFBS_HasSVE, // GLDFF1H_D_UXTW_REAL = 2415 |
| 18983 | CEFBS_HasSVE, // GLDFF1H_D_UXTW_SCALED_REAL = 2416 |
| 18984 | CEFBS_HasSVE, // GLDFF1H_S_IMM_REAL = 2417 |
| 18985 | CEFBS_HasSVE, // GLDFF1H_S_SXTW_REAL = 2418 |
| 18986 | CEFBS_HasSVE, // GLDFF1H_S_SXTW_SCALED_REAL = 2419 |
| 18987 | CEFBS_HasSVE, // GLDFF1H_S_UXTW_REAL = 2420 |
| 18988 | CEFBS_HasSVE, // GLDFF1H_S_UXTW_SCALED_REAL = 2421 |
| 18989 | CEFBS_HasSVE, // GLDFF1SB_D_IMM_REAL = 2422 |
| 18990 | CEFBS_HasSVE, // GLDFF1SB_D_REAL = 2423 |
| 18991 | CEFBS_HasSVE, // GLDFF1SB_D_SXTW_REAL = 2424 |
| 18992 | CEFBS_HasSVE, // GLDFF1SB_D_UXTW_REAL = 2425 |
| 18993 | CEFBS_HasSVE, // GLDFF1SB_S_IMM_REAL = 2426 |
| 18994 | CEFBS_HasSVE, // GLDFF1SB_S_SXTW_REAL = 2427 |
| 18995 | CEFBS_HasSVE, // GLDFF1SB_S_UXTW_REAL = 2428 |
| 18996 | CEFBS_HasSVE, // GLDFF1SH_D_IMM_REAL = 2429 |
| 18997 | CEFBS_HasSVE, // GLDFF1SH_D_REAL = 2430 |
| 18998 | CEFBS_HasSVE, // GLDFF1SH_D_SCALED_REAL = 2431 |
| 18999 | CEFBS_HasSVE, // GLDFF1SH_D_SXTW_REAL = 2432 |
| 19000 | CEFBS_HasSVE, // GLDFF1SH_D_SXTW_SCALED_REAL = 2433 |
| 19001 | CEFBS_HasSVE, // GLDFF1SH_D_UXTW_REAL = 2434 |
| 19002 | CEFBS_HasSVE, // GLDFF1SH_D_UXTW_SCALED_REAL = 2435 |
| 19003 | CEFBS_HasSVE, // GLDFF1SH_S_IMM_REAL = 2436 |
| 19004 | CEFBS_HasSVE, // GLDFF1SH_S_SXTW_REAL = 2437 |
| 19005 | CEFBS_HasSVE, // GLDFF1SH_S_SXTW_SCALED_REAL = 2438 |
| 19006 | CEFBS_HasSVE, // GLDFF1SH_S_UXTW_REAL = 2439 |
| 19007 | CEFBS_HasSVE, // GLDFF1SH_S_UXTW_SCALED_REAL = 2440 |
| 19008 | CEFBS_HasSVE, // GLDFF1SW_D_IMM_REAL = 2441 |
| 19009 | CEFBS_HasSVE, // GLDFF1SW_D_REAL = 2442 |
| 19010 | CEFBS_HasSVE, // GLDFF1SW_D_SCALED_REAL = 2443 |
| 19011 | CEFBS_HasSVE, // GLDFF1SW_D_SXTW_REAL = 2444 |
| 19012 | CEFBS_HasSVE, // GLDFF1SW_D_SXTW_SCALED_REAL = 2445 |
| 19013 | CEFBS_HasSVE, // GLDFF1SW_D_UXTW_REAL = 2446 |
| 19014 | CEFBS_HasSVE, // GLDFF1SW_D_UXTW_SCALED_REAL = 2447 |
| 19015 | CEFBS_HasSVE, // GLDFF1W_D_IMM_REAL = 2448 |
| 19016 | CEFBS_HasSVE, // GLDFF1W_D_REAL = 2449 |
| 19017 | CEFBS_HasSVE, // GLDFF1W_D_SCALED_REAL = 2450 |
| 19018 | CEFBS_HasSVE, // GLDFF1W_D_SXTW_REAL = 2451 |
| 19019 | CEFBS_HasSVE, // GLDFF1W_D_SXTW_SCALED_REAL = 2452 |
| 19020 | CEFBS_HasSVE, // GLDFF1W_D_UXTW_REAL = 2453 |
| 19021 | CEFBS_HasSVE, // GLDFF1W_D_UXTW_SCALED_REAL = 2454 |
| 19022 | CEFBS_HasSVE, // GLDFF1W_IMM_REAL = 2455 |
| 19023 | CEFBS_HasSVE, // GLDFF1W_SXTW_REAL = 2456 |
| 19024 | CEFBS_HasSVE, // GLDFF1W_SXTW_SCALED_REAL = 2457 |
| 19025 | CEFBS_HasSVE, // GLDFF1W_UXTW_REAL = 2458 |
| 19026 | CEFBS_HasSVE, // GLDFF1W_UXTW_SCALED_REAL = 2459 |
| 19027 | CEFBS_HasMTE, // GMI = 2460 |
| 19028 | CEFBS_None, // HINT = 2461 |
| 19029 | CEFBS_HasSVE2, // HISTCNT_ZPzZZ_D = 2462 |
| 19030 | CEFBS_HasSVE2, // HISTCNT_ZPzZZ_S = 2463 |
| 19031 | CEFBS_HasSVE2, // HISTSEG_ZZZ = 2464 |
| 19032 | CEFBS_None, // HLT = 2465 |
| 19033 | CEFBS_None, // HVC = 2466 |
| 19034 | CEFBS_HasSVE, // INCB_XPiI = 2467 |
| 19035 | CEFBS_HasSVE, // INCD_XPiI = 2468 |
| 19036 | CEFBS_HasSVE, // INCD_ZPiI = 2469 |
| 19037 | CEFBS_HasSVE, // INCH_XPiI = 2470 |
| 19038 | CEFBS_HasSVE, // INCH_ZPiI = 2471 |
| 19039 | CEFBS_HasSVE, // INCP_XP_B = 2472 |
| 19040 | CEFBS_HasSVE, // INCP_XP_D = 2473 |
| 19041 | CEFBS_HasSVE, // INCP_XP_H = 2474 |
| 19042 | CEFBS_HasSVE, // INCP_XP_S = 2475 |
| 19043 | CEFBS_HasSVE, // INCP_ZP_D = 2476 |
| 19044 | CEFBS_HasSVE, // INCP_ZP_H = 2477 |
| 19045 | CEFBS_HasSVE, // INCP_ZP_S = 2478 |
| 19046 | CEFBS_HasSVE, // INCW_XPiI = 2479 |
| 19047 | CEFBS_HasSVE, // INCW_ZPiI = 2480 |
| 19048 | CEFBS_HasSVE, // INDEX_II_B = 2481 |
| 19049 | CEFBS_HasSVE, // INDEX_II_D = 2482 |
| 19050 | CEFBS_HasSVE, // INDEX_II_H = 2483 |
| 19051 | CEFBS_HasSVE, // INDEX_II_S = 2484 |
| 19052 | CEFBS_HasSVE, // INDEX_IR_B = 2485 |
| 19053 | CEFBS_HasSVE, // INDEX_IR_D = 2486 |
| 19054 | CEFBS_HasSVE, // INDEX_IR_H = 2487 |
| 19055 | CEFBS_HasSVE, // INDEX_IR_S = 2488 |
| 19056 | CEFBS_HasSVE, // INDEX_RI_B = 2489 |
| 19057 | CEFBS_HasSVE, // INDEX_RI_D = 2490 |
| 19058 | CEFBS_HasSVE, // INDEX_RI_H = 2491 |
| 19059 | CEFBS_HasSVE, // INDEX_RI_S = 2492 |
| 19060 | CEFBS_HasSVE, // INDEX_RR_B = 2493 |
| 19061 | CEFBS_HasSVE, // INDEX_RR_D = 2494 |
| 19062 | CEFBS_HasSVE, // INDEX_RR_H = 2495 |
| 19063 | CEFBS_HasSVE, // INDEX_RR_S = 2496 |
| 19064 | CEFBS_HasSVE, // INSR_ZR_B = 2497 |
| 19065 | CEFBS_HasSVE, // INSR_ZR_D = 2498 |
| 19066 | CEFBS_HasSVE, // INSR_ZR_H = 2499 |
| 19067 | CEFBS_HasSVE, // INSR_ZR_S = 2500 |
| 19068 | CEFBS_HasSVE, // INSR_ZV_B = 2501 |
| 19069 | CEFBS_HasSVE, // INSR_ZV_D = 2502 |
| 19070 | CEFBS_HasSVE, // INSR_ZV_H = 2503 |
| 19071 | CEFBS_HasSVE, // INSR_ZV_S = 2504 |
| 19072 | CEFBS_HasNEON, // INSvi16gpr = 2505 |
| 19073 | CEFBS_HasNEON, // INSvi16lane = 2506 |
| 19074 | CEFBS_HasNEON, // INSvi32gpr = 2507 |
| 19075 | CEFBS_HasNEON, // INSvi32lane = 2508 |
| 19076 | CEFBS_HasNEON, // INSvi64gpr = 2509 |
| 19077 | CEFBS_HasNEON, // INSvi64lane = 2510 |
| 19078 | CEFBS_HasNEON, // INSvi8gpr = 2511 |
| 19079 | CEFBS_HasNEON, // INSvi8lane = 2512 |
| 19080 | CEFBS_HasMTE, // IRG = 2513 |
| 19081 | CEFBS_None, // ISB = 2514 |
| 19082 | CEFBS_HasSVE, // LASTA_RPZ_B = 2515 |
| 19083 | CEFBS_HasSVE, // LASTA_RPZ_D = 2516 |
| 19084 | CEFBS_HasSVE, // LASTA_RPZ_H = 2517 |
| 19085 | CEFBS_HasSVE, // LASTA_RPZ_S = 2518 |
| 19086 | CEFBS_HasSVE, // LASTA_VPZ_B = 2519 |
| 19087 | CEFBS_HasSVE, // LASTA_VPZ_D = 2520 |
| 19088 | CEFBS_HasSVE, // LASTA_VPZ_H = 2521 |
| 19089 | CEFBS_HasSVE, // LASTA_VPZ_S = 2522 |
| 19090 | CEFBS_HasSVE, // LASTB_RPZ_B = 2523 |
| 19091 | CEFBS_HasSVE, // LASTB_RPZ_D = 2524 |
| 19092 | CEFBS_HasSVE, // LASTB_RPZ_H = 2525 |
| 19093 | CEFBS_HasSVE, // LASTB_RPZ_S = 2526 |
| 19094 | CEFBS_HasSVE, // LASTB_VPZ_B = 2527 |
| 19095 | CEFBS_HasSVE, // LASTB_VPZ_D = 2528 |
| 19096 | CEFBS_HasSVE, // LASTB_VPZ_H = 2529 |
| 19097 | CEFBS_HasSVE, // LASTB_VPZ_S = 2530 |
| 19098 | CEFBS_HasSVE, // LD1B = 2531 |
| 19099 | CEFBS_HasSVE, // LD1B_D = 2532 |
| 19100 | CEFBS_HasSVE, // LD1B_D_IMM_REAL = 2533 |
| 19101 | CEFBS_HasSVE, // LD1B_H = 2534 |
| 19102 | CEFBS_HasSVE, // LD1B_H_IMM_REAL = 2535 |
| 19103 | CEFBS_HasSVE, // LD1B_IMM_REAL = 2536 |
| 19104 | CEFBS_HasSVE, // LD1B_S = 2537 |
| 19105 | CEFBS_HasSVE, // LD1B_S_IMM_REAL = 2538 |
| 19106 | CEFBS_HasSVE, // LD1D = 2539 |
| 19107 | CEFBS_HasSVE, // LD1D_IMM_REAL = 2540 |
| 19108 | CEFBS_HasNEON, // LD1Fourv16b = 2541 |
| 19109 | CEFBS_HasNEON, // LD1Fourv16b_POST = 2542 |
| 19110 | CEFBS_HasNEON, // LD1Fourv1d = 2543 |
| 19111 | CEFBS_HasNEON, // LD1Fourv1d_POST = 2544 |
| 19112 | CEFBS_HasNEON, // LD1Fourv2d = 2545 |
| 19113 | CEFBS_HasNEON, // LD1Fourv2d_POST = 2546 |
| 19114 | CEFBS_HasNEON, // LD1Fourv2s = 2547 |
| 19115 | CEFBS_HasNEON, // LD1Fourv2s_POST = 2548 |
| 19116 | CEFBS_HasNEON, // LD1Fourv4h = 2549 |
| 19117 | CEFBS_HasNEON, // LD1Fourv4h_POST = 2550 |
| 19118 | CEFBS_HasNEON, // LD1Fourv4s = 2551 |
| 19119 | CEFBS_HasNEON, // LD1Fourv4s_POST = 2552 |
| 19120 | CEFBS_HasNEON, // LD1Fourv8b = 2553 |
| 19121 | CEFBS_HasNEON, // LD1Fourv8b_POST = 2554 |
| 19122 | CEFBS_HasNEON, // LD1Fourv8h = 2555 |
| 19123 | CEFBS_HasNEON, // LD1Fourv8h_POST = 2556 |
| 19124 | CEFBS_HasSVE, // LD1H = 2557 |
| 19125 | CEFBS_HasSVE, // LD1H_D = 2558 |
| 19126 | CEFBS_HasSVE, // LD1H_D_IMM_REAL = 2559 |
| 19127 | CEFBS_HasSVE, // LD1H_IMM_REAL = 2560 |
| 19128 | CEFBS_HasSVE, // LD1H_S = 2561 |
| 19129 | CEFBS_HasSVE, // LD1H_S_IMM_REAL = 2562 |
| 19130 | CEFBS_HasNEON, // LD1Onev16b = 2563 |
| 19131 | CEFBS_HasNEON, // LD1Onev16b_POST = 2564 |
| 19132 | CEFBS_HasNEON, // LD1Onev1d = 2565 |
| 19133 | CEFBS_HasNEON, // LD1Onev1d_POST = 2566 |
| 19134 | CEFBS_HasNEON, // LD1Onev2d = 2567 |
| 19135 | CEFBS_HasNEON, // LD1Onev2d_POST = 2568 |
| 19136 | CEFBS_HasNEON, // LD1Onev2s = 2569 |
| 19137 | CEFBS_HasNEON, // LD1Onev2s_POST = 2570 |
| 19138 | CEFBS_HasNEON, // LD1Onev4h = 2571 |
| 19139 | CEFBS_HasNEON, // LD1Onev4h_POST = 2572 |
| 19140 | CEFBS_HasNEON, // LD1Onev4s = 2573 |
| 19141 | CEFBS_HasNEON, // LD1Onev4s_POST = 2574 |
| 19142 | CEFBS_HasNEON, // LD1Onev8b = 2575 |
| 19143 | CEFBS_HasNEON, // LD1Onev8b_POST = 2576 |
| 19144 | CEFBS_HasNEON, // LD1Onev8h = 2577 |
| 19145 | CEFBS_HasNEON, // LD1Onev8h_POST = 2578 |
| 19146 | CEFBS_HasSVE, // LD1RB_D_IMM = 2579 |
| 19147 | CEFBS_HasSVE, // LD1RB_H_IMM = 2580 |
| 19148 | CEFBS_HasSVE, // LD1RB_IMM = 2581 |
| 19149 | CEFBS_HasSVE, // LD1RB_S_IMM = 2582 |
| 19150 | CEFBS_HasSVE, // LD1RD_IMM = 2583 |
| 19151 | CEFBS_HasSVE, // LD1RH_D_IMM = 2584 |
| 19152 | CEFBS_HasSVE, // LD1RH_IMM = 2585 |
| 19153 | CEFBS_HasSVE, // LD1RH_S_IMM = 2586 |
| 19154 | CEFBS_HasSVE_HasMatMulFP64, // LD1RO_B = 2587 |
| 19155 | CEFBS_HasSVE_HasMatMulFP64, // LD1RO_B_IMM = 2588 |
| 19156 | CEFBS_HasSVE_HasMatMulFP64, // LD1RO_D = 2589 |
| 19157 | CEFBS_HasSVE_HasMatMulFP64, // LD1RO_D_IMM = 2590 |
| 19158 | CEFBS_HasSVE_HasMatMulFP64, // LD1RO_H = 2591 |
| 19159 | CEFBS_HasSVE_HasMatMulFP64, // LD1RO_H_IMM = 2592 |
| 19160 | CEFBS_HasSVE_HasMatMulFP64, // LD1RO_W = 2593 |
| 19161 | CEFBS_HasSVE_HasMatMulFP64, // LD1RO_W_IMM = 2594 |
| 19162 | CEFBS_HasSVE, // LD1RQ_B = 2595 |
| 19163 | CEFBS_HasSVE, // LD1RQ_B_IMM = 2596 |
| 19164 | CEFBS_HasSVE, // LD1RQ_D = 2597 |
| 19165 | CEFBS_HasSVE, // LD1RQ_D_IMM = 2598 |
| 19166 | CEFBS_HasSVE, // LD1RQ_H = 2599 |
| 19167 | CEFBS_HasSVE, // LD1RQ_H_IMM = 2600 |
| 19168 | CEFBS_HasSVE, // LD1RQ_W = 2601 |
| 19169 | CEFBS_HasSVE, // LD1RQ_W_IMM = 2602 |
| 19170 | CEFBS_HasSVE, // LD1RSB_D_IMM = 2603 |
| 19171 | CEFBS_HasSVE, // LD1RSB_H_IMM = 2604 |
| 19172 | CEFBS_HasSVE, // LD1RSB_S_IMM = 2605 |
| 19173 | CEFBS_HasSVE, // LD1RSH_D_IMM = 2606 |
| 19174 | CEFBS_HasSVE, // LD1RSH_S_IMM = 2607 |
| 19175 | CEFBS_HasSVE, // LD1RSW_IMM = 2608 |
| 19176 | CEFBS_HasSVE, // LD1RW_D_IMM = 2609 |
| 19177 | CEFBS_HasSVE, // LD1RW_IMM = 2610 |
| 19178 | CEFBS_HasNEON, // LD1Rv16b = 2611 |
| 19179 | CEFBS_HasNEON, // LD1Rv16b_POST = 2612 |
| 19180 | CEFBS_HasNEON, // LD1Rv1d = 2613 |
| 19181 | CEFBS_HasNEON, // LD1Rv1d_POST = 2614 |
| 19182 | CEFBS_HasNEON, // LD1Rv2d = 2615 |
| 19183 | CEFBS_HasNEON, // LD1Rv2d_POST = 2616 |
| 19184 | CEFBS_HasNEON, // LD1Rv2s = 2617 |
| 19185 | CEFBS_HasNEON, // LD1Rv2s_POST = 2618 |
| 19186 | CEFBS_HasNEON, // LD1Rv4h = 2619 |
| 19187 | CEFBS_HasNEON, // LD1Rv4h_POST = 2620 |
| 19188 | CEFBS_HasNEON, // LD1Rv4s = 2621 |
| 19189 | CEFBS_HasNEON, // LD1Rv4s_POST = 2622 |
| 19190 | CEFBS_HasNEON, // LD1Rv8b = 2623 |
| 19191 | CEFBS_HasNEON, // LD1Rv8b_POST = 2624 |
| 19192 | CEFBS_HasNEON, // LD1Rv8h = 2625 |
| 19193 | CEFBS_HasNEON, // LD1Rv8h_POST = 2626 |
| 19194 | CEFBS_HasSVE, // LD1SB_D = 2627 |
| 19195 | CEFBS_HasSVE, // LD1SB_D_IMM_REAL = 2628 |
| 19196 | CEFBS_HasSVE, // LD1SB_H = 2629 |
| 19197 | CEFBS_HasSVE, // LD1SB_H_IMM_REAL = 2630 |
| 19198 | CEFBS_HasSVE, // LD1SB_S = 2631 |
| 19199 | CEFBS_HasSVE, // LD1SB_S_IMM_REAL = 2632 |
| 19200 | CEFBS_HasSVE, // LD1SH_D = 2633 |
| 19201 | CEFBS_HasSVE, // LD1SH_D_IMM_REAL = 2634 |
| 19202 | CEFBS_HasSVE, // LD1SH_S = 2635 |
| 19203 | CEFBS_HasSVE, // LD1SH_S_IMM_REAL = 2636 |
| 19204 | CEFBS_HasSVE, // LD1SW_D = 2637 |
| 19205 | CEFBS_HasSVE, // LD1SW_D_IMM_REAL = 2638 |
| 19206 | CEFBS_HasNEON, // LD1Threev16b = 2639 |
| 19207 | CEFBS_HasNEON, // LD1Threev16b_POST = 2640 |
| 19208 | CEFBS_HasNEON, // LD1Threev1d = 2641 |
| 19209 | CEFBS_HasNEON, // LD1Threev1d_POST = 2642 |
| 19210 | CEFBS_HasNEON, // LD1Threev2d = 2643 |
| 19211 | CEFBS_HasNEON, // LD1Threev2d_POST = 2644 |
| 19212 | CEFBS_HasNEON, // LD1Threev2s = 2645 |
| 19213 | CEFBS_HasNEON, // LD1Threev2s_POST = 2646 |
| 19214 | CEFBS_HasNEON, // LD1Threev4h = 2647 |
| 19215 | CEFBS_HasNEON, // LD1Threev4h_POST = 2648 |
| 19216 | CEFBS_HasNEON, // LD1Threev4s = 2649 |
| 19217 | CEFBS_HasNEON, // LD1Threev4s_POST = 2650 |
| 19218 | CEFBS_HasNEON, // LD1Threev8b = 2651 |
| 19219 | CEFBS_HasNEON, // LD1Threev8b_POST = 2652 |
| 19220 | CEFBS_HasNEON, // LD1Threev8h = 2653 |
| 19221 | CEFBS_HasNEON, // LD1Threev8h_POST = 2654 |
| 19222 | CEFBS_HasNEON, // LD1Twov16b = 2655 |
| 19223 | CEFBS_HasNEON, // LD1Twov16b_POST = 2656 |
| 19224 | CEFBS_HasNEON, // LD1Twov1d = 2657 |
| 19225 | CEFBS_HasNEON, // LD1Twov1d_POST = 2658 |
| 19226 | CEFBS_HasNEON, // LD1Twov2d = 2659 |
| 19227 | CEFBS_HasNEON, // LD1Twov2d_POST = 2660 |
| 19228 | CEFBS_HasNEON, // LD1Twov2s = 2661 |
| 19229 | CEFBS_HasNEON, // LD1Twov2s_POST = 2662 |
| 19230 | CEFBS_HasNEON, // LD1Twov4h = 2663 |
| 19231 | CEFBS_HasNEON, // LD1Twov4h_POST = 2664 |
| 19232 | CEFBS_HasNEON, // LD1Twov4s = 2665 |
| 19233 | CEFBS_HasNEON, // LD1Twov4s_POST = 2666 |
| 19234 | CEFBS_HasNEON, // LD1Twov8b = 2667 |
| 19235 | CEFBS_HasNEON, // LD1Twov8b_POST = 2668 |
| 19236 | CEFBS_HasNEON, // LD1Twov8h = 2669 |
| 19237 | CEFBS_HasNEON, // LD1Twov8h_POST = 2670 |
| 19238 | CEFBS_HasSVE, // LD1W = 2671 |
| 19239 | CEFBS_HasSVE, // LD1W_D = 2672 |
| 19240 | CEFBS_HasSVE, // LD1W_D_IMM_REAL = 2673 |
| 19241 | CEFBS_HasSVE, // LD1W_IMM_REAL = 2674 |
| 19242 | CEFBS_HasNEON, // LD1i16 = 2675 |
| 19243 | CEFBS_HasNEON, // LD1i16_POST = 2676 |
| 19244 | CEFBS_HasNEON, // LD1i32 = 2677 |
| 19245 | CEFBS_HasNEON, // LD1i32_POST = 2678 |
| 19246 | CEFBS_HasNEON, // LD1i64 = 2679 |
| 19247 | CEFBS_HasNEON, // LD1i64_POST = 2680 |
| 19248 | CEFBS_HasNEON, // LD1i8 = 2681 |
| 19249 | CEFBS_HasNEON, // LD1i8_POST = 2682 |
| 19250 | CEFBS_HasSVE, // LD2B = 2683 |
| 19251 | CEFBS_HasSVE, // LD2B_IMM = 2684 |
| 19252 | CEFBS_HasSVE, // LD2D = 2685 |
| 19253 | CEFBS_HasSVE, // LD2D_IMM = 2686 |
| 19254 | CEFBS_HasSVE, // LD2H = 2687 |
| 19255 | CEFBS_HasSVE, // LD2H_IMM = 2688 |
| 19256 | CEFBS_HasNEON, // LD2Rv16b = 2689 |
| 19257 | CEFBS_HasNEON, // LD2Rv16b_POST = 2690 |
| 19258 | CEFBS_HasNEON, // LD2Rv1d = 2691 |
| 19259 | CEFBS_HasNEON, // LD2Rv1d_POST = 2692 |
| 19260 | CEFBS_HasNEON, // LD2Rv2d = 2693 |
| 19261 | CEFBS_HasNEON, // LD2Rv2d_POST = 2694 |
| 19262 | CEFBS_HasNEON, // LD2Rv2s = 2695 |
| 19263 | CEFBS_HasNEON, // LD2Rv2s_POST = 2696 |
| 19264 | CEFBS_HasNEON, // LD2Rv4h = 2697 |
| 19265 | CEFBS_HasNEON, // LD2Rv4h_POST = 2698 |
| 19266 | CEFBS_HasNEON, // LD2Rv4s = 2699 |
| 19267 | CEFBS_HasNEON, // LD2Rv4s_POST = 2700 |
| 19268 | CEFBS_HasNEON, // LD2Rv8b = 2701 |
| 19269 | CEFBS_HasNEON, // LD2Rv8b_POST = 2702 |
| 19270 | CEFBS_HasNEON, // LD2Rv8h = 2703 |
| 19271 | CEFBS_HasNEON, // LD2Rv8h_POST = 2704 |
| 19272 | CEFBS_HasNEON, // LD2Twov16b = 2705 |
| 19273 | CEFBS_HasNEON, // LD2Twov16b_POST = 2706 |
| 19274 | CEFBS_HasNEON, // LD2Twov2d = 2707 |
| 19275 | CEFBS_HasNEON, // LD2Twov2d_POST = 2708 |
| 19276 | CEFBS_HasNEON, // LD2Twov2s = 2709 |
| 19277 | CEFBS_HasNEON, // LD2Twov2s_POST = 2710 |
| 19278 | CEFBS_HasNEON, // LD2Twov4h = 2711 |
| 19279 | CEFBS_HasNEON, // LD2Twov4h_POST = 2712 |
| 19280 | CEFBS_HasNEON, // LD2Twov4s = 2713 |
| 19281 | CEFBS_HasNEON, // LD2Twov4s_POST = 2714 |
| 19282 | CEFBS_HasNEON, // LD2Twov8b = 2715 |
| 19283 | CEFBS_HasNEON, // LD2Twov8b_POST = 2716 |
| 19284 | CEFBS_HasNEON, // LD2Twov8h = 2717 |
| 19285 | CEFBS_HasNEON, // LD2Twov8h_POST = 2718 |
| 19286 | CEFBS_HasSVE, // LD2W = 2719 |
| 19287 | CEFBS_HasSVE, // LD2W_IMM = 2720 |
| 19288 | CEFBS_HasNEON, // LD2i16 = 2721 |
| 19289 | CEFBS_HasNEON, // LD2i16_POST = 2722 |
| 19290 | CEFBS_HasNEON, // LD2i32 = 2723 |
| 19291 | CEFBS_HasNEON, // LD2i32_POST = 2724 |
| 19292 | CEFBS_HasNEON, // LD2i64 = 2725 |
| 19293 | CEFBS_HasNEON, // LD2i64_POST = 2726 |
| 19294 | CEFBS_HasNEON, // LD2i8 = 2727 |
| 19295 | CEFBS_HasNEON, // LD2i8_POST = 2728 |
| 19296 | CEFBS_HasSVE, // LD3B = 2729 |
| 19297 | CEFBS_HasSVE, // LD3B_IMM = 2730 |
| 19298 | CEFBS_HasSVE, // LD3D = 2731 |
| 19299 | CEFBS_HasSVE, // LD3D_IMM = 2732 |
| 19300 | CEFBS_HasSVE, // LD3H = 2733 |
| 19301 | CEFBS_HasSVE, // LD3H_IMM = 2734 |
| 19302 | CEFBS_HasNEON, // LD3Rv16b = 2735 |
| 19303 | CEFBS_HasNEON, // LD3Rv16b_POST = 2736 |
| 19304 | CEFBS_HasNEON, // LD3Rv1d = 2737 |
| 19305 | CEFBS_HasNEON, // LD3Rv1d_POST = 2738 |
| 19306 | CEFBS_HasNEON, // LD3Rv2d = 2739 |
| 19307 | CEFBS_HasNEON, // LD3Rv2d_POST = 2740 |
| 19308 | CEFBS_HasNEON, // LD3Rv2s = 2741 |
| 19309 | CEFBS_HasNEON, // LD3Rv2s_POST = 2742 |
| 19310 | CEFBS_HasNEON, // LD3Rv4h = 2743 |
| 19311 | CEFBS_HasNEON, // LD3Rv4h_POST = 2744 |
| 19312 | CEFBS_HasNEON, // LD3Rv4s = 2745 |
| 19313 | CEFBS_HasNEON, // LD3Rv4s_POST = 2746 |
| 19314 | CEFBS_HasNEON, // LD3Rv8b = 2747 |
| 19315 | CEFBS_HasNEON, // LD3Rv8b_POST = 2748 |
| 19316 | CEFBS_HasNEON, // LD3Rv8h = 2749 |
| 19317 | CEFBS_HasNEON, // LD3Rv8h_POST = 2750 |
| 19318 | CEFBS_HasNEON, // LD3Threev16b = 2751 |
| 19319 | CEFBS_HasNEON, // LD3Threev16b_POST = 2752 |
| 19320 | CEFBS_HasNEON, // LD3Threev2d = 2753 |
| 19321 | CEFBS_HasNEON, // LD3Threev2d_POST = 2754 |
| 19322 | CEFBS_HasNEON, // LD3Threev2s = 2755 |
| 19323 | CEFBS_HasNEON, // LD3Threev2s_POST = 2756 |
| 19324 | CEFBS_HasNEON, // LD3Threev4h = 2757 |
| 19325 | CEFBS_HasNEON, // LD3Threev4h_POST = 2758 |
| 19326 | CEFBS_HasNEON, // LD3Threev4s = 2759 |
| 19327 | CEFBS_HasNEON, // LD3Threev4s_POST = 2760 |
| 19328 | CEFBS_HasNEON, // LD3Threev8b = 2761 |
| 19329 | CEFBS_HasNEON, // LD3Threev8b_POST = 2762 |
| 19330 | CEFBS_HasNEON, // LD3Threev8h = 2763 |
| 19331 | CEFBS_HasNEON, // LD3Threev8h_POST = 2764 |
| 19332 | CEFBS_HasSVE, // LD3W = 2765 |
| 19333 | CEFBS_HasSVE, // LD3W_IMM = 2766 |
| 19334 | CEFBS_HasNEON, // LD3i16 = 2767 |
| 19335 | CEFBS_HasNEON, // LD3i16_POST = 2768 |
| 19336 | CEFBS_HasNEON, // LD3i32 = 2769 |
| 19337 | CEFBS_HasNEON, // LD3i32_POST = 2770 |
| 19338 | CEFBS_HasNEON, // LD3i64 = 2771 |
| 19339 | CEFBS_HasNEON, // LD3i64_POST = 2772 |
| 19340 | CEFBS_HasNEON, // LD3i8 = 2773 |
| 19341 | CEFBS_HasNEON, // LD3i8_POST = 2774 |
| 19342 | CEFBS_HasSVE, // LD4B = 2775 |
| 19343 | CEFBS_HasSVE, // LD4B_IMM = 2776 |
| 19344 | CEFBS_HasSVE, // LD4D = 2777 |
| 19345 | CEFBS_HasSVE, // LD4D_IMM = 2778 |
| 19346 | CEFBS_HasNEON, // LD4Fourv16b = 2779 |
| 19347 | CEFBS_HasNEON, // LD4Fourv16b_POST = 2780 |
| 19348 | CEFBS_HasNEON, // LD4Fourv2d = 2781 |
| 19349 | CEFBS_HasNEON, // LD4Fourv2d_POST = 2782 |
| 19350 | CEFBS_HasNEON, // LD4Fourv2s = 2783 |
| 19351 | CEFBS_HasNEON, // LD4Fourv2s_POST = 2784 |
| 19352 | CEFBS_HasNEON, // LD4Fourv4h = 2785 |
| 19353 | CEFBS_HasNEON, // LD4Fourv4h_POST = 2786 |
| 19354 | CEFBS_HasNEON, // LD4Fourv4s = 2787 |
| 19355 | CEFBS_HasNEON, // LD4Fourv4s_POST = 2788 |
| 19356 | CEFBS_HasNEON, // LD4Fourv8b = 2789 |
| 19357 | CEFBS_HasNEON, // LD4Fourv8b_POST = 2790 |
| 19358 | CEFBS_HasNEON, // LD4Fourv8h = 2791 |
| 19359 | CEFBS_HasNEON, // LD4Fourv8h_POST = 2792 |
| 19360 | CEFBS_HasSVE, // LD4H = 2793 |
| 19361 | CEFBS_HasSVE, // LD4H_IMM = 2794 |
| 19362 | CEFBS_HasNEON, // LD4Rv16b = 2795 |
| 19363 | CEFBS_HasNEON, // LD4Rv16b_POST = 2796 |
| 19364 | CEFBS_HasNEON, // LD4Rv1d = 2797 |
| 19365 | CEFBS_HasNEON, // LD4Rv1d_POST = 2798 |
| 19366 | CEFBS_HasNEON, // LD4Rv2d = 2799 |
| 19367 | CEFBS_HasNEON, // LD4Rv2d_POST = 2800 |
| 19368 | CEFBS_HasNEON, // LD4Rv2s = 2801 |
| 19369 | CEFBS_HasNEON, // LD4Rv2s_POST = 2802 |
| 19370 | CEFBS_HasNEON, // LD4Rv4h = 2803 |
| 19371 | CEFBS_HasNEON, // LD4Rv4h_POST = 2804 |
| 19372 | CEFBS_HasNEON, // LD4Rv4s = 2805 |
| 19373 | CEFBS_HasNEON, // LD4Rv4s_POST = 2806 |
| 19374 | CEFBS_HasNEON, // LD4Rv8b = 2807 |
| 19375 | CEFBS_HasNEON, // LD4Rv8b_POST = 2808 |
| 19376 | CEFBS_HasNEON, // LD4Rv8h = 2809 |
| 19377 | CEFBS_HasNEON, // LD4Rv8h_POST = 2810 |
| 19378 | CEFBS_HasSVE, // LD4W = 2811 |
| 19379 | CEFBS_HasSVE, // LD4W_IMM = 2812 |
| 19380 | CEFBS_HasNEON, // LD4i16 = 2813 |
| 19381 | CEFBS_HasNEON, // LD4i16_POST = 2814 |
| 19382 | CEFBS_HasNEON, // LD4i32 = 2815 |
| 19383 | CEFBS_HasNEON, // LD4i32_POST = 2816 |
| 19384 | CEFBS_HasNEON, // LD4i64 = 2817 |
| 19385 | CEFBS_HasNEON, // LD4i64_POST = 2818 |
| 19386 | CEFBS_HasNEON, // LD4i8 = 2819 |
| 19387 | CEFBS_HasNEON, // LD4i8_POST = 2820 |
| 19388 | CEFBS_HasLS64, // LD64B = 2821 |
| 19389 | CEFBS_HasLSE, // LDADDAB = 2822 |
| 19390 | CEFBS_HasLSE, // LDADDAH = 2823 |
| 19391 | CEFBS_HasLSE, // LDADDALB = 2824 |
| 19392 | CEFBS_HasLSE, // LDADDALH = 2825 |
| 19393 | CEFBS_HasLSE, // LDADDALW = 2826 |
| 19394 | CEFBS_HasLSE, // LDADDALX = 2827 |
| 19395 | CEFBS_HasLSE, // LDADDAW = 2828 |
| 19396 | CEFBS_HasLSE, // LDADDAX = 2829 |
| 19397 | CEFBS_HasLSE, // LDADDB = 2830 |
| 19398 | CEFBS_HasLSE, // LDADDH = 2831 |
| 19399 | CEFBS_HasLSE, // LDADDLB = 2832 |
| 19400 | CEFBS_HasLSE, // LDADDLH = 2833 |
| 19401 | CEFBS_HasLSE, // LDADDLW = 2834 |
| 19402 | CEFBS_HasLSE, // LDADDLX = 2835 |
| 19403 | CEFBS_HasLSE, // LDADDW = 2836 |
| 19404 | CEFBS_HasLSE, // LDADDX = 2837 |
| 19405 | CEFBS_HasRCPC, // LDAPRB = 2838 |
| 19406 | CEFBS_HasRCPC, // LDAPRH = 2839 |
| 19407 | CEFBS_HasRCPC, // LDAPRW = 2840 |
| 19408 | CEFBS_HasRCPC, // LDAPRX = 2841 |
| 19409 | CEFBS_HasRCPC_IMMO, // LDAPURBi = 2842 |
| 19410 | CEFBS_HasRCPC_IMMO, // LDAPURHi = 2843 |
| 19411 | CEFBS_HasRCPC_IMMO, // LDAPURSBWi = 2844 |
| 19412 | CEFBS_HasRCPC_IMMO, // LDAPURSBXi = 2845 |
| 19413 | CEFBS_HasRCPC_IMMO, // LDAPURSHWi = 2846 |
| 19414 | CEFBS_HasRCPC_IMMO, // LDAPURSHXi = 2847 |
| 19415 | CEFBS_HasRCPC_IMMO, // LDAPURSWi = 2848 |
| 19416 | CEFBS_HasRCPC_IMMO, // LDAPURXi = 2849 |
| 19417 | CEFBS_HasRCPC_IMMO, // LDAPURi = 2850 |
| 19418 | CEFBS_None, // LDARB = 2851 |
| 19419 | CEFBS_None, // LDARH = 2852 |
| 19420 | CEFBS_None, // LDARW = 2853 |
| 19421 | CEFBS_None, // LDARX = 2854 |
| 19422 | CEFBS_None, // LDAXPW = 2855 |
| 19423 | CEFBS_None, // LDAXPX = 2856 |
| 19424 | CEFBS_None, // LDAXRB = 2857 |
| 19425 | CEFBS_None, // LDAXRH = 2858 |
| 19426 | CEFBS_None, // LDAXRW = 2859 |
| 19427 | CEFBS_None, // LDAXRX = 2860 |
| 19428 | CEFBS_HasLSE, // LDCLRAB = 2861 |
| 19429 | CEFBS_HasLSE, // LDCLRAH = 2862 |
| 19430 | CEFBS_HasLSE, // LDCLRALB = 2863 |
| 19431 | CEFBS_HasLSE, // LDCLRALH = 2864 |
| 19432 | CEFBS_HasLSE, // LDCLRALW = 2865 |
| 19433 | CEFBS_HasLSE, // LDCLRALX = 2866 |
| 19434 | CEFBS_HasLSE, // LDCLRAW = 2867 |
| 19435 | CEFBS_HasLSE, // LDCLRAX = 2868 |
| 19436 | CEFBS_HasLSE, // LDCLRB = 2869 |
| 19437 | CEFBS_HasLSE, // LDCLRH = 2870 |
| 19438 | CEFBS_HasLSE, // LDCLRLB = 2871 |
| 19439 | CEFBS_HasLSE, // LDCLRLH = 2872 |
| 19440 | CEFBS_HasLSE, // LDCLRLW = 2873 |
| 19441 | CEFBS_HasLSE, // LDCLRLX = 2874 |
| 19442 | CEFBS_HasLSE, // LDCLRW = 2875 |
| 19443 | CEFBS_HasLSE, // LDCLRX = 2876 |
| 19444 | CEFBS_HasLSE, // LDEORAB = 2877 |
| 19445 | CEFBS_HasLSE, // LDEORAH = 2878 |
| 19446 | CEFBS_HasLSE, // LDEORALB = 2879 |
| 19447 | CEFBS_HasLSE, // LDEORALH = 2880 |
| 19448 | CEFBS_HasLSE, // LDEORALW = 2881 |
| 19449 | CEFBS_HasLSE, // LDEORALX = 2882 |
| 19450 | CEFBS_HasLSE, // LDEORAW = 2883 |
| 19451 | CEFBS_HasLSE, // LDEORAX = 2884 |
| 19452 | CEFBS_HasLSE, // LDEORB = 2885 |
| 19453 | CEFBS_HasLSE, // LDEORH = 2886 |
| 19454 | CEFBS_HasLSE, // LDEORLB = 2887 |
| 19455 | CEFBS_HasLSE, // LDEORLH = 2888 |
| 19456 | CEFBS_HasLSE, // LDEORLW = 2889 |
| 19457 | CEFBS_HasLSE, // LDEORLX = 2890 |
| 19458 | CEFBS_HasLSE, // LDEORW = 2891 |
| 19459 | CEFBS_HasLSE, // LDEORX = 2892 |
| 19460 | CEFBS_HasSVE, // LDFF1B_D_REAL = 2893 |
| 19461 | CEFBS_HasSVE, // LDFF1B_H_REAL = 2894 |
| 19462 | CEFBS_HasSVE, // LDFF1B_REAL = 2895 |
| 19463 | CEFBS_HasSVE, // LDFF1B_S_REAL = 2896 |
| 19464 | CEFBS_HasSVE, // LDFF1D_REAL = 2897 |
| 19465 | CEFBS_HasSVE, // LDFF1H_D_REAL = 2898 |
| 19466 | CEFBS_HasSVE, // LDFF1H_REAL = 2899 |
| 19467 | CEFBS_HasSVE, // LDFF1H_S_REAL = 2900 |
| 19468 | CEFBS_HasSVE, // LDFF1SB_D_REAL = 2901 |
| 19469 | CEFBS_HasSVE, // LDFF1SB_H_REAL = 2902 |
| 19470 | CEFBS_HasSVE, // LDFF1SB_S_REAL = 2903 |
| 19471 | CEFBS_HasSVE, // LDFF1SH_D_REAL = 2904 |
| 19472 | CEFBS_HasSVE, // LDFF1SH_S_REAL = 2905 |
| 19473 | CEFBS_HasSVE, // LDFF1SW_D_REAL = 2906 |
| 19474 | CEFBS_HasSVE, // LDFF1W_D_REAL = 2907 |
| 19475 | CEFBS_HasSVE, // LDFF1W_REAL = 2908 |
| 19476 | CEFBS_HasMTE, // LDG = 2909 |
| 19477 | CEFBS_HasMTE, // LDGM = 2910 |
| 19478 | CEFBS_HasLOR, // LDLARB = 2911 |
| 19479 | CEFBS_HasLOR, // LDLARH = 2912 |
| 19480 | CEFBS_HasLOR, // LDLARW = 2913 |
| 19481 | CEFBS_HasLOR, // LDLARX = 2914 |
| 19482 | CEFBS_HasSVE, // LDNF1B_D_IMM_REAL = 2915 |
| 19483 | CEFBS_HasSVE, // LDNF1B_H_IMM_REAL = 2916 |
| 19484 | CEFBS_HasSVE, // LDNF1B_IMM_REAL = 2917 |
| 19485 | CEFBS_HasSVE, // LDNF1B_S_IMM_REAL = 2918 |
| 19486 | CEFBS_HasSVE, // LDNF1D_IMM_REAL = 2919 |
| 19487 | CEFBS_HasSVE, // LDNF1H_D_IMM_REAL = 2920 |
| 19488 | CEFBS_HasSVE, // LDNF1H_IMM_REAL = 2921 |
| 19489 | CEFBS_HasSVE, // LDNF1H_S_IMM_REAL = 2922 |
| 19490 | CEFBS_HasSVE, // LDNF1SB_D_IMM_REAL = 2923 |
| 19491 | CEFBS_HasSVE, // LDNF1SB_H_IMM_REAL = 2924 |
| 19492 | CEFBS_HasSVE, // LDNF1SB_S_IMM_REAL = 2925 |
| 19493 | CEFBS_HasSVE, // LDNF1SH_D_IMM_REAL = 2926 |
| 19494 | CEFBS_HasSVE, // LDNF1SH_S_IMM_REAL = 2927 |
| 19495 | CEFBS_HasSVE, // LDNF1SW_D_IMM_REAL = 2928 |
| 19496 | CEFBS_HasSVE, // LDNF1W_D_IMM_REAL = 2929 |
| 19497 | CEFBS_HasSVE, // LDNF1W_IMM_REAL = 2930 |
| 19498 | CEFBS_None, // LDNPDi = 2931 |
| 19499 | CEFBS_None, // LDNPQi = 2932 |
| 19500 | CEFBS_None, // LDNPSi = 2933 |
| 19501 | CEFBS_None, // LDNPWi = 2934 |
| 19502 | CEFBS_None, // LDNPXi = 2935 |
| 19503 | CEFBS_HasSVE, // LDNT1B_ZRI = 2936 |
| 19504 | CEFBS_HasSVE, // LDNT1B_ZRR = 2937 |
| 19505 | CEFBS_HasSVE2, // LDNT1B_ZZR_D_REAL = 2938 |
| 19506 | CEFBS_HasSVE2, // LDNT1B_ZZR_S_REAL = 2939 |
| 19507 | CEFBS_HasSVE, // LDNT1D_ZRI = 2940 |
| 19508 | CEFBS_HasSVE, // LDNT1D_ZRR = 2941 |
| 19509 | CEFBS_HasSVE2, // LDNT1D_ZZR_D_REAL = 2942 |
| 19510 | CEFBS_HasSVE, // LDNT1H_ZRI = 2943 |
| 19511 | CEFBS_HasSVE, // LDNT1H_ZRR = 2944 |
| 19512 | CEFBS_HasSVE2, // LDNT1H_ZZR_D_REAL = 2945 |
| 19513 | CEFBS_HasSVE2, // LDNT1H_ZZR_S_REAL = 2946 |
| 19514 | CEFBS_HasSVE2, // LDNT1SB_ZZR_D_REAL = 2947 |
| 19515 | CEFBS_HasSVE2, // LDNT1SB_ZZR_S_REAL = 2948 |
| 19516 | CEFBS_HasSVE2, // LDNT1SH_ZZR_D_REAL = 2949 |
| 19517 | CEFBS_HasSVE2, // LDNT1SH_ZZR_S_REAL = 2950 |
| 19518 | CEFBS_HasSVE2, // LDNT1SW_ZZR_D_REAL = 2951 |
| 19519 | CEFBS_HasSVE, // LDNT1W_ZRI = 2952 |
| 19520 | CEFBS_HasSVE, // LDNT1W_ZRR = 2953 |
| 19521 | CEFBS_HasSVE2, // LDNT1W_ZZR_D_REAL = 2954 |
| 19522 | CEFBS_HasSVE2, // LDNT1W_ZZR_S_REAL = 2955 |
| 19523 | CEFBS_None, // LDPDi = 2956 |
| 19524 | CEFBS_None, // LDPDpost = 2957 |
| 19525 | CEFBS_None, // LDPDpre = 2958 |
| 19526 | CEFBS_None, // LDPQi = 2959 |
| 19527 | CEFBS_None, // LDPQpost = 2960 |
| 19528 | CEFBS_None, // LDPQpre = 2961 |
| 19529 | CEFBS_None, // LDPSWi = 2962 |
| 19530 | CEFBS_None, // LDPSWpost = 2963 |
| 19531 | CEFBS_None, // LDPSWpre = 2964 |
| 19532 | CEFBS_None, // LDPSi = 2965 |
| 19533 | CEFBS_None, // LDPSpost = 2966 |
| 19534 | CEFBS_None, // LDPSpre = 2967 |
| 19535 | CEFBS_None, // LDPWi = 2968 |
| 19536 | CEFBS_None, // LDPWpost = 2969 |
| 19537 | CEFBS_None, // LDPWpre = 2970 |
| 19538 | CEFBS_None, // LDPXi = 2971 |
| 19539 | CEFBS_None, // LDPXpost = 2972 |
| 19540 | CEFBS_None, // LDPXpre = 2973 |
| 19541 | CEFBS_HasPAuth, // LDRAAindexed = 2974 |
| 19542 | CEFBS_HasPAuth, // LDRAAwriteback = 2975 |
| 19543 | CEFBS_HasPAuth, // LDRABindexed = 2976 |
| 19544 | CEFBS_HasPAuth, // LDRABwriteback = 2977 |
| 19545 | CEFBS_None, // LDRBBpost = 2978 |
| 19546 | CEFBS_None, // LDRBBpre = 2979 |
| 19547 | CEFBS_None, // LDRBBroW = 2980 |
| 19548 | CEFBS_None, // LDRBBroX = 2981 |
| 19549 | CEFBS_None, // LDRBBui = 2982 |
| 19550 | CEFBS_None, // LDRBpost = 2983 |
| 19551 | CEFBS_None, // LDRBpre = 2984 |
| 19552 | CEFBS_None, // LDRBroW = 2985 |
| 19553 | CEFBS_None, // LDRBroX = 2986 |
| 19554 | CEFBS_None, // LDRBui = 2987 |
| 19555 | CEFBS_None, // LDRDl = 2988 |
| 19556 | CEFBS_None, // LDRDpost = 2989 |
| 19557 | CEFBS_None, // LDRDpre = 2990 |
| 19558 | CEFBS_None, // LDRDroW = 2991 |
| 19559 | CEFBS_None, // LDRDroX = 2992 |
| 19560 | CEFBS_None, // LDRDui = 2993 |
| 19561 | CEFBS_None, // LDRHHpost = 2994 |
| 19562 | CEFBS_None, // LDRHHpre = 2995 |
| 19563 | CEFBS_None, // LDRHHroW = 2996 |
| 19564 | CEFBS_None, // LDRHHroX = 2997 |
| 19565 | CEFBS_None, // LDRHHui = 2998 |
| 19566 | CEFBS_None, // LDRHpost = 2999 |
| 19567 | CEFBS_None, // LDRHpre = 3000 |
| 19568 | CEFBS_None, // LDRHroW = 3001 |
| 19569 | CEFBS_None, // LDRHroX = 3002 |
| 19570 | CEFBS_None, // LDRHui = 3003 |
| 19571 | CEFBS_None, // LDRQl = 3004 |
| 19572 | CEFBS_None, // LDRQpost = 3005 |
| 19573 | CEFBS_None, // LDRQpre = 3006 |
| 19574 | CEFBS_None, // LDRQroW = 3007 |
| 19575 | CEFBS_None, // LDRQroX = 3008 |
| 19576 | CEFBS_None, // LDRQui = 3009 |
| 19577 | CEFBS_None, // LDRSBWpost = 3010 |
| 19578 | CEFBS_None, // LDRSBWpre = 3011 |
| 19579 | CEFBS_None, // LDRSBWroW = 3012 |
| 19580 | CEFBS_None, // LDRSBWroX = 3013 |
| 19581 | CEFBS_None, // LDRSBWui = 3014 |
| 19582 | CEFBS_None, // LDRSBXpost = 3015 |
| 19583 | CEFBS_None, // LDRSBXpre = 3016 |
| 19584 | CEFBS_None, // LDRSBXroW = 3017 |
| 19585 | CEFBS_None, // LDRSBXroX = 3018 |
| 19586 | CEFBS_None, // LDRSBXui = 3019 |
| 19587 | CEFBS_None, // LDRSHWpost = 3020 |
| 19588 | CEFBS_None, // LDRSHWpre = 3021 |
| 19589 | CEFBS_None, // LDRSHWroW = 3022 |
| 19590 | CEFBS_None, // LDRSHWroX = 3023 |
| 19591 | CEFBS_None, // LDRSHWui = 3024 |
| 19592 | CEFBS_None, // LDRSHXpost = 3025 |
| 19593 | CEFBS_None, // LDRSHXpre = 3026 |
| 19594 | CEFBS_None, // LDRSHXroW = 3027 |
| 19595 | CEFBS_None, // LDRSHXroX = 3028 |
| 19596 | CEFBS_None, // LDRSHXui = 3029 |
| 19597 | CEFBS_None, // LDRSWl = 3030 |
| 19598 | CEFBS_None, // LDRSWpost = 3031 |
| 19599 | CEFBS_None, // LDRSWpre = 3032 |
| 19600 | CEFBS_None, // LDRSWroW = 3033 |
| 19601 | CEFBS_None, // LDRSWroX = 3034 |
| 19602 | CEFBS_None, // LDRSWui = 3035 |
| 19603 | CEFBS_None, // LDRSl = 3036 |
| 19604 | CEFBS_None, // LDRSpost = 3037 |
| 19605 | CEFBS_None, // LDRSpre = 3038 |
| 19606 | CEFBS_None, // LDRSroW = 3039 |
| 19607 | CEFBS_None, // LDRSroX = 3040 |
| 19608 | CEFBS_None, // LDRSui = 3041 |
| 19609 | CEFBS_None, // LDRWl = 3042 |
| 19610 | CEFBS_None, // LDRWpost = 3043 |
| 19611 | CEFBS_None, // LDRWpre = 3044 |
| 19612 | CEFBS_None, // LDRWroW = 3045 |
| 19613 | CEFBS_None, // LDRWroX = 3046 |
| 19614 | CEFBS_None, // LDRWui = 3047 |
| 19615 | CEFBS_None, // LDRXl = 3048 |
| 19616 | CEFBS_None, // LDRXpost = 3049 |
| 19617 | CEFBS_None, // LDRXpre = 3050 |
| 19618 | CEFBS_None, // LDRXroW = 3051 |
| 19619 | CEFBS_None, // LDRXroX = 3052 |
| 19620 | CEFBS_None, // LDRXui = 3053 |
| 19621 | CEFBS_HasSVE, // LDR_PXI = 3054 |
| 19622 | CEFBS_HasSVE, // LDR_ZXI = 3055 |
| 19623 | CEFBS_HasLSE, // LDSETAB = 3056 |
| 19624 | CEFBS_HasLSE, // LDSETAH = 3057 |
| 19625 | CEFBS_HasLSE, // LDSETALB = 3058 |
| 19626 | CEFBS_HasLSE, // LDSETALH = 3059 |
| 19627 | CEFBS_HasLSE, // LDSETALW = 3060 |
| 19628 | CEFBS_HasLSE, // LDSETALX = 3061 |
| 19629 | CEFBS_HasLSE, // LDSETAW = 3062 |
| 19630 | CEFBS_HasLSE, // LDSETAX = 3063 |
| 19631 | CEFBS_HasLSE, // LDSETB = 3064 |
| 19632 | CEFBS_HasLSE, // LDSETH = 3065 |
| 19633 | CEFBS_HasLSE, // LDSETLB = 3066 |
| 19634 | CEFBS_HasLSE, // LDSETLH = 3067 |
| 19635 | CEFBS_HasLSE, // LDSETLW = 3068 |
| 19636 | CEFBS_HasLSE, // LDSETLX = 3069 |
| 19637 | CEFBS_HasLSE, // LDSETW = 3070 |
| 19638 | CEFBS_HasLSE, // LDSETX = 3071 |
| 19639 | CEFBS_HasLSE, // LDSMAXAB = 3072 |
| 19640 | CEFBS_HasLSE, // LDSMAXAH = 3073 |
| 19641 | CEFBS_HasLSE, // LDSMAXALB = 3074 |
| 19642 | CEFBS_HasLSE, // LDSMAXALH = 3075 |
| 19643 | CEFBS_HasLSE, // LDSMAXALW = 3076 |
| 19644 | CEFBS_HasLSE, // LDSMAXALX = 3077 |
| 19645 | CEFBS_HasLSE, // LDSMAXAW = 3078 |
| 19646 | CEFBS_HasLSE, // LDSMAXAX = 3079 |
| 19647 | CEFBS_HasLSE, // LDSMAXB = 3080 |
| 19648 | CEFBS_HasLSE, // LDSMAXH = 3081 |
| 19649 | CEFBS_HasLSE, // LDSMAXLB = 3082 |
| 19650 | CEFBS_HasLSE, // LDSMAXLH = 3083 |
| 19651 | CEFBS_HasLSE, // LDSMAXLW = 3084 |
| 19652 | CEFBS_HasLSE, // LDSMAXLX = 3085 |
| 19653 | CEFBS_HasLSE, // LDSMAXW = 3086 |
| 19654 | CEFBS_HasLSE, // LDSMAXX = 3087 |
| 19655 | CEFBS_HasLSE, // LDSMINAB = 3088 |
| 19656 | CEFBS_HasLSE, // LDSMINAH = 3089 |
| 19657 | CEFBS_HasLSE, // LDSMINALB = 3090 |
| 19658 | CEFBS_HasLSE, // LDSMINALH = 3091 |
| 19659 | CEFBS_HasLSE, // LDSMINALW = 3092 |
| 19660 | CEFBS_HasLSE, // LDSMINALX = 3093 |
| 19661 | CEFBS_HasLSE, // LDSMINAW = 3094 |
| 19662 | CEFBS_HasLSE, // LDSMINAX = 3095 |
| 19663 | CEFBS_HasLSE, // LDSMINB = 3096 |
| 19664 | CEFBS_HasLSE, // LDSMINH = 3097 |
| 19665 | CEFBS_HasLSE, // LDSMINLB = 3098 |
| 19666 | CEFBS_HasLSE, // LDSMINLH = 3099 |
| 19667 | CEFBS_HasLSE, // LDSMINLW = 3100 |
| 19668 | CEFBS_HasLSE, // LDSMINLX = 3101 |
| 19669 | CEFBS_HasLSE, // LDSMINW = 3102 |
| 19670 | CEFBS_HasLSE, // LDSMINX = 3103 |
| 19671 | CEFBS_None, // LDTRBi = 3104 |
| 19672 | CEFBS_None, // LDTRHi = 3105 |
| 19673 | CEFBS_None, // LDTRSBWi = 3106 |
| 19674 | CEFBS_None, // LDTRSBXi = 3107 |
| 19675 | CEFBS_None, // LDTRSHWi = 3108 |
| 19676 | CEFBS_None, // LDTRSHXi = 3109 |
| 19677 | CEFBS_None, // LDTRSWi = 3110 |
| 19678 | CEFBS_None, // LDTRWi = 3111 |
| 19679 | CEFBS_None, // LDTRXi = 3112 |
| 19680 | CEFBS_HasLSE, // LDUMAXAB = 3113 |
| 19681 | CEFBS_HasLSE, // LDUMAXAH = 3114 |
| 19682 | CEFBS_HasLSE, // LDUMAXALB = 3115 |
| 19683 | CEFBS_HasLSE, // LDUMAXALH = 3116 |
| 19684 | CEFBS_HasLSE, // LDUMAXALW = 3117 |
| 19685 | CEFBS_HasLSE, // LDUMAXALX = 3118 |
| 19686 | CEFBS_HasLSE, // LDUMAXAW = 3119 |
| 19687 | CEFBS_HasLSE, // LDUMAXAX = 3120 |
| 19688 | CEFBS_HasLSE, // LDUMAXB = 3121 |
| 19689 | CEFBS_HasLSE, // LDUMAXH = 3122 |
| 19690 | CEFBS_HasLSE, // LDUMAXLB = 3123 |
| 19691 | CEFBS_HasLSE, // LDUMAXLH = 3124 |
| 19692 | CEFBS_HasLSE, // LDUMAXLW = 3125 |
| 19693 | CEFBS_HasLSE, // LDUMAXLX = 3126 |
| 19694 | CEFBS_HasLSE, // LDUMAXW = 3127 |
| 19695 | CEFBS_HasLSE, // LDUMAXX = 3128 |
| 19696 | CEFBS_HasLSE, // LDUMINAB = 3129 |
| 19697 | CEFBS_HasLSE, // LDUMINAH = 3130 |
| 19698 | CEFBS_HasLSE, // LDUMINALB = 3131 |
| 19699 | CEFBS_HasLSE, // LDUMINALH = 3132 |
| 19700 | CEFBS_HasLSE, // LDUMINALW = 3133 |
| 19701 | CEFBS_HasLSE, // LDUMINALX = 3134 |
| 19702 | CEFBS_HasLSE, // LDUMINAW = 3135 |
| 19703 | CEFBS_HasLSE, // LDUMINAX = 3136 |
| 19704 | CEFBS_HasLSE, // LDUMINB = 3137 |
| 19705 | CEFBS_HasLSE, // LDUMINH = 3138 |
| 19706 | CEFBS_HasLSE, // LDUMINLB = 3139 |
| 19707 | CEFBS_HasLSE, // LDUMINLH = 3140 |
| 19708 | CEFBS_HasLSE, // LDUMINLW = 3141 |
| 19709 | CEFBS_HasLSE, // LDUMINLX = 3142 |
| 19710 | CEFBS_HasLSE, // LDUMINW = 3143 |
| 19711 | CEFBS_HasLSE, // LDUMINX = 3144 |
| 19712 | CEFBS_None, // LDURBBi = 3145 |
| 19713 | CEFBS_None, // LDURBi = 3146 |
| 19714 | CEFBS_None, // LDURDi = 3147 |
| 19715 | CEFBS_None, // LDURHHi = 3148 |
| 19716 | CEFBS_None, // LDURHi = 3149 |
| 19717 | CEFBS_None, // LDURQi = 3150 |
| 19718 | CEFBS_None, // LDURSBWi = 3151 |
| 19719 | CEFBS_None, // LDURSBXi = 3152 |
| 19720 | CEFBS_None, // LDURSHWi = 3153 |
| 19721 | CEFBS_None, // LDURSHXi = 3154 |
| 19722 | CEFBS_None, // LDURSWi = 3155 |
| 19723 | CEFBS_None, // LDURSi = 3156 |
| 19724 | CEFBS_None, // LDURWi = 3157 |
| 19725 | CEFBS_None, // LDURXi = 3158 |
| 19726 | CEFBS_None, // LDXPW = 3159 |
| 19727 | CEFBS_None, // LDXPX = 3160 |
| 19728 | CEFBS_None, // LDXRB = 3161 |
| 19729 | CEFBS_None, // LDXRH = 3162 |
| 19730 | CEFBS_None, // LDXRW = 3163 |
| 19731 | CEFBS_None, // LDXRX = 3164 |
| 19732 | CEFBS_HasSVE, // LSLR_ZPmZ_B = 3165 |
| 19733 | CEFBS_HasSVE, // LSLR_ZPmZ_D = 3166 |
| 19734 | CEFBS_HasSVE, // LSLR_ZPmZ_H = 3167 |
| 19735 | CEFBS_HasSVE, // LSLR_ZPmZ_S = 3168 |
| 19736 | CEFBS_None, // LSLVWr = 3169 |
| 19737 | CEFBS_None, // LSLVXr = 3170 |
| 19738 | CEFBS_HasSVE, // LSL_WIDE_ZPmZ_B = 3171 |
| 19739 | CEFBS_HasSVE, // LSL_WIDE_ZPmZ_H = 3172 |
| 19740 | CEFBS_HasSVE, // LSL_WIDE_ZPmZ_S = 3173 |
| 19741 | CEFBS_HasSVE, // LSL_WIDE_ZZZ_B = 3174 |
| 19742 | CEFBS_HasSVE, // LSL_WIDE_ZZZ_H = 3175 |
| 19743 | CEFBS_HasSVE, // LSL_WIDE_ZZZ_S = 3176 |
| 19744 | CEFBS_HasSVE, // LSL_ZPmI_B = 3177 |
| 19745 | CEFBS_HasSVE, // LSL_ZPmI_D = 3178 |
| 19746 | CEFBS_HasSVE, // LSL_ZPmI_H = 3179 |
| 19747 | CEFBS_HasSVE, // LSL_ZPmI_S = 3180 |
| 19748 | CEFBS_HasSVE, // LSL_ZPmZ_B = 3181 |
| 19749 | CEFBS_HasSVE, // LSL_ZPmZ_D = 3182 |
| 19750 | CEFBS_HasSVE, // LSL_ZPmZ_H = 3183 |
| 19751 | CEFBS_HasSVE, // LSL_ZPmZ_S = 3184 |
| 19752 | CEFBS_HasSVE, // LSL_ZZI_B = 3185 |
| 19753 | CEFBS_HasSVE, // LSL_ZZI_D = 3186 |
| 19754 | CEFBS_HasSVE, // LSL_ZZI_H = 3187 |
| 19755 | CEFBS_HasSVE, // LSL_ZZI_S = 3188 |
| 19756 | CEFBS_HasSVE, // LSRR_ZPmZ_B = 3189 |
| 19757 | CEFBS_HasSVE, // LSRR_ZPmZ_D = 3190 |
| 19758 | CEFBS_HasSVE, // LSRR_ZPmZ_H = 3191 |
| 19759 | CEFBS_HasSVE, // LSRR_ZPmZ_S = 3192 |
| 19760 | CEFBS_None, // LSRVWr = 3193 |
| 19761 | CEFBS_None, // LSRVXr = 3194 |
| 19762 | CEFBS_HasSVE, // LSR_WIDE_ZPmZ_B = 3195 |
| 19763 | CEFBS_HasSVE, // LSR_WIDE_ZPmZ_H = 3196 |
| 19764 | CEFBS_HasSVE, // LSR_WIDE_ZPmZ_S = 3197 |
| 19765 | CEFBS_HasSVE, // LSR_WIDE_ZZZ_B = 3198 |
| 19766 | CEFBS_HasSVE, // LSR_WIDE_ZZZ_H = 3199 |
| 19767 | CEFBS_HasSVE, // LSR_WIDE_ZZZ_S = 3200 |
| 19768 | CEFBS_HasSVE, // LSR_ZPmI_B = 3201 |
| 19769 | CEFBS_HasSVE, // LSR_ZPmI_D = 3202 |
| 19770 | CEFBS_HasSVE, // LSR_ZPmI_H = 3203 |
| 19771 | CEFBS_HasSVE, // LSR_ZPmI_S = 3204 |
| 19772 | CEFBS_HasSVE, // LSR_ZPmZ_B = 3205 |
| 19773 | CEFBS_HasSVE, // LSR_ZPmZ_D = 3206 |
| 19774 | CEFBS_HasSVE, // LSR_ZPmZ_H = 3207 |
| 19775 | CEFBS_HasSVE, // LSR_ZPmZ_S = 3208 |
| 19776 | CEFBS_HasSVE, // LSR_ZZI_B = 3209 |
| 19777 | CEFBS_HasSVE, // LSR_ZZI_D = 3210 |
| 19778 | CEFBS_HasSVE, // LSR_ZZI_H = 3211 |
| 19779 | CEFBS_HasSVE, // LSR_ZZI_S = 3212 |
| 19780 | CEFBS_None, // MADDWrrr = 3213 |
| 19781 | CEFBS_None, // MADDXrrr = 3214 |
| 19782 | CEFBS_HasSVE, // MAD_ZPmZZ_B = 3215 |
| 19783 | CEFBS_HasSVE, // MAD_ZPmZZ_D = 3216 |
| 19784 | CEFBS_HasSVE, // MAD_ZPmZZ_H = 3217 |
| 19785 | CEFBS_HasSVE, // MAD_ZPmZZ_S = 3218 |
| 19786 | CEFBS_HasSVE2, // MATCH_PPzZZ_B = 3219 |
| 19787 | CEFBS_HasSVE2, // MATCH_PPzZZ_H = 3220 |
| 19788 | CEFBS_HasSVE, // MLA_ZPmZZ_B = 3221 |
| 19789 | CEFBS_HasSVE, // MLA_ZPmZZ_D = 3222 |
| 19790 | CEFBS_HasSVE, // MLA_ZPmZZ_H = 3223 |
| 19791 | CEFBS_HasSVE, // MLA_ZPmZZ_S = 3224 |
| 19792 | CEFBS_HasSVE2, // MLA_ZZZI_D = 3225 |
| 19793 | CEFBS_HasSVE2, // MLA_ZZZI_H = 3226 |
| 19794 | CEFBS_HasSVE2, // MLA_ZZZI_S = 3227 |
| 19795 | CEFBS_HasNEON, // MLAv16i8 = 3228 |
| 19796 | CEFBS_HasNEON, // MLAv2i32 = 3229 |
| 19797 | CEFBS_HasNEON, // MLAv2i32_indexed = 3230 |
| 19798 | CEFBS_HasNEON, // MLAv4i16 = 3231 |
| 19799 | CEFBS_HasNEON, // MLAv4i16_indexed = 3232 |
| 19800 | CEFBS_HasNEON, // MLAv4i32 = 3233 |
| 19801 | CEFBS_HasNEON, // MLAv4i32_indexed = 3234 |
| 19802 | CEFBS_HasNEON, // MLAv8i16 = 3235 |
| 19803 | CEFBS_HasNEON, // MLAv8i16_indexed = 3236 |
| 19804 | CEFBS_HasNEON, // MLAv8i8 = 3237 |
| 19805 | CEFBS_HasSVE, // MLS_ZPmZZ_B = 3238 |
| 19806 | CEFBS_HasSVE, // MLS_ZPmZZ_D = 3239 |
| 19807 | CEFBS_HasSVE, // MLS_ZPmZZ_H = 3240 |
| 19808 | CEFBS_HasSVE, // MLS_ZPmZZ_S = 3241 |
| 19809 | CEFBS_HasSVE2, // MLS_ZZZI_D = 3242 |
| 19810 | CEFBS_HasSVE2, // MLS_ZZZI_H = 3243 |
| 19811 | CEFBS_HasSVE2, // MLS_ZZZI_S = 3244 |
| 19812 | CEFBS_HasNEON, // MLSv16i8 = 3245 |
| 19813 | CEFBS_HasNEON, // MLSv2i32 = 3246 |
| 19814 | CEFBS_HasNEON, // MLSv2i32_indexed = 3247 |
| 19815 | CEFBS_HasNEON, // MLSv4i16 = 3248 |
| 19816 | CEFBS_HasNEON, // MLSv4i16_indexed = 3249 |
| 19817 | CEFBS_HasNEON, // MLSv4i32 = 3250 |
| 19818 | CEFBS_HasNEON, // MLSv4i32_indexed = 3251 |
| 19819 | CEFBS_HasNEON, // MLSv8i16 = 3252 |
| 19820 | CEFBS_HasNEON, // MLSv8i16_indexed = 3253 |
| 19821 | CEFBS_HasNEON, // MLSv8i8 = 3254 |
| 19822 | CEFBS_HasNEON, // MOVID = 3255 |
| 19823 | CEFBS_HasNEON, // MOVIv16b_ns = 3256 |
| 19824 | CEFBS_HasNEON, // MOVIv2d_ns = 3257 |
| 19825 | CEFBS_HasNEON, // MOVIv2i32 = 3258 |
| 19826 | CEFBS_HasNEON, // MOVIv2s_msl = 3259 |
| 19827 | CEFBS_HasNEON, // MOVIv4i16 = 3260 |
| 19828 | CEFBS_HasNEON, // MOVIv4i32 = 3261 |
| 19829 | CEFBS_HasNEON, // MOVIv4s_msl = 3262 |
| 19830 | CEFBS_HasNEON, // MOVIv8b_ns = 3263 |
| 19831 | CEFBS_HasNEON, // MOVIv8i16 = 3264 |
| 19832 | CEFBS_None, // MOVKWi = 3265 |
| 19833 | CEFBS_None, // MOVKXi = 3266 |
| 19834 | CEFBS_None, // MOVNWi = 3267 |
| 19835 | CEFBS_None, // MOVNXi = 3268 |
| 19836 | CEFBS_HasSVE, // MOVPRFX_ZPmZ_B = 3269 |
| 19837 | CEFBS_HasSVE, // MOVPRFX_ZPmZ_D = 3270 |
| 19838 | CEFBS_HasSVE, // MOVPRFX_ZPmZ_H = 3271 |
| 19839 | CEFBS_HasSVE, // MOVPRFX_ZPmZ_S = 3272 |
| 19840 | CEFBS_HasSVE, // MOVPRFX_ZPzZ_B = 3273 |
| 19841 | CEFBS_HasSVE, // MOVPRFX_ZPzZ_D = 3274 |
| 19842 | CEFBS_HasSVE, // MOVPRFX_ZPzZ_H = 3275 |
| 19843 | CEFBS_HasSVE, // MOVPRFX_ZPzZ_S = 3276 |
| 19844 | CEFBS_HasSVE, // MOVPRFX_ZZ = 3277 |
| 19845 | CEFBS_None, // MOVZWi = 3278 |
| 19846 | CEFBS_None, // MOVZXi = 3279 |
| 19847 | CEFBS_None, // MRS = 3280 |
| 19848 | CEFBS_HasSVE, // MSB_ZPmZZ_B = 3281 |
| 19849 | CEFBS_HasSVE, // MSB_ZPmZZ_D = 3282 |
| 19850 | CEFBS_HasSVE, // MSB_ZPmZZ_H = 3283 |
| 19851 | CEFBS_HasSVE, // MSB_ZPmZZ_S = 3284 |
| 19852 | CEFBS_None, // MSR = 3285 |
| 19853 | CEFBS_None, // MSRpstateImm1 = 3286 |
| 19854 | CEFBS_None, // MSRpstateImm4 = 3287 |
| 19855 | CEFBS_None, // MSUBWrrr = 3288 |
| 19856 | CEFBS_None, // MSUBXrrr = 3289 |
| 19857 | CEFBS_HasSVE, // MUL_ZI_B = 3290 |
| 19858 | CEFBS_HasSVE, // MUL_ZI_D = 3291 |
| 19859 | CEFBS_HasSVE, // MUL_ZI_H = 3292 |
| 19860 | CEFBS_HasSVE, // MUL_ZI_S = 3293 |
| 19861 | CEFBS_HasSVE, // MUL_ZPmZ_B = 3294 |
| 19862 | CEFBS_HasSVE, // MUL_ZPmZ_D = 3295 |
| 19863 | CEFBS_HasSVE, // MUL_ZPmZ_H = 3296 |
| 19864 | CEFBS_HasSVE, // MUL_ZPmZ_S = 3297 |
| 19865 | CEFBS_HasSVE2, // MUL_ZZZI_D = 3298 |
| 19866 | CEFBS_HasSVE2, // MUL_ZZZI_H = 3299 |
| 19867 | CEFBS_HasSVE2, // MUL_ZZZI_S = 3300 |
| 19868 | CEFBS_HasSVE2, // MUL_ZZZ_B = 3301 |
| 19869 | CEFBS_HasSVE2, // MUL_ZZZ_D = 3302 |
| 19870 | CEFBS_HasSVE2, // MUL_ZZZ_H = 3303 |
| 19871 | CEFBS_HasSVE2, // MUL_ZZZ_S = 3304 |
| 19872 | CEFBS_HasNEON, // MULv16i8 = 3305 |
| 19873 | CEFBS_HasNEON, // MULv2i32 = 3306 |
| 19874 | CEFBS_HasNEON, // MULv2i32_indexed = 3307 |
| 19875 | CEFBS_HasNEON, // MULv4i16 = 3308 |
| 19876 | CEFBS_HasNEON, // MULv4i16_indexed = 3309 |
| 19877 | CEFBS_HasNEON, // MULv4i32 = 3310 |
| 19878 | CEFBS_HasNEON, // MULv4i32_indexed = 3311 |
| 19879 | CEFBS_HasNEON, // MULv8i16 = 3312 |
| 19880 | CEFBS_HasNEON, // MULv8i16_indexed = 3313 |
| 19881 | CEFBS_HasNEON, // MULv8i8 = 3314 |
| 19882 | CEFBS_HasNEON, // MVNIv2i32 = 3315 |
| 19883 | CEFBS_HasNEON, // MVNIv2s_msl = 3316 |
| 19884 | CEFBS_HasNEON, // MVNIv4i16 = 3317 |
| 19885 | CEFBS_HasNEON, // MVNIv4i32 = 3318 |
| 19886 | CEFBS_HasNEON, // MVNIv4s_msl = 3319 |
| 19887 | CEFBS_HasNEON, // MVNIv8i16 = 3320 |
| 19888 | CEFBS_HasSVE, // NANDS_PPzPP = 3321 |
| 19889 | CEFBS_HasSVE, // NAND_PPzPP = 3322 |
| 19890 | CEFBS_HasSVE2, // NBSL_ZZZZ = 3323 |
| 19891 | CEFBS_HasSVE, // NEG_ZPmZ_B = 3324 |
| 19892 | CEFBS_HasSVE, // NEG_ZPmZ_D = 3325 |
| 19893 | CEFBS_HasSVE, // NEG_ZPmZ_H = 3326 |
| 19894 | CEFBS_HasSVE, // NEG_ZPmZ_S = 3327 |
| 19895 | CEFBS_HasNEON, // NEGv16i8 = 3328 |
| 19896 | CEFBS_HasNEON, // NEGv1i64 = 3329 |
| 19897 | CEFBS_HasNEON, // NEGv2i32 = 3330 |
| 19898 | CEFBS_HasNEON, // NEGv2i64 = 3331 |
| 19899 | CEFBS_HasNEON, // NEGv4i16 = 3332 |
| 19900 | CEFBS_HasNEON, // NEGv4i32 = 3333 |
| 19901 | CEFBS_HasNEON, // NEGv8i16 = 3334 |
| 19902 | CEFBS_HasNEON, // NEGv8i8 = 3335 |
| 19903 | CEFBS_HasSVE2, // NMATCH_PPzZZ_B = 3336 |
| 19904 | CEFBS_HasSVE2, // NMATCH_PPzZZ_H = 3337 |
| 19905 | CEFBS_HasSVE, // NORS_PPzPP = 3338 |
| 19906 | CEFBS_HasSVE, // NOR_PPzPP = 3339 |
| 19907 | CEFBS_HasSVE, // NOT_ZPmZ_B = 3340 |
| 19908 | CEFBS_HasSVE, // NOT_ZPmZ_D = 3341 |
| 19909 | CEFBS_HasSVE, // NOT_ZPmZ_H = 3342 |
| 19910 | CEFBS_HasSVE, // NOT_ZPmZ_S = 3343 |
| 19911 | CEFBS_HasNEON, // NOTv16i8 = 3344 |
| 19912 | CEFBS_HasNEON, // NOTv8i8 = 3345 |
| 19913 | CEFBS_HasSVE, // ORNS_PPzPP = 3346 |
| 19914 | CEFBS_None, // ORNWrs = 3347 |
| 19915 | CEFBS_None, // ORNXrs = 3348 |
| 19916 | CEFBS_HasSVE, // ORN_PPzPP = 3349 |
| 19917 | CEFBS_HasNEON, // ORNv16i8 = 3350 |
| 19918 | CEFBS_HasNEON, // ORNv8i8 = 3351 |
| 19919 | CEFBS_HasSVE, // ORRS_PPzPP = 3352 |
| 19920 | CEFBS_None, // ORRWri = 3353 |
| 19921 | CEFBS_None, // ORRWrs = 3354 |
| 19922 | CEFBS_None, // ORRXri = 3355 |
| 19923 | CEFBS_None, // ORRXrs = 3356 |
| 19924 | CEFBS_HasSVE, // ORR_PPzPP = 3357 |
| 19925 | CEFBS_HasSVE, // ORR_ZI = 3358 |
| 19926 | CEFBS_HasSVE, // ORR_ZPmZ_B = 3359 |
| 19927 | CEFBS_HasSVE, // ORR_ZPmZ_D = 3360 |
| 19928 | CEFBS_HasSVE, // ORR_ZPmZ_H = 3361 |
| 19929 | CEFBS_HasSVE, // ORR_ZPmZ_S = 3362 |
| 19930 | CEFBS_HasSVE, // ORR_ZZZ = 3363 |
| 19931 | CEFBS_HasNEON, // ORRv16i8 = 3364 |
| 19932 | CEFBS_HasNEON, // ORRv2i32 = 3365 |
| 19933 | CEFBS_HasNEON, // ORRv4i16 = 3366 |
| 19934 | CEFBS_HasNEON, // ORRv4i32 = 3367 |
| 19935 | CEFBS_HasNEON, // ORRv8i16 = 3368 |
| 19936 | CEFBS_HasNEON, // ORRv8i8 = 3369 |
| 19937 | CEFBS_HasSVE, // ORV_VPZ_B = 3370 |
| 19938 | CEFBS_HasSVE, // ORV_VPZ_D = 3371 |
| 19939 | CEFBS_HasSVE, // ORV_VPZ_H = 3372 |
| 19940 | CEFBS_HasSVE, // ORV_VPZ_S = 3373 |
| 19941 | CEFBS_HasPAuth, // PACDA = 3374 |
| 19942 | CEFBS_HasPAuth, // PACDB = 3375 |
| 19943 | CEFBS_HasPAuth, // PACDZA = 3376 |
| 19944 | CEFBS_HasPAuth, // PACDZB = 3377 |
| 19945 | CEFBS_HasPAuth, // PACGA = 3378 |
| 19946 | CEFBS_HasPAuth, // PACIA = 3379 |
| 19947 | CEFBS_None, // PACIA1716 = 3380 |
| 19948 | CEFBS_None, // PACIASP = 3381 |
| 19949 | CEFBS_None, // PACIAZ = 3382 |
| 19950 | CEFBS_HasPAuth, // PACIB = 3383 |
| 19951 | CEFBS_None, // PACIB1716 = 3384 |
| 19952 | CEFBS_None, // PACIBSP = 3385 |
| 19953 | CEFBS_None, // PACIBZ = 3386 |
| 19954 | CEFBS_HasPAuth, // PACIZA = 3387 |
| 19955 | CEFBS_HasPAuth, // PACIZB = 3388 |
| 19956 | CEFBS_HasSVE, // PFALSE = 3389 |
| 19957 | CEFBS_HasSVE, // PFIRST_B = 3390 |
| 19958 | CEFBS_HasSVE2, // PMULLB_ZZZ_D = 3391 |
| 19959 | CEFBS_HasSVE2, // PMULLB_ZZZ_H = 3392 |
| 19960 | CEFBS_HasSVE2AES, // PMULLB_ZZZ_Q = 3393 |
| 19961 | CEFBS_HasSVE2, // PMULLT_ZZZ_D = 3394 |
| 19962 | CEFBS_HasSVE2, // PMULLT_ZZZ_H = 3395 |
| 19963 | CEFBS_HasSVE2AES, // PMULLT_ZZZ_Q = 3396 |
| 19964 | CEFBS_HasNEON, // PMULLv16i8 = 3397 |
| 19965 | CEFBS_HasAES, // PMULLv1i64 = 3398 |
| 19966 | CEFBS_HasAES, // PMULLv2i64 = 3399 |
| 19967 | CEFBS_HasNEON, // PMULLv8i8 = 3400 |
| 19968 | CEFBS_HasSVE2, // PMUL_ZZZ_B = 3401 |
| 19969 | CEFBS_HasNEON, // PMULv16i8 = 3402 |
| 19970 | CEFBS_HasNEON, // PMULv8i8 = 3403 |
| 19971 | CEFBS_HasSVE, // PNEXT_B = 3404 |
| 19972 | CEFBS_HasSVE, // PNEXT_D = 3405 |
| 19973 | CEFBS_HasSVE, // PNEXT_H = 3406 |
| 19974 | CEFBS_HasSVE, // PNEXT_S = 3407 |
| 19975 | CEFBS_HasSVE, // PRFB_D_PZI = 3408 |
| 19976 | CEFBS_HasSVE, // PRFB_D_SCALED = 3409 |
| 19977 | CEFBS_HasSVE, // PRFB_D_SXTW_SCALED = 3410 |
| 19978 | CEFBS_HasSVE, // PRFB_D_UXTW_SCALED = 3411 |
| 19979 | CEFBS_HasSVE, // PRFB_PRI = 3412 |
| 19980 | CEFBS_HasSVE, // PRFB_PRR = 3413 |
| 19981 | CEFBS_HasSVE, // PRFB_S_PZI = 3414 |
| 19982 | CEFBS_HasSVE, // PRFB_S_SXTW_SCALED = 3415 |
| 19983 | CEFBS_HasSVE, // PRFB_S_UXTW_SCALED = 3416 |
| 19984 | CEFBS_HasSVE, // PRFD_D_PZI = 3417 |
| 19985 | CEFBS_HasSVE, // PRFD_D_SCALED = 3418 |
| 19986 | CEFBS_HasSVE, // PRFD_D_SXTW_SCALED = 3419 |
| 19987 | CEFBS_HasSVE, // PRFD_D_UXTW_SCALED = 3420 |
| 19988 | CEFBS_HasSVE, // PRFD_PRI = 3421 |
| 19989 | CEFBS_HasSVE, // PRFD_PRR = 3422 |
| 19990 | CEFBS_HasSVE, // PRFD_S_PZI = 3423 |
| 19991 | CEFBS_HasSVE, // PRFD_S_SXTW_SCALED = 3424 |
| 19992 | CEFBS_HasSVE, // PRFD_S_UXTW_SCALED = 3425 |
| 19993 | CEFBS_HasSVE, // PRFH_D_PZI = 3426 |
| 19994 | CEFBS_HasSVE, // PRFH_D_SCALED = 3427 |
| 19995 | CEFBS_HasSVE, // PRFH_D_SXTW_SCALED = 3428 |
| 19996 | CEFBS_HasSVE, // PRFH_D_UXTW_SCALED = 3429 |
| 19997 | CEFBS_HasSVE, // PRFH_PRI = 3430 |
| 19998 | CEFBS_HasSVE, // PRFH_PRR = 3431 |
| 19999 | CEFBS_HasSVE, // PRFH_S_PZI = 3432 |
| 20000 | CEFBS_HasSVE, // PRFH_S_SXTW_SCALED = 3433 |
| 20001 | CEFBS_HasSVE, // PRFH_S_UXTW_SCALED = 3434 |
| 20002 | CEFBS_None, // PRFMl = 3435 |
| 20003 | CEFBS_None, // PRFMroW = 3436 |
| 20004 | CEFBS_None, // PRFMroX = 3437 |
| 20005 | CEFBS_None, // PRFMui = 3438 |
| 20006 | CEFBS_HasSVE, // PRFS_PRR = 3439 |
| 20007 | CEFBS_None, // PRFUMi = 3440 |
| 20008 | CEFBS_HasSVE, // PRFW_D_PZI = 3441 |
| 20009 | CEFBS_HasSVE, // PRFW_D_SCALED = 3442 |
| 20010 | CEFBS_HasSVE, // PRFW_D_SXTW_SCALED = 3443 |
| 20011 | CEFBS_HasSVE, // PRFW_D_UXTW_SCALED = 3444 |
| 20012 | CEFBS_HasSVE, // PRFW_PRI = 3445 |
| 20013 | CEFBS_HasSVE, // PRFW_S_PZI = 3446 |
| 20014 | CEFBS_HasSVE, // PRFW_S_SXTW_SCALED = 3447 |
| 20015 | CEFBS_HasSVE, // PRFW_S_UXTW_SCALED = 3448 |
| 20016 | CEFBS_HasSVE, // PTEST_PP = 3449 |
| 20017 | CEFBS_HasSVE, // PTRUES_B = 3450 |
| 20018 | CEFBS_HasSVE, // PTRUES_D = 3451 |
| 20019 | CEFBS_HasSVE, // PTRUES_H = 3452 |
| 20020 | CEFBS_HasSVE, // PTRUES_S = 3453 |
| 20021 | CEFBS_HasSVE, // PTRUE_B = 3454 |
| 20022 | CEFBS_HasSVE, // PTRUE_D = 3455 |
| 20023 | CEFBS_HasSVE, // PTRUE_H = 3456 |
| 20024 | CEFBS_HasSVE, // PTRUE_S = 3457 |
| 20025 | CEFBS_HasSVE, // PUNPKHI_PP = 3458 |
| 20026 | CEFBS_HasSVE, // PUNPKLO_PP = 3459 |
| 20027 | CEFBS_HasSVE2, // RADDHNB_ZZZ_B = 3460 |
| 20028 | CEFBS_HasSVE2, // RADDHNB_ZZZ_H = 3461 |
| 20029 | CEFBS_HasSVE2, // RADDHNB_ZZZ_S = 3462 |
| 20030 | CEFBS_HasSVE2, // RADDHNT_ZZZ_B = 3463 |
| 20031 | CEFBS_HasSVE2, // RADDHNT_ZZZ_H = 3464 |
| 20032 | CEFBS_HasSVE2, // RADDHNT_ZZZ_S = 3465 |
| 20033 | CEFBS_HasNEON, // RADDHNv2i64_v2i32 = 3466 |
| 20034 | CEFBS_HasNEON, // RADDHNv2i64_v4i32 = 3467 |
| 20035 | CEFBS_HasNEON, // RADDHNv4i32_v4i16 = 3468 |
| 20036 | CEFBS_HasNEON, // RADDHNv4i32_v8i16 = 3469 |
| 20037 | CEFBS_HasNEON, // RADDHNv8i16_v16i8 = 3470 |
| 20038 | CEFBS_HasNEON, // RADDHNv8i16_v8i8 = 3471 |
| 20039 | CEFBS_HasSHA3, // RAX1 = 3472 |
| 20040 | CEFBS_HasSVE2SHA3, // RAX1_ZZZ_D = 3473 |
| 20041 | CEFBS_None, // RBITWr = 3474 |
| 20042 | CEFBS_None, // RBITXr = 3475 |
| 20043 | CEFBS_HasSVE, // RBIT_ZPmZ_B = 3476 |
| 20044 | CEFBS_HasSVE, // RBIT_ZPmZ_D = 3477 |
| 20045 | CEFBS_HasSVE, // RBIT_ZPmZ_H = 3478 |
| 20046 | CEFBS_HasSVE, // RBIT_ZPmZ_S = 3479 |
| 20047 | CEFBS_HasNEON, // RBITv16i8 = 3480 |
| 20048 | CEFBS_HasNEON, // RBITv8i8 = 3481 |
| 20049 | CEFBS_HasSVE, // RDFFRS_PPz = 3482 |
| 20050 | CEFBS_HasSVE, // RDFFR_PPz_REAL = 3483 |
| 20051 | CEFBS_HasSVE, // RDFFR_P_REAL = 3484 |
| 20052 | CEFBS_HasSVE, // RDVLI_XI = 3485 |
| 20053 | CEFBS_None, // RET = 3486 |
| 20054 | CEFBS_HasPAuth, // RETAA = 3487 |
| 20055 | CEFBS_HasPAuth, // RETAB = 3488 |
| 20056 | CEFBS_None, // REV16Wr = 3489 |
| 20057 | CEFBS_None, // REV16Xr = 3490 |
| 20058 | CEFBS_HasNEON, // REV16v16i8 = 3491 |
| 20059 | CEFBS_HasNEON, // REV16v8i8 = 3492 |
| 20060 | CEFBS_None, // REV32Xr = 3493 |
| 20061 | CEFBS_HasNEON, // REV32v16i8 = 3494 |
| 20062 | CEFBS_HasNEON, // REV32v4i16 = 3495 |
| 20063 | CEFBS_HasNEON, // REV32v8i16 = 3496 |
| 20064 | CEFBS_HasNEON, // REV32v8i8 = 3497 |
| 20065 | CEFBS_HasNEON, // REV64v16i8 = 3498 |
| 20066 | CEFBS_HasNEON, // REV64v2i32 = 3499 |
| 20067 | CEFBS_HasNEON, // REV64v4i16 = 3500 |
| 20068 | CEFBS_HasNEON, // REV64v4i32 = 3501 |
| 20069 | CEFBS_HasNEON, // REV64v8i16 = 3502 |
| 20070 | CEFBS_HasNEON, // REV64v8i8 = 3503 |
| 20071 | CEFBS_HasSVE, // REVB_ZPmZ_D = 3504 |
| 20072 | CEFBS_HasSVE, // REVB_ZPmZ_H = 3505 |
| 20073 | CEFBS_HasSVE, // REVB_ZPmZ_S = 3506 |
| 20074 | CEFBS_HasSVE, // REVH_ZPmZ_D = 3507 |
| 20075 | CEFBS_HasSVE, // REVH_ZPmZ_S = 3508 |
| 20076 | CEFBS_HasSVE, // REVW_ZPmZ_D = 3509 |
| 20077 | CEFBS_None, // REVWr = 3510 |
| 20078 | CEFBS_None, // REVXr = 3511 |
| 20079 | CEFBS_HasSVE, // REV_PP_B = 3512 |
| 20080 | CEFBS_HasSVE, // REV_PP_D = 3513 |
| 20081 | CEFBS_HasSVE, // REV_PP_H = 3514 |
| 20082 | CEFBS_HasSVE, // REV_PP_S = 3515 |
| 20083 | CEFBS_HasSVE, // REV_ZZ_B = 3516 |
| 20084 | CEFBS_HasSVE, // REV_ZZ_D = 3517 |
| 20085 | CEFBS_HasSVE, // REV_ZZ_H = 3518 |
| 20086 | CEFBS_HasSVE, // REV_ZZ_S = 3519 |
| 20087 | CEFBS_HasFlagM, // RMIF = 3520 |
| 20088 | CEFBS_None, // RORVWr = 3521 |
| 20089 | CEFBS_None, // RORVXr = 3522 |
| 20090 | CEFBS_HasSVE2, // RSHRNB_ZZI_B = 3523 |
| 20091 | CEFBS_HasSVE2, // RSHRNB_ZZI_H = 3524 |
| 20092 | CEFBS_HasSVE2, // RSHRNB_ZZI_S = 3525 |
| 20093 | CEFBS_HasSVE2, // RSHRNT_ZZI_B = 3526 |
| 20094 | CEFBS_HasSVE2, // RSHRNT_ZZI_H = 3527 |
| 20095 | CEFBS_HasSVE2, // RSHRNT_ZZI_S = 3528 |
| 20096 | CEFBS_HasNEON, // RSHRNv16i8_shift = 3529 |
| 20097 | CEFBS_HasNEON, // RSHRNv2i32_shift = 3530 |
| 20098 | CEFBS_HasNEON, // RSHRNv4i16_shift = 3531 |
| 20099 | CEFBS_HasNEON, // RSHRNv4i32_shift = 3532 |
| 20100 | CEFBS_HasNEON, // RSHRNv8i16_shift = 3533 |
| 20101 | CEFBS_HasNEON, // RSHRNv8i8_shift = 3534 |
| 20102 | CEFBS_HasSVE2, // RSUBHNB_ZZZ_B = 3535 |
| 20103 | CEFBS_HasSVE2, // RSUBHNB_ZZZ_H = 3536 |
| 20104 | CEFBS_HasSVE2, // RSUBHNB_ZZZ_S = 3537 |
| 20105 | CEFBS_HasSVE2, // RSUBHNT_ZZZ_B = 3538 |
| 20106 | CEFBS_HasSVE2, // RSUBHNT_ZZZ_H = 3539 |
| 20107 | CEFBS_HasSVE2, // RSUBHNT_ZZZ_S = 3540 |
| 20108 | CEFBS_HasNEON, // RSUBHNv2i64_v2i32 = 3541 |
| 20109 | CEFBS_HasNEON, // RSUBHNv2i64_v4i32 = 3542 |
| 20110 | CEFBS_HasNEON, // RSUBHNv4i32_v4i16 = 3543 |
| 20111 | CEFBS_HasNEON, // RSUBHNv4i32_v8i16 = 3544 |
| 20112 | CEFBS_HasNEON, // RSUBHNv8i16_v16i8 = 3545 |
| 20113 | CEFBS_HasNEON, // RSUBHNv8i16_v8i8 = 3546 |
| 20114 | CEFBS_HasSVE2, // SABALB_ZZZ_D = 3547 |
| 20115 | CEFBS_HasSVE2, // SABALB_ZZZ_H = 3548 |
| 20116 | CEFBS_HasSVE2, // SABALB_ZZZ_S = 3549 |
| 20117 | CEFBS_HasSVE2, // SABALT_ZZZ_D = 3550 |
| 20118 | CEFBS_HasSVE2, // SABALT_ZZZ_H = 3551 |
| 20119 | CEFBS_HasSVE2, // SABALT_ZZZ_S = 3552 |
| 20120 | CEFBS_HasNEON, // SABALv16i8_v8i16 = 3553 |
| 20121 | CEFBS_HasNEON, // SABALv2i32_v2i64 = 3554 |
| 20122 | CEFBS_HasNEON, // SABALv4i16_v4i32 = 3555 |
| 20123 | CEFBS_HasNEON, // SABALv4i32_v2i64 = 3556 |
| 20124 | CEFBS_HasNEON, // SABALv8i16_v4i32 = 3557 |
| 20125 | CEFBS_HasNEON, // SABALv8i8_v8i16 = 3558 |
| 20126 | CEFBS_HasSVE2, // SABA_ZZZ_B = 3559 |
| 20127 | CEFBS_HasSVE2, // SABA_ZZZ_D = 3560 |
| 20128 | CEFBS_HasSVE2, // SABA_ZZZ_H = 3561 |
| 20129 | CEFBS_HasSVE2, // SABA_ZZZ_S = 3562 |
| 20130 | CEFBS_HasNEON, // SABAv16i8 = 3563 |
| 20131 | CEFBS_HasNEON, // SABAv2i32 = 3564 |
| 20132 | CEFBS_HasNEON, // SABAv4i16 = 3565 |
| 20133 | CEFBS_HasNEON, // SABAv4i32 = 3566 |
| 20134 | CEFBS_HasNEON, // SABAv8i16 = 3567 |
| 20135 | CEFBS_HasNEON, // SABAv8i8 = 3568 |
| 20136 | CEFBS_HasSVE2, // SABDLB_ZZZ_D = 3569 |
| 20137 | CEFBS_HasSVE2, // SABDLB_ZZZ_H = 3570 |
| 20138 | CEFBS_HasSVE2, // SABDLB_ZZZ_S = 3571 |
| 20139 | CEFBS_HasSVE2, // SABDLT_ZZZ_D = 3572 |
| 20140 | CEFBS_HasSVE2, // SABDLT_ZZZ_H = 3573 |
| 20141 | CEFBS_HasSVE2, // SABDLT_ZZZ_S = 3574 |
| 20142 | CEFBS_HasNEON, // SABDLv16i8_v8i16 = 3575 |
| 20143 | CEFBS_HasNEON, // SABDLv2i32_v2i64 = 3576 |
| 20144 | CEFBS_HasNEON, // SABDLv4i16_v4i32 = 3577 |
| 20145 | CEFBS_HasNEON, // SABDLv4i32_v2i64 = 3578 |
| 20146 | CEFBS_HasNEON, // SABDLv8i16_v4i32 = 3579 |
| 20147 | CEFBS_HasNEON, // SABDLv8i8_v8i16 = 3580 |
| 20148 | CEFBS_HasSVE, // SABD_ZPmZ_B = 3581 |
| 20149 | CEFBS_HasSVE, // SABD_ZPmZ_D = 3582 |
| 20150 | CEFBS_HasSVE, // SABD_ZPmZ_H = 3583 |
| 20151 | CEFBS_HasSVE, // SABD_ZPmZ_S = 3584 |
| 20152 | CEFBS_HasNEON, // SABDv16i8 = 3585 |
| 20153 | CEFBS_HasNEON, // SABDv2i32 = 3586 |
| 20154 | CEFBS_HasNEON, // SABDv4i16 = 3587 |
| 20155 | CEFBS_HasNEON, // SABDv4i32 = 3588 |
| 20156 | CEFBS_HasNEON, // SABDv8i16 = 3589 |
| 20157 | CEFBS_HasNEON, // SABDv8i8 = 3590 |
| 20158 | CEFBS_HasSVE2, // SADALP_ZPmZ_D = 3591 |
| 20159 | CEFBS_HasSVE2, // SADALP_ZPmZ_H = 3592 |
| 20160 | CEFBS_HasSVE2, // SADALP_ZPmZ_S = 3593 |
| 20161 | CEFBS_HasNEON, // SADALPv16i8_v8i16 = 3594 |
| 20162 | CEFBS_HasNEON, // SADALPv2i32_v1i64 = 3595 |
| 20163 | CEFBS_HasNEON, // SADALPv4i16_v2i32 = 3596 |
| 20164 | CEFBS_HasNEON, // SADALPv4i32_v2i64 = 3597 |
| 20165 | CEFBS_HasNEON, // SADALPv8i16_v4i32 = 3598 |
| 20166 | CEFBS_HasNEON, // SADALPv8i8_v4i16 = 3599 |
| 20167 | CEFBS_HasSVE2, // SADDLBT_ZZZ_D = 3600 |
| 20168 | CEFBS_HasSVE2, // SADDLBT_ZZZ_H = 3601 |
| 20169 | CEFBS_HasSVE2, // SADDLBT_ZZZ_S = 3602 |
| 20170 | CEFBS_HasSVE2, // SADDLB_ZZZ_D = 3603 |
| 20171 | CEFBS_HasSVE2, // SADDLB_ZZZ_H = 3604 |
| 20172 | CEFBS_HasSVE2, // SADDLB_ZZZ_S = 3605 |
| 20173 | CEFBS_HasNEON, // SADDLPv16i8_v8i16 = 3606 |
| 20174 | CEFBS_HasNEON, // SADDLPv2i32_v1i64 = 3607 |
| 20175 | CEFBS_HasNEON, // SADDLPv4i16_v2i32 = 3608 |
| 20176 | CEFBS_HasNEON, // SADDLPv4i32_v2i64 = 3609 |
| 20177 | CEFBS_HasNEON, // SADDLPv8i16_v4i32 = 3610 |
| 20178 | CEFBS_HasNEON, // SADDLPv8i8_v4i16 = 3611 |
| 20179 | CEFBS_HasSVE2, // SADDLT_ZZZ_D = 3612 |
| 20180 | CEFBS_HasSVE2, // SADDLT_ZZZ_H = 3613 |
| 20181 | CEFBS_HasSVE2, // SADDLT_ZZZ_S = 3614 |
| 20182 | CEFBS_HasNEON, // SADDLVv16i8v = 3615 |
| 20183 | CEFBS_HasNEON, // SADDLVv4i16v = 3616 |
| 20184 | CEFBS_HasNEON, // SADDLVv4i32v = 3617 |
| 20185 | CEFBS_HasNEON, // SADDLVv8i16v = 3618 |
| 20186 | CEFBS_HasNEON, // SADDLVv8i8v = 3619 |
| 20187 | CEFBS_HasNEON, // SADDLv16i8_v8i16 = 3620 |
| 20188 | CEFBS_HasNEON, // SADDLv2i32_v2i64 = 3621 |
| 20189 | CEFBS_HasNEON, // SADDLv4i16_v4i32 = 3622 |
| 20190 | CEFBS_HasNEON, // SADDLv4i32_v2i64 = 3623 |
| 20191 | CEFBS_HasNEON, // SADDLv8i16_v4i32 = 3624 |
| 20192 | CEFBS_HasNEON, // SADDLv8i8_v8i16 = 3625 |
| 20193 | CEFBS_HasSVE, // SADDV_VPZ_B = 3626 |
| 20194 | CEFBS_HasSVE, // SADDV_VPZ_H = 3627 |
| 20195 | CEFBS_HasSVE, // SADDV_VPZ_S = 3628 |
| 20196 | CEFBS_HasSVE2, // SADDWB_ZZZ_D = 3629 |
| 20197 | CEFBS_HasSVE2, // SADDWB_ZZZ_H = 3630 |
| 20198 | CEFBS_HasSVE2, // SADDWB_ZZZ_S = 3631 |
| 20199 | CEFBS_HasSVE2, // SADDWT_ZZZ_D = 3632 |
| 20200 | CEFBS_HasSVE2, // SADDWT_ZZZ_H = 3633 |
| 20201 | CEFBS_HasSVE2, // SADDWT_ZZZ_S = 3634 |
| 20202 | CEFBS_HasNEON, // SADDWv16i8_v8i16 = 3635 |
| 20203 | CEFBS_HasNEON, // SADDWv2i32_v2i64 = 3636 |
| 20204 | CEFBS_HasNEON, // SADDWv4i16_v4i32 = 3637 |
| 20205 | CEFBS_HasNEON, // SADDWv4i32_v2i64 = 3638 |
| 20206 | CEFBS_HasNEON, // SADDWv8i16_v4i32 = 3639 |
| 20207 | CEFBS_HasNEON, // SADDWv8i8_v8i16 = 3640 |
| 20208 | CEFBS_HasSB, // SB = 3641 |
| 20209 | CEFBS_HasSVE2, // SBCLB_ZZZ_D = 3642 |
| 20210 | CEFBS_HasSVE2, // SBCLB_ZZZ_S = 3643 |
| 20211 | CEFBS_HasSVE2, // SBCLT_ZZZ_D = 3644 |
| 20212 | CEFBS_HasSVE2, // SBCLT_ZZZ_S = 3645 |
| 20213 | CEFBS_None, // SBCSWr = 3646 |
| 20214 | CEFBS_None, // SBCSXr = 3647 |
| 20215 | CEFBS_None, // SBCWr = 3648 |
| 20216 | CEFBS_None, // SBCXr = 3649 |
| 20217 | CEFBS_None, // SBFMWri = 3650 |
| 20218 | CEFBS_None, // SBFMXri = 3651 |
| 20219 | CEFBS_HasFPARMv8, // SCVTFSWDri = 3652 |
| 20220 | CEFBS_HasFullFP16, // SCVTFSWHri = 3653 |
| 20221 | CEFBS_HasFPARMv8, // SCVTFSWSri = 3654 |
| 20222 | CEFBS_HasFPARMv8, // SCVTFSXDri = 3655 |
| 20223 | CEFBS_HasFullFP16, // SCVTFSXHri = 3656 |
| 20224 | CEFBS_HasFPARMv8, // SCVTFSXSri = 3657 |
| 20225 | CEFBS_HasFPARMv8, // SCVTFUWDri = 3658 |
| 20226 | CEFBS_HasFullFP16, // SCVTFUWHri = 3659 |
| 20227 | CEFBS_HasFPARMv8, // SCVTFUWSri = 3660 |
| 20228 | CEFBS_HasFPARMv8, // SCVTFUXDri = 3661 |
| 20229 | CEFBS_HasFullFP16, // SCVTFUXHri = 3662 |
| 20230 | CEFBS_HasFPARMv8, // SCVTFUXSri = 3663 |
| 20231 | CEFBS_HasSVE, // SCVTF_ZPmZ_DtoD = 3664 |
| 20232 | CEFBS_HasSVE, // SCVTF_ZPmZ_DtoH = 3665 |
| 20233 | CEFBS_HasSVE, // SCVTF_ZPmZ_DtoS = 3666 |
| 20234 | CEFBS_HasSVE, // SCVTF_ZPmZ_HtoH = 3667 |
| 20235 | CEFBS_HasSVE, // SCVTF_ZPmZ_StoD = 3668 |
| 20236 | CEFBS_HasSVE, // SCVTF_ZPmZ_StoH = 3669 |
| 20237 | CEFBS_HasSVE, // SCVTF_ZPmZ_StoS = 3670 |
| 20238 | CEFBS_HasNEON, // SCVTFd = 3671 |
| 20239 | CEFBS_HasNEON_HasFullFP16, // SCVTFh = 3672 |
| 20240 | CEFBS_HasNEON, // SCVTFs = 3673 |
| 20241 | CEFBS_HasNEON_HasFullFP16, // SCVTFv1i16 = 3674 |
| 20242 | CEFBS_HasNEON, // SCVTFv1i32 = 3675 |
| 20243 | CEFBS_HasNEON, // SCVTFv1i64 = 3676 |
| 20244 | CEFBS_HasNEON, // SCVTFv2f32 = 3677 |
| 20245 | CEFBS_HasNEON, // SCVTFv2f64 = 3678 |
| 20246 | CEFBS_HasNEON, // SCVTFv2i32_shift = 3679 |
| 20247 | CEFBS_HasNEON, // SCVTFv2i64_shift = 3680 |
| 20248 | CEFBS_HasNEON_HasFullFP16, // SCVTFv4f16 = 3681 |
| 20249 | CEFBS_HasNEON, // SCVTFv4f32 = 3682 |
| 20250 | CEFBS_HasNEON_HasFullFP16, // SCVTFv4i16_shift = 3683 |
| 20251 | CEFBS_HasNEON, // SCVTFv4i32_shift = 3684 |
| 20252 | CEFBS_HasNEON_HasFullFP16, // SCVTFv8f16 = 3685 |
| 20253 | CEFBS_HasNEON_HasFullFP16, // SCVTFv8i16_shift = 3686 |
| 20254 | CEFBS_HasSVE, // SDIVR_ZPmZ_D = 3687 |
| 20255 | CEFBS_HasSVE, // SDIVR_ZPmZ_S = 3688 |
| 20256 | CEFBS_None, // SDIVWr = 3689 |
| 20257 | CEFBS_None, // SDIVXr = 3690 |
| 20258 | CEFBS_HasSVE, // SDIV_ZPmZ_D = 3691 |
| 20259 | CEFBS_HasSVE, // SDIV_ZPmZ_S = 3692 |
| 20260 | CEFBS_HasSVE, // SDOT_ZZZI_D = 3693 |
| 20261 | CEFBS_HasSVE, // SDOT_ZZZI_S = 3694 |
| 20262 | CEFBS_HasSVE, // SDOT_ZZZ_D = 3695 |
| 20263 | CEFBS_HasSVE, // SDOT_ZZZ_S = 3696 |
| 20264 | CEFBS_HasDotProd, // SDOTlanev16i8 = 3697 |
| 20265 | CEFBS_HasDotProd, // SDOTlanev8i8 = 3698 |
| 20266 | CEFBS_HasDotProd, // SDOTv16i8 = 3699 |
| 20267 | CEFBS_HasDotProd, // SDOTv8i8 = 3700 |
| 20268 | CEFBS_HasSVE, // SEL_PPPP = 3701 |
| 20269 | CEFBS_HasSVE, // SEL_ZPZZ_B = 3702 |
| 20270 | CEFBS_HasSVE, // SEL_ZPZZ_D = 3703 |
| 20271 | CEFBS_HasSVE, // SEL_ZPZZ_H = 3704 |
| 20272 | CEFBS_HasSVE, // SEL_ZPZZ_S = 3705 |
| 20273 | CEFBS_HasFlagM, // SETF16 = 3706 |
| 20274 | CEFBS_HasFlagM, // SETF8 = 3707 |
| 20275 | CEFBS_HasSVE, // SETFFR = 3708 |
| 20276 | CEFBS_HasSHA2, // SHA1Crrr = 3709 |
| 20277 | CEFBS_HasSHA2, // SHA1Hrr = 3710 |
| 20278 | CEFBS_HasSHA2, // SHA1Mrrr = 3711 |
| 20279 | CEFBS_HasSHA2, // SHA1Prrr = 3712 |
| 20280 | CEFBS_HasSHA2, // SHA1SU0rrr = 3713 |
| 20281 | CEFBS_HasSHA2, // SHA1SU1rr = 3714 |
| 20282 | CEFBS_HasSHA2, // SHA256H2rrr = 3715 |
| 20283 | CEFBS_HasSHA2, // SHA256Hrrr = 3716 |
| 20284 | CEFBS_HasSHA2, // SHA256SU0rr = 3717 |
| 20285 | CEFBS_HasSHA2, // SHA256SU1rrr = 3718 |
| 20286 | CEFBS_HasSHA3, // SHA512H = 3719 |
| 20287 | CEFBS_HasSHA3, // SHA512H2 = 3720 |
| 20288 | CEFBS_HasSHA3, // SHA512SU0 = 3721 |
| 20289 | CEFBS_HasSHA3, // SHA512SU1 = 3722 |
| 20290 | CEFBS_HasSVE2, // SHADD_ZPmZ_B = 3723 |
| 20291 | CEFBS_HasSVE2, // SHADD_ZPmZ_D = 3724 |
| 20292 | CEFBS_HasSVE2, // SHADD_ZPmZ_H = 3725 |
| 20293 | CEFBS_HasSVE2, // SHADD_ZPmZ_S = 3726 |
| 20294 | CEFBS_HasNEON, // SHADDv16i8 = 3727 |
| 20295 | CEFBS_HasNEON, // SHADDv2i32 = 3728 |
| 20296 | CEFBS_HasNEON, // SHADDv4i16 = 3729 |
| 20297 | CEFBS_HasNEON, // SHADDv4i32 = 3730 |
| 20298 | CEFBS_HasNEON, // SHADDv8i16 = 3731 |
| 20299 | CEFBS_HasNEON, // SHADDv8i8 = 3732 |
| 20300 | CEFBS_HasNEON, // SHLLv16i8 = 3733 |
| 20301 | CEFBS_HasNEON, // SHLLv2i32 = 3734 |
| 20302 | CEFBS_HasNEON, // SHLLv4i16 = 3735 |
| 20303 | CEFBS_HasNEON, // SHLLv4i32 = 3736 |
| 20304 | CEFBS_HasNEON, // SHLLv8i16 = 3737 |
| 20305 | CEFBS_HasNEON, // SHLLv8i8 = 3738 |
| 20306 | CEFBS_HasNEON, // SHLd = 3739 |
| 20307 | CEFBS_HasNEON, // SHLv16i8_shift = 3740 |
| 20308 | CEFBS_HasNEON, // SHLv2i32_shift = 3741 |
| 20309 | CEFBS_HasNEON, // SHLv2i64_shift = 3742 |
| 20310 | CEFBS_HasNEON, // SHLv4i16_shift = 3743 |
| 20311 | CEFBS_HasNEON, // SHLv4i32_shift = 3744 |
| 20312 | CEFBS_HasNEON, // SHLv8i16_shift = 3745 |
| 20313 | CEFBS_HasNEON, // SHLv8i8_shift = 3746 |
| 20314 | CEFBS_HasSVE2, // SHRNB_ZZI_B = 3747 |
| 20315 | CEFBS_HasSVE2, // SHRNB_ZZI_H = 3748 |
| 20316 | CEFBS_HasSVE2, // SHRNB_ZZI_S = 3749 |
| 20317 | CEFBS_HasSVE2, // SHRNT_ZZI_B = 3750 |
| 20318 | CEFBS_HasSVE2, // SHRNT_ZZI_H = 3751 |
| 20319 | CEFBS_HasSVE2, // SHRNT_ZZI_S = 3752 |
| 20320 | CEFBS_HasNEON, // SHRNv16i8_shift = 3753 |
| 20321 | CEFBS_HasNEON, // SHRNv2i32_shift = 3754 |
| 20322 | CEFBS_HasNEON, // SHRNv4i16_shift = 3755 |
| 20323 | CEFBS_HasNEON, // SHRNv4i32_shift = 3756 |
| 20324 | CEFBS_HasNEON, // SHRNv8i16_shift = 3757 |
| 20325 | CEFBS_HasNEON, // SHRNv8i8_shift = 3758 |
| 20326 | CEFBS_HasSVE2, // SHSUBR_ZPmZ_B = 3759 |
| 20327 | CEFBS_HasSVE2, // SHSUBR_ZPmZ_D = 3760 |
| 20328 | CEFBS_HasSVE2, // SHSUBR_ZPmZ_H = 3761 |
| 20329 | CEFBS_HasSVE2, // SHSUBR_ZPmZ_S = 3762 |
| 20330 | CEFBS_HasSVE2, // SHSUB_ZPmZ_B = 3763 |
| 20331 | CEFBS_HasSVE2, // SHSUB_ZPmZ_D = 3764 |
| 20332 | CEFBS_HasSVE2, // SHSUB_ZPmZ_H = 3765 |
| 20333 | CEFBS_HasSVE2, // SHSUB_ZPmZ_S = 3766 |
| 20334 | CEFBS_HasNEON, // SHSUBv16i8 = 3767 |
| 20335 | CEFBS_HasNEON, // SHSUBv2i32 = 3768 |
| 20336 | CEFBS_HasNEON, // SHSUBv4i16 = 3769 |
| 20337 | CEFBS_HasNEON, // SHSUBv4i32 = 3770 |
| 20338 | CEFBS_HasNEON, // SHSUBv8i16 = 3771 |
| 20339 | CEFBS_HasNEON, // SHSUBv8i8 = 3772 |
| 20340 | CEFBS_HasSVE2, // SLI_ZZI_B = 3773 |
| 20341 | CEFBS_HasSVE2, // SLI_ZZI_D = 3774 |
| 20342 | CEFBS_HasSVE2, // SLI_ZZI_H = 3775 |
| 20343 | CEFBS_HasSVE2, // SLI_ZZI_S = 3776 |
| 20344 | CEFBS_HasNEON, // SLId = 3777 |
| 20345 | CEFBS_HasNEON, // SLIv16i8_shift = 3778 |
| 20346 | CEFBS_HasNEON, // SLIv2i32_shift = 3779 |
| 20347 | CEFBS_HasNEON, // SLIv2i64_shift = 3780 |
| 20348 | CEFBS_HasNEON, // SLIv4i16_shift = 3781 |
| 20349 | CEFBS_HasNEON, // SLIv4i32_shift = 3782 |
| 20350 | CEFBS_HasNEON, // SLIv8i16_shift = 3783 |
| 20351 | CEFBS_HasNEON, // SLIv8i8_shift = 3784 |
| 20352 | CEFBS_HasSM4, // SM3PARTW1 = 3785 |
| 20353 | CEFBS_HasSM4, // SM3PARTW2 = 3786 |
| 20354 | CEFBS_HasSM4, // SM3SS1 = 3787 |
| 20355 | CEFBS_HasSM4, // SM3TT1A = 3788 |
| 20356 | CEFBS_HasSM4, // SM3TT1B = 3789 |
| 20357 | CEFBS_HasSM4, // SM3TT2A = 3790 |
| 20358 | CEFBS_HasSM4, // SM3TT2B = 3791 |
| 20359 | CEFBS_HasSM4, // SM4E = 3792 |
| 20360 | CEFBS_HasSVE2SM4, // SM4EKEY_ZZZ_S = 3793 |
| 20361 | CEFBS_HasSM4, // SM4ENCKEY = 3794 |
| 20362 | CEFBS_HasSVE2SM4, // SM4E_ZZZ_S = 3795 |
| 20363 | CEFBS_None, // SMADDLrrr = 3796 |
| 20364 | CEFBS_HasSVE2, // SMAXP_ZPmZ_B = 3797 |
| 20365 | CEFBS_HasSVE2, // SMAXP_ZPmZ_D = 3798 |
| 20366 | CEFBS_HasSVE2, // SMAXP_ZPmZ_H = 3799 |
| 20367 | CEFBS_HasSVE2, // SMAXP_ZPmZ_S = 3800 |
| 20368 | CEFBS_HasNEON, // SMAXPv16i8 = 3801 |
| 20369 | CEFBS_HasNEON, // SMAXPv2i32 = 3802 |
| 20370 | CEFBS_HasNEON, // SMAXPv4i16 = 3803 |
| 20371 | CEFBS_HasNEON, // SMAXPv4i32 = 3804 |
| 20372 | CEFBS_HasNEON, // SMAXPv8i16 = 3805 |
| 20373 | CEFBS_HasNEON, // SMAXPv8i8 = 3806 |
| 20374 | CEFBS_HasSVE, // SMAXV_VPZ_B = 3807 |
| 20375 | CEFBS_HasSVE, // SMAXV_VPZ_D = 3808 |
| 20376 | CEFBS_HasSVE, // SMAXV_VPZ_H = 3809 |
| 20377 | CEFBS_HasSVE, // SMAXV_VPZ_S = 3810 |
| 20378 | CEFBS_HasNEON, // SMAXVv16i8v = 3811 |
| 20379 | CEFBS_HasNEON, // SMAXVv4i16v = 3812 |
| 20380 | CEFBS_HasNEON, // SMAXVv4i32v = 3813 |
| 20381 | CEFBS_HasNEON, // SMAXVv8i16v = 3814 |
| 20382 | CEFBS_HasNEON, // SMAXVv8i8v = 3815 |
| 20383 | CEFBS_HasSVE, // SMAX_ZI_B = 3816 |
| 20384 | CEFBS_HasSVE, // SMAX_ZI_D = 3817 |
| 20385 | CEFBS_HasSVE, // SMAX_ZI_H = 3818 |
| 20386 | CEFBS_HasSVE, // SMAX_ZI_S = 3819 |
| 20387 | CEFBS_HasSVE, // SMAX_ZPmZ_B = 3820 |
| 20388 | CEFBS_HasSVE, // SMAX_ZPmZ_D = 3821 |
| 20389 | CEFBS_HasSVE, // SMAX_ZPmZ_H = 3822 |
| 20390 | CEFBS_HasSVE, // SMAX_ZPmZ_S = 3823 |
| 20391 | CEFBS_HasNEON, // SMAXv16i8 = 3824 |
| 20392 | CEFBS_HasNEON, // SMAXv2i32 = 3825 |
| 20393 | CEFBS_HasNEON, // SMAXv4i16 = 3826 |
| 20394 | CEFBS_HasNEON, // SMAXv4i32 = 3827 |
| 20395 | CEFBS_HasNEON, // SMAXv8i16 = 3828 |
| 20396 | CEFBS_HasNEON, // SMAXv8i8 = 3829 |
| 20397 | CEFBS_None, // SMC = 3830 |
| 20398 | CEFBS_HasSVE2, // SMINP_ZPmZ_B = 3831 |
| 20399 | CEFBS_HasSVE2, // SMINP_ZPmZ_D = 3832 |
| 20400 | CEFBS_HasSVE2, // SMINP_ZPmZ_H = 3833 |
| 20401 | CEFBS_HasSVE2, // SMINP_ZPmZ_S = 3834 |
| 20402 | CEFBS_HasNEON, // SMINPv16i8 = 3835 |
| 20403 | CEFBS_HasNEON, // SMINPv2i32 = 3836 |
| 20404 | CEFBS_HasNEON, // SMINPv4i16 = 3837 |
| 20405 | CEFBS_HasNEON, // SMINPv4i32 = 3838 |
| 20406 | CEFBS_HasNEON, // SMINPv8i16 = 3839 |
| 20407 | CEFBS_HasNEON, // SMINPv8i8 = 3840 |
| 20408 | CEFBS_HasSVE, // SMINV_VPZ_B = 3841 |
| 20409 | CEFBS_HasSVE, // SMINV_VPZ_D = 3842 |
| 20410 | CEFBS_HasSVE, // SMINV_VPZ_H = 3843 |
| 20411 | CEFBS_HasSVE, // SMINV_VPZ_S = 3844 |
| 20412 | CEFBS_HasNEON, // SMINVv16i8v = 3845 |
| 20413 | CEFBS_HasNEON, // SMINVv4i16v = 3846 |
| 20414 | CEFBS_HasNEON, // SMINVv4i32v = 3847 |
| 20415 | CEFBS_HasNEON, // SMINVv8i16v = 3848 |
| 20416 | CEFBS_HasNEON, // SMINVv8i8v = 3849 |
| 20417 | CEFBS_HasSVE, // SMIN_ZI_B = 3850 |
| 20418 | CEFBS_HasSVE, // SMIN_ZI_D = 3851 |
| 20419 | CEFBS_HasSVE, // SMIN_ZI_H = 3852 |
| 20420 | CEFBS_HasSVE, // SMIN_ZI_S = 3853 |
| 20421 | CEFBS_HasSVE, // SMIN_ZPmZ_B = 3854 |
| 20422 | CEFBS_HasSVE, // SMIN_ZPmZ_D = 3855 |
| 20423 | CEFBS_HasSVE, // SMIN_ZPmZ_H = 3856 |
| 20424 | CEFBS_HasSVE, // SMIN_ZPmZ_S = 3857 |
| 20425 | CEFBS_HasNEON, // SMINv16i8 = 3858 |
| 20426 | CEFBS_HasNEON, // SMINv2i32 = 3859 |
| 20427 | CEFBS_HasNEON, // SMINv4i16 = 3860 |
| 20428 | CEFBS_HasNEON, // SMINv4i32 = 3861 |
| 20429 | CEFBS_HasNEON, // SMINv8i16 = 3862 |
| 20430 | CEFBS_HasNEON, // SMINv8i8 = 3863 |
| 20431 | CEFBS_HasSVE2, // SMLALB_ZZZI_D = 3864 |
| 20432 | CEFBS_HasSVE2, // SMLALB_ZZZI_S = 3865 |
| 20433 | CEFBS_HasSVE2, // SMLALB_ZZZ_D = 3866 |
| 20434 | CEFBS_HasSVE2, // SMLALB_ZZZ_H = 3867 |
| 20435 | CEFBS_HasSVE2, // SMLALB_ZZZ_S = 3868 |
| 20436 | CEFBS_HasSVE2, // SMLALT_ZZZI_D = 3869 |
| 20437 | CEFBS_HasSVE2, // SMLALT_ZZZI_S = 3870 |
| 20438 | CEFBS_HasSVE2, // SMLALT_ZZZ_D = 3871 |
| 20439 | CEFBS_HasSVE2, // SMLALT_ZZZ_H = 3872 |
| 20440 | CEFBS_HasSVE2, // SMLALT_ZZZ_S = 3873 |
| 20441 | CEFBS_HasNEON, // SMLALv16i8_v8i16 = 3874 |
| 20442 | CEFBS_HasNEON, // SMLALv2i32_indexed = 3875 |
| 20443 | CEFBS_HasNEON, // SMLALv2i32_v2i64 = 3876 |
| 20444 | CEFBS_HasNEON, // SMLALv4i16_indexed = 3877 |
| 20445 | CEFBS_HasNEON, // SMLALv4i16_v4i32 = 3878 |
| 20446 | CEFBS_HasNEON, // SMLALv4i32_indexed = 3879 |
| 20447 | CEFBS_HasNEON, // SMLALv4i32_v2i64 = 3880 |
| 20448 | CEFBS_HasNEON, // SMLALv8i16_indexed = 3881 |
| 20449 | CEFBS_HasNEON, // SMLALv8i16_v4i32 = 3882 |
| 20450 | CEFBS_HasNEON, // SMLALv8i8_v8i16 = 3883 |
| 20451 | CEFBS_HasSVE2, // SMLSLB_ZZZI_D = 3884 |
| 20452 | CEFBS_HasSVE2, // SMLSLB_ZZZI_S = 3885 |
| 20453 | CEFBS_HasSVE2, // SMLSLB_ZZZ_D = 3886 |
| 20454 | CEFBS_HasSVE2, // SMLSLB_ZZZ_H = 3887 |
| 20455 | CEFBS_HasSVE2, // SMLSLB_ZZZ_S = 3888 |
| 20456 | CEFBS_HasSVE2, // SMLSLT_ZZZI_D = 3889 |
| 20457 | CEFBS_HasSVE2, // SMLSLT_ZZZI_S = 3890 |
| 20458 | CEFBS_HasSVE2, // SMLSLT_ZZZ_D = 3891 |
| 20459 | CEFBS_HasSVE2, // SMLSLT_ZZZ_H = 3892 |
| 20460 | CEFBS_HasSVE2, // SMLSLT_ZZZ_S = 3893 |
| 20461 | CEFBS_HasNEON, // SMLSLv16i8_v8i16 = 3894 |
| 20462 | CEFBS_HasNEON, // SMLSLv2i32_indexed = 3895 |
| 20463 | CEFBS_HasNEON, // SMLSLv2i32_v2i64 = 3896 |
| 20464 | CEFBS_HasNEON, // SMLSLv4i16_indexed = 3897 |
| 20465 | CEFBS_HasNEON, // SMLSLv4i16_v4i32 = 3898 |
| 20466 | CEFBS_HasNEON, // SMLSLv4i32_indexed = 3899 |
| 20467 | CEFBS_HasNEON, // SMLSLv4i32_v2i64 = 3900 |
| 20468 | CEFBS_HasNEON, // SMLSLv8i16_indexed = 3901 |
| 20469 | CEFBS_HasNEON, // SMLSLv8i16_v4i32 = 3902 |
| 20470 | CEFBS_HasNEON, // SMLSLv8i8_v8i16 = 3903 |
| 20471 | CEFBS_HasMatMulInt8, // SMMLA = 3904 |
| 20472 | CEFBS_HasSVE_HasMatMulInt8, // SMMLA_ZZZ = 3905 |
| 20473 | CEFBS_HasNEON, // SMOVvi16to32 = 3906 |
| 20474 | CEFBS_HasNEON, // SMOVvi16to64 = 3907 |
| 20475 | CEFBS_HasNEON, // SMOVvi32to64 = 3908 |
| 20476 | CEFBS_HasNEON, // SMOVvi8to32 = 3909 |
| 20477 | CEFBS_HasNEON, // SMOVvi8to64 = 3910 |
| 20478 | CEFBS_None, // SMSUBLrrr = 3911 |
| 20479 | CEFBS_HasSVE, // SMULH_ZPmZ_B = 3912 |
| 20480 | CEFBS_HasSVE, // SMULH_ZPmZ_D = 3913 |
| 20481 | CEFBS_HasSVE, // SMULH_ZPmZ_H = 3914 |
| 20482 | CEFBS_HasSVE, // SMULH_ZPmZ_S = 3915 |
| 20483 | CEFBS_HasSVE2, // SMULH_ZZZ_B = 3916 |
| 20484 | CEFBS_HasSVE2, // SMULH_ZZZ_D = 3917 |
| 20485 | CEFBS_HasSVE2, // SMULH_ZZZ_H = 3918 |
| 20486 | CEFBS_HasSVE2, // SMULH_ZZZ_S = 3919 |
| 20487 | CEFBS_None, // SMULHrr = 3920 |
| 20488 | CEFBS_HasSVE2, // SMULLB_ZZZI_D = 3921 |
| 20489 | CEFBS_HasSVE2, // SMULLB_ZZZI_S = 3922 |
| 20490 | CEFBS_HasSVE2, // SMULLB_ZZZ_D = 3923 |
| 20491 | CEFBS_HasSVE2, // SMULLB_ZZZ_H = 3924 |
| 20492 | CEFBS_HasSVE2, // SMULLB_ZZZ_S = 3925 |
| 20493 | CEFBS_HasSVE2, // SMULLT_ZZZI_D = 3926 |
| 20494 | CEFBS_HasSVE2, // SMULLT_ZZZI_S = 3927 |
| 20495 | CEFBS_HasSVE2, // SMULLT_ZZZ_D = 3928 |
| 20496 | CEFBS_HasSVE2, // SMULLT_ZZZ_H = 3929 |
| 20497 | CEFBS_HasSVE2, // SMULLT_ZZZ_S = 3930 |
| 20498 | CEFBS_HasNEON, // SMULLv16i8_v8i16 = 3931 |
| 20499 | CEFBS_HasNEON, // SMULLv2i32_indexed = 3932 |
| 20500 | CEFBS_HasNEON, // SMULLv2i32_v2i64 = 3933 |
| 20501 | CEFBS_HasNEON, // SMULLv4i16_indexed = 3934 |
| 20502 | CEFBS_HasNEON, // SMULLv4i16_v4i32 = 3935 |
| 20503 | CEFBS_HasNEON, // SMULLv4i32_indexed = 3936 |
| 20504 | CEFBS_HasNEON, // SMULLv4i32_v2i64 = 3937 |
| 20505 | CEFBS_HasNEON, // SMULLv8i16_indexed = 3938 |
| 20506 | CEFBS_HasNEON, // SMULLv8i16_v4i32 = 3939 |
| 20507 | CEFBS_HasNEON, // SMULLv8i8_v8i16 = 3940 |
| 20508 | CEFBS_HasSVE2, // SPLICE_ZPZZ_B = 3941 |
| 20509 | CEFBS_HasSVE2, // SPLICE_ZPZZ_D = 3942 |
| 20510 | CEFBS_HasSVE2, // SPLICE_ZPZZ_H = 3943 |
| 20511 | CEFBS_HasSVE2, // SPLICE_ZPZZ_S = 3944 |
| 20512 | CEFBS_HasSVE, // SPLICE_ZPZ_B = 3945 |
| 20513 | CEFBS_HasSVE, // SPLICE_ZPZ_D = 3946 |
| 20514 | CEFBS_HasSVE, // SPLICE_ZPZ_H = 3947 |
| 20515 | CEFBS_HasSVE, // SPLICE_ZPZ_S = 3948 |
| 20516 | CEFBS_HasSVE2, // SQABS_ZPmZ_B = 3949 |
| 20517 | CEFBS_HasSVE2, // SQABS_ZPmZ_D = 3950 |
| 20518 | CEFBS_HasSVE2, // SQABS_ZPmZ_H = 3951 |
| 20519 | CEFBS_HasSVE2, // SQABS_ZPmZ_S = 3952 |
| 20520 | CEFBS_HasNEON, // SQABSv16i8 = 3953 |
| 20521 | CEFBS_HasNEON, // SQABSv1i16 = 3954 |
| 20522 | CEFBS_HasNEON, // SQABSv1i32 = 3955 |
| 20523 | CEFBS_HasNEON, // SQABSv1i64 = 3956 |
| 20524 | CEFBS_HasNEON, // SQABSv1i8 = 3957 |
| 20525 | CEFBS_HasNEON, // SQABSv2i32 = 3958 |
| 20526 | CEFBS_HasNEON, // SQABSv2i64 = 3959 |
| 20527 | CEFBS_HasNEON, // SQABSv4i16 = 3960 |
| 20528 | CEFBS_HasNEON, // SQABSv4i32 = 3961 |
| 20529 | CEFBS_HasNEON, // SQABSv8i16 = 3962 |
| 20530 | CEFBS_HasNEON, // SQABSv8i8 = 3963 |
| 20531 | CEFBS_HasSVE, // SQADD_ZI_B = 3964 |
| 20532 | CEFBS_HasSVE, // SQADD_ZI_D = 3965 |
| 20533 | CEFBS_HasSVE, // SQADD_ZI_H = 3966 |
| 20534 | CEFBS_HasSVE, // SQADD_ZI_S = 3967 |
| 20535 | CEFBS_HasSVE2, // SQADD_ZPmZ_B = 3968 |
| 20536 | CEFBS_HasSVE2, // SQADD_ZPmZ_D = 3969 |
| 20537 | CEFBS_HasSVE2, // SQADD_ZPmZ_H = 3970 |
| 20538 | CEFBS_HasSVE2, // SQADD_ZPmZ_S = 3971 |
| 20539 | CEFBS_HasSVE, // SQADD_ZZZ_B = 3972 |
| 20540 | CEFBS_HasSVE, // SQADD_ZZZ_D = 3973 |
| 20541 | CEFBS_HasSVE, // SQADD_ZZZ_H = 3974 |
| 20542 | CEFBS_HasSVE, // SQADD_ZZZ_S = 3975 |
| 20543 | CEFBS_HasNEON, // SQADDv16i8 = 3976 |
| 20544 | CEFBS_HasNEON, // SQADDv1i16 = 3977 |
| 20545 | CEFBS_HasNEON, // SQADDv1i32 = 3978 |
| 20546 | CEFBS_HasNEON, // SQADDv1i64 = 3979 |
| 20547 | CEFBS_HasNEON, // SQADDv1i8 = 3980 |
| 20548 | CEFBS_HasNEON, // SQADDv2i32 = 3981 |
| 20549 | CEFBS_HasNEON, // SQADDv2i64 = 3982 |
| 20550 | CEFBS_HasNEON, // SQADDv4i16 = 3983 |
| 20551 | CEFBS_HasNEON, // SQADDv4i32 = 3984 |
| 20552 | CEFBS_HasNEON, // SQADDv8i16 = 3985 |
| 20553 | CEFBS_HasNEON, // SQADDv8i8 = 3986 |
| 20554 | CEFBS_HasSVE2, // SQCADD_ZZI_B = 3987 |
| 20555 | CEFBS_HasSVE2, // SQCADD_ZZI_D = 3988 |
| 20556 | CEFBS_HasSVE2, // SQCADD_ZZI_H = 3989 |
| 20557 | CEFBS_HasSVE2, // SQCADD_ZZI_S = 3990 |
| 20558 | CEFBS_HasSVE, // SQDECB_XPiI = 3991 |
| 20559 | CEFBS_HasSVE, // SQDECB_XPiWdI = 3992 |
| 20560 | CEFBS_HasSVE, // SQDECD_XPiI = 3993 |
| 20561 | CEFBS_HasSVE, // SQDECD_XPiWdI = 3994 |
| 20562 | CEFBS_HasSVE, // SQDECD_ZPiI = 3995 |
| 20563 | CEFBS_HasSVE, // SQDECH_XPiI = 3996 |
| 20564 | CEFBS_HasSVE, // SQDECH_XPiWdI = 3997 |
| 20565 | CEFBS_HasSVE, // SQDECH_ZPiI = 3998 |
| 20566 | CEFBS_HasSVE, // SQDECP_XPWd_B = 3999 |
| 20567 | CEFBS_HasSVE, // SQDECP_XPWd_D = 4000 |
| 20568 | CEFBS_HasSVE, // SQDECP_XPWd_H = 4001 |
| 20569 | CEFBS_HasSVE, // SQDECP_XPWd_S = 4002 |
| 20570 | CEFBS_HasSVE, // SQDECP_XP_B = 4003 |
| 20571 | CEFBS_HasSVE, // SQDECP_XP_D = 4004 |
| 20572 | CEFBS_HasSVE, // SQDECP_XP_H = 4005 |
| 20573 | CEFBS_HasSVE, // SQDECP_XP_S = 4006 |
| 20574 | CEFBS_HasSVE, // SQDECP_ZP_D = 4007 |
| 20575 | CEFBS_HasSVE, // SQDECP_ZP_H = 4008 |
| 20576 | CEFBS_HasSVE, // SQDECP_ZP_S = 4009 |
| 20577 | CEFBS_HasSVE, // SQDECW_XPiI = 4010 |
| 20578 | CEFBS_HasSVE, // SQDECW_XPiWdI = 4011 |
| 20579 | CEFBS_HasSVE, // SQDECW_ZPiI = 4012 |
| 20580 | CEFBS_HasSVE2, // SQDMLALBT_ZZZ_D = 4013 |
| 20581 | CEFBS_HasSVE2, // SQDMLALBT_ZZZ_H = 4014 |
| 20582 | CEFBS_HasSVE2, // SQDMLALBT_ZZZ_S = 4015 |
| 20583 | CEFBS_HasSVE2, // SQDMLALB_ZZZI_D = 4016 |
| 20584 | CEFBS_HasSVE2, // SQDMLALB_ZZZI_S = 4017 |
| 20585 | CEFBS_HasSVE2, // SQDMLALB_ZZZ_D = 4018 |
| 20586 | CEFBS_HasSVE2, // SQDMLALB_ZZZ_H = 4019 |
| 20587 | CEFBS_HasSVE2, // SQDMLALB_ZZZ_S = 4020 |
| 20588 | CEFBS_HasSVE2, // SQDMLALT_ZZZI_D = 4021 |
| 20589 | CEFBS_HasSVE2, // SQDMLALT_ZZZI_S = 4022 |
| 20590 | CEFBS_HasSVE2, // SQDMLALT_ZZZ_D = 4023 |
| 20591 | CEFBS_HasSVE2, // SQDMLALT_ZZZ_H = 4024 |
| 20592 | CEFBS_HasSVE2, // SQDMLALT_ZZZ_S = 4025 |
| 20593 | CEFBS_HasNEON, // SQDMLALi16 = 4026 |
| 20594 | CEFBS_HasNEON, // SQDMLALi32 = 4027 |
| 20595 | CEFBS_HasNEON, // SQDMLALv1i32_indexed = 4028 |
| 20596 | CEFBS_HasNEON, // SQDMLALv1i64_indexed = 4029 |
| 20597 | CEFBS_HasNEON, // SQDMLALv2i32_indexed = 4030 |
| 20598 | CEFBS_HasNEON, // SQDMLALv2i32_v2i64 = 4031 |
| 20599 | CEFBS_HasNEON, // SQDMLALv4i16_indexed = 4032 |
| 20600 | CEFBS_HasNEON, // SQDMLALv4i16_v4i32 = 4033 |
| 20601 | CEFBS_HasNEON, // SQDMLALv4i32_indexed = 4034 |
| 20602 | CEFBS_HasNEON, // SQDMLALv4i32_v2i64 = 4035 |
| 20603 | CEFBS_HasNEON, // SQDMLALv8i16_indexed = 4036 |
| 20604 | CEFBS_HasNEON, // SQDMLALv8i16_v4i32 = 4037 |
| 20605 | CEFBS_HasSVE2, // SQDMLSLBT_ZZZ_D = 4038 |
| 20606 | CEFBS_HasSVE2, // SQDMLSLBT_ZZZ_H = 4039 |
| 20607 | CEFBS_HasSVE2, // SQDMLSLBT_ZZZ_S = 4040 |
| 20608 | CEFBS_HasSVE2, // SQDMLSLB_ZZZI_D = 4041 |
| 20609 | CEFBS_HasSVE2, // SQDMLSLB_ZZZI_S = 4042 |
| 20610 | CEFBS_HasSVE2, // SQDMLSLB_ZZZ_D = 4043 |
| 20611 | CEFBS_HasSVE2, // SQDMLSLB_ZZZ_H = 4044 |
| 20612 | CEFBS_HasSVE2, // SQDMLSLB_ZZZ_S = 4045 |
| 20613 | CEFBS_HasSVE2, // SQDMLSLT_ZZZI_D = 4046 |
| 20614 | CEFBS_HasSVE2, // SQDMLSLT_ZZZI_S = 4047 |
| 20615 | CEFBS_HasSVE2, // SQDMLSLT_ZZZ_D = 4048 |
| 20616 | CEFBS_HasSVE2, // SQDMLSLT_ZZZ_H = 4049 |
| 20617 | CEFBS_HasSVE2, // SQDMLSLT_ZZZ_S = 4050 |
| 20618 | CEFBS_HasNEON, // SQDMLSLi16 = 4051 |
| 20619 | CEFBS_HasNEON, // SQDMLSLi32 = 4052 |
| 20620 | CEFBS_HasNEON, // SQDMLSLv1i32_indexed = 4053 |
| 20621 | CEFBS_HasNEON, // SQDMLSLv1i64_indexed = 4054 |
| 20622 | CEFBS_HasNEON, // SQDMLSLv2i32_indexed = 4055 |
| 20623 | CEFBS_HasNEON, // SQDMLSLv2i32_v2i64 = 4056 |
| 20624 | CEFBS_HasNEON, // SQDMLSLv4i16_indexed = 4057 |
| 20625 | CEFBS_HasNEON, // SQDMLSLv4i16_v4i32 = 4058 |
| 20626 | CEFBS_HasNEON, // SQDMLSLv4i32_indexed = 4059 |
| 20627 | CEFBS_HasNEON, // SQDMLSLv4i32_v2i64 = 4060 |
| 20628 | CEFBS_HasNEON, // SQDMLSLv8i16_indexed = 4061 |
| 20629 | CEFBS_HasNEON, // SQDMLSLv8i16_v4i32 = 4062 |
| 20630 | CEFBS_HasSVE2, // SQDMULH_ZZZI_D = 4063 |
| 20631 | CEFBS_HasSVE2, // SQDMULH_ZZZI_H = 4064 |
| 20632 | CEFBS_HasSVE2, // SQDMULH_ZZZI_S = 4065 |
| 20633 | CEFBS_HasSVE2, // SQDMULH_ZZZ_B = 4066 |
| 20634 | CEFBS_HasSVE2, // SQDMULH_ZZZ_D = 4067 |
| 20635 | CEFBS_HasSVE2, // SQDMULH_ZZZ_H = 4068 |
| 20636 | CEFBS_HasSVE2, // SQDMULH_ZZZ_S = 4069 |
| 20637 | CEFBS_HasNEON, // SQDMULHv1i16 = 4070 |
| 20638 | CEFBS_HasNEON, // SQDMULHv1i16_indexed = 4071 |
| 20639 | CEFBS_HasNEON, // SQDMULHv1i32 = 4072 |
| 20640 | CEFBS_HasNEON, // SQDMULHv1i32_indexed = 4073 |
| 20641 | CEFBS_HasNEON, // SQDMULHv2i32 = 4074 |
| 20642 | CEFBS_HasNEON, // SQDMULHv2i32_indexed = 4075 |
| 20643 | CEFBS_HasNEON, // SQDMULHv4i16 = 4076 |
| 20644 | CEFBS_HasNEON, // SQDMULHv4i16_indexed = 4077 |
| 20645 | CEFBS_HasNEON, // SQDMULHv4i32 = 4078 |
| 20646 | CEFBS_HasNEON, // SQDMULHv4i32_indexed = 4079 |
| 20647 | CEFBS_HasNEON, // SQDMULHv8i16 = 4080 |
| 20648 | CEFBS_HasNEON, // SQDMULHv8i16_indexed = 4081 |
| 20649 | CEFBS_HasSVE2, // SQDMULLB_ZZZI_D = 4082 |
| 20650 | CEFBS_HasSVE2, // SQDMULLB_ZZZI_S = 4083 |
| 20651 | CEFBS_HasSVE2, // SQDMULLB_ZZZ_D = 4084 |
| 20652 | CEFBS_HasSVE2, // SQDMULLB_ZZZ_H = 4085 |
| 20653 | CEFBS_HasSVE2, // SQDMULLB_ZZZ_S = 4086 |
| 20654 | CEFBS_HasSVE2, // SQDMULLT_ZZZI_D = 4087 |
| 20655 | CEFBS_HasSVE2, // SQDMULLT_ZZZI_S = 4088 |
| 20656 | CEFBS_HasSVE2, // SQDMULLT_ZZZ_D = 4089 |
| 20657 | CEFBS_HasSVE2, // SQDMULLT_ZZZ_H = 4090 |
| 20658 | CEFBS_HasSVE2, // SQDMULLT_ZZZ_S = 4091 |
| 20659 | CEFBS_HasNEON, // SQDMULLi16 = 4092 |
| 20660 | CEFBS_HasNEON, // SQDMULLi32 = 4093 |
| 20661 | CEFBS_HasNEON, // SQDMULLv1i32_indexed = 4094 |
| 20662 | CEFBS_HasNEON, // SQDMULLv1i64_indexed = 4095 |
| 20663 | CEFBS_HasNEON, // SQDMULLv2i32_indexed = 4096 |
| 20664 | CEFBS_HasNEON, // SQDMULLv2i32_v2i64 = 4097 |
| 20665 | CEFBS_HasNEON, // SQDMULLv4i16_indexed = 4098 |
| 20666 | CEFBS_HasNEON, // SQDMULLv4i16_v4i32 = 4099 |
| 20667 | CEFBS_HasNEON, // SQDMULLv4i32_indexed = 4100 |
| 20668 | CEFBS_HasNEON, // SQDMULLv4i32_v2i64 = 4101 |
| 20669 | CEFBS_HasNEON, // SQDMULLv8i16_indexed = 4102 |
| 20670 | CEFBS_HasNEON, // SQDMULLv8i16_v4i32 = 4103 |
| 20671 | CEFBS_HasSVE, // SQINCB_XPiI = 4104 |
| 20672 | CEFBS_HasSVE, // SQINCB_XPiWdI = 4105 |
| 20673 | CEFBS_HasSVE, // SQINCD_XPiI = 4106 |
| 20674 | CEFBS_HasSVE, // SQINCD_XPiWdI = 4107 |
| 20675 | CEFBS_HasSVE, // SQINCD_ZPiI = 4108 |
| 20676 | CEFBS_HasSVE, // SQINCH_XPiI = 4109 |
| 20677 | CEFBS_HasSVE, // SQINCH_XPiWdI = 4110 |
| 20678 | CEFBS_HasSVE, // SQINCH_ZPiI = 4111 |
| 20679 | CEFBS_HasSVE, // SQINCP_XPWd_B = 4112 |
| 20680 | CEFBS_HasSVE, // SQINCP_XPWd_D = 4113 |
| 20681 | CEFBS_HasSVE, // SQINCP_XPWd_H = 4114 |
| 20682 | CEFBS_HasSVE, // SQINCP_XPWd_S = 4115 |
| 20683 | CEFBS_HasSVE, // SQINCP_XP_B = 4116 |
| 20684 | CEFBS_HasSVE, // SQINCP_XP_D = 4117 |
| 20685 | CEFBS_HasSVE, // SQINCP_XP_H = 4118 |
| 20686 | CEFBS_HasSVE, // SQINCP_XP_S = 4119 |
| 20687 | CEFBS_HasSVE, // SQINCP_ZP_D = 4120 |
| 20688 | CEFBS_HasSVE, // SQINCP_ZP_H = 4121 |
| 20689 | CEFBS_HasSVE, // SQINCP_ZP_S = 4122 |
| 20690 | CEFBS_HasSVE, // SQINCW_XPiI = 4123 |
| 20691 | CEFBS_HasSVE, // SQINCW_XPiWdI = 4124 |
| 20692 | CEFBS_HasSVE, // SQINCW_ZPiI = 4125 |
| 20693 | CEFBS_HasSVE2, // SQNEG_ZPmZ_B = 4126 |
| 20694 | CEFBS_HasSVE2, // SQNEG_ZPmZ_D = 4127 |
| 20695 | CEFBS_HasSVE2, // SQNEG_ZPmZ_H = 4128 |
| 20696 | CEFBS_HasSVE2, // SQNEG_ZPmZ_S = 4129 |
| 20697 | CEFBS_HasNEON, // SQNEGv16i8 = 4130 |
| 20698 | CEFBS_HasNEON, // SQNEGv1i16 = 4131 |
| 20699 | CEFBS_HasNEON, // SQNEGv1i32 = 4132 |
| 20700 | CEFBS_HasNEON, // SQNEGv1i64 = 4133 |
| 20701 | CEFBS_HasNEON, // SQNEGv1i8 = 4134 |
| 20702 | CEFBS_HasNEON, // SQNEGv2i32 = 4135 |
| 20703 | CEFBS_HasNEON, // SQNEGv2i64 = 4136 |
| 20704 | CEFBS_HasNEON, // SQNEGv4i16 = 4137 |
| 20705 | CEFBS_HasNEON, // SQNEGv4i32 = 4138 |
| 20706 | CEFBS_HasNEON, // SQNEGv8i16 = 4139 |
| 20707 | CEFBS_HasNEON, // SQNEGv8i8 = 4140 |
| 20708 | CEFBS_HasSVE2, // SQRDCMLAH_ZZZI_H = 4141 |
| 20709 | CEFBS_HasSVE2, // SQRDCMLAH_ZZZI_S = 4142 |
| 20710 | CEFBS_HasSVE2, // SQRDCMLAH_ZZZ_B = 4143 |
| 20711 | CEFBS_HasSVE2, // SQRDCMLAH_ZZZ_D = 4144 |
| 20712 | CEFBS_HasSVE2, // SQRDCMLAH_ZZZ_H = 4145 |
| 20713 | CEFBS_HasSVE2, // SQRDCMLAH_ZZZ_S = 4146 |
| 20714 | CEFBS_HasSVE2, // SQRDMLAH_ZZZI_D = 4147 |
| 20715 | CEFBS_HasSVE2, // SQRDMLAH_ZZZI_H = 4148 |
| 20716 | CEFBS_HasSVE2, // SQRDMLAH_ZZZI_S = 4149 |
| 20717 | CEFBS_HasSVE2, // SQRDMLAH_ZZZ_B = 4150 |
| 20718 | CEFBS_HasSVE2, // SQRDMLAH_ZZZ_D = 4151 |
| 20719 | CEFBS_HasSVE2, // SQRDMLAH_ZZZ_H = 4152 |
| 20720 | CEFBS_HasSVE2, // SQRDMLAH_ZZZ_S = 4153 |
| 20721 | CEFBS_HasNEON_HasRDM, // SQRDMLAHi16_indexed = 4154 |
| 20722 | CEFBS_HasNEON_HasRDM, // SQRDMLAHi32_indexed = 4155 |
| 20723 | CEFBS_HasRDM, // SQRDMLAHv1i16 = 4156 |
| 20724 | CEFBS_HasRDM, // SQRDMLAHv1i32 = 4157 |
| 20725 | CEFBS_HasNEON_HasRDM, // SQRDMLAHv2i32 = 4158 |
| 20726 | CEFBS_HasNEON_HasRDM, // SQRDMLAHv2i32_indexed = 4159 |
| 20727 | CEFBS_HasNEON_HasRDM, // SQRDMLAHv4i16 = 4160 |
| 20728 | CEFBS_HasNEON_HasRDM, // SQRDMLAHv4i16_indexed = 4161 |
| 20729 | CEFBS_HasNEON_HasRDM, // SQRDMLAHv4i32 = 4162 |
| 20730 | CEFBS_HasNEON_HasRDM, // SQRDMLAHv4i32_indexed = 4163 |
| 20731 | CEFBS_HasNEON_HasRDM, // SQRDMLAHv8i16 = 4164 |
| 20732 | CEFBS_HasNEON_HasRDM, // SQRDMLAHv8i16_indexed = 4165 |
| 20733 | CEFBS_HasSVE2, // SQRDMLSH_ZZZI_D = 4166 |
| 20734 | CEFBS_HasSVE2, // SQRDMLSH_ZZZI_H = 4167 |
| 20735 | CEFBS_HasSVE2, // SQRDMLSH_ZZZI_S = 4168 |
| 20736 | CEFBS_HasSVE2, // SQRDMLSH_ZZZ_B = 4169 |
| 20737 | CEFBS_HasSVE2, // SQRDMLSH_ZZZ_D = 4170 |
| 20738 | CEFBS_HasSVE2, // SQRDMLSH_ZZZ_H = 4171 |
| 20739 | CEFBS_HasSVE2, // SQRDMLSH_ZZZ_S = 4172 |
| 20740 | CEFBS_HasNEON_HasRDM, // SQRDMLSHi16_indexed = 4173 |
| 20741 | CEFBS_HasNEON_HasRDM, // SQRDMLSHi32_indexed = 4174 |
| 20742 | CEFBS_HasRDM, // SQRDMLSHv1i16 = 4175 |
| 20743 | CEFBS_HasRDM, // SQRDMLSHv1i32 = 4176 |
| 20744 | CEFBS_HasNEON_HasRDM, // SQRDMLSHv2i32 = 4177 |
| 20745 | CEFBS_HasNEON_HasRDM, // SQRDMLSHv2i32_indexed = 4178 |
| 20746 | CEFBS_HasNEON_HasRDM, // SQRDMLSHv4i16 = 4179 |
| 20747 | CEFBS_HasNEON_HasRDM, // SQRDMLSHv4i16_indexed = 4180 |
| 20748 | CEFBS_HasNEON_HasRDM, // SQRDMLSHv4i32 = 4181 |
| 20749 | CEFBS_HasNEON_HasRDM, // SQRDMLSHv4i32_indexed = 4182 |
| 20750 | CEFBS_HasNEON_HasRDM, // SQRDMLSHv8i16 = 4183 |
| 20751 | CEFBS_HasNEON_HasRDM, // SQRDMLSHv8i16_indexed = 4184 |
| 20752 | CEFBS_HasSVE2, // SQRDMULH_ZZZI_D = 4185 |
| 20753 | CEFBS_HasSVE2, // SQRDMULH_ZZZI_H = 4186 |
| 20754 | CEFBS_HasSVE2, // SQRDMULH_ZZZI_S = 4187 |
| 20755 | CEFBS_HasSVE2, // SQRDMULH_ZZZ_B = 4188 |
| 20756 | CEFBS_HasSVE2, // SQRDMULH_ZZZ_D = 4189 |
| 20757 | CEFBS_HasSVE2, // SQRDMULH_ZZZ_H = 4190 |
| 20758 | CEFBS_HasSVE2, // SQRDMULH_ZZZ_S = 4191 |
| 20759 | CEFBS_HasNEON, // SQRDMULHv1i16 = 4192 |
| 20760 | CEFBS_HasNEON, // SQRDMULHv1i16_indexed = 4193 |
| 20761 | CEFBS_HasNEON, // SQRDMULHv1i32 = 4194 |
| 20762 | CEFBS_HasNEON, // SQRDMULHv1i32_indexed = 4195 |
| 20763 | CEFBS_HasNEON, // SQRDMULHv2i32 = 4196 |
| 20764 | CEFBS_HasNEON, // SQRDMULHv2i32_indexed = 4197 |
| 20765 | CEFBS_HasNEON, // SQRDMULHv4i16 = 4198 |
| 20766 | CEFBS_HasNEON, // SQRDMULHv4i16_indexed = 4199 |
| 20767 | CEFBS_HasNEON, // SQRDMULHv4i32 = 4200 |
| 20768 | CEFBS_HasNEON, // SQRDMULHv4i32_indexed = 4201 |
| 20769 | CEFBS_HasNEON, // SQRDMULHv8i16 = 4202 |
| 20770 | CEFBS_HasNEON, // SQRDMULHv8i16_indexed = 4203 |
| 20771 | CEFBS_HasSVE2, // SQRSHLR_ZPmZ_B = 4204 |
| 20772 | CEFBS_HasSVE2, // SQRSHLR_ZPmZ_D = 4205 |
| 20773 | CEFBS_HasSVE2, // SQRSHLR_ZPmZ_H = 4206 |
| 20774 | CEFBS_HasSVE2, // SQRSHLR_ZPmZ_S = 4207 |
| 20775 | CEFBS_HasSVE2, // SQRSHL_ZPmZ_B = 4208 |
| 20776 | CEFBS_HasSVE2, // SQRSHL_ZPmZ_D = 4209 |
| 20777 | CEFBS_HasSVE2, // SQRSHL_ZPmZ_H = 4210 |
| 20778 | CEFBS_HasSVE2, // SQRSHL_ZPmZ_S = 4211 |
| 20779 | CEFBS_HasNEON, // SQRSHLv16i8 = 4212 |
| 20780 | CEFBS_HasNEON, // SQRSHLv1i16 = 4213 |
| 20781 | CEFBS_HasNEON, // SQRSHLv1i32 = 4214 |
| 20782 | CEFBS_HasNEON, // SQRSHLv1i64 = 4215 |
| 20783 | CEFBS_HasNEON, // SQRSHLv1i8 = 4216 |
| 20784 | CEFBS_HasNEON, // SQRSHLv2i32 = 4217 |
| 20785 | CEFBS_HasNEON, // SQRSHLv2i64 = 4218 |
| 20786 | CEFBS_HasNEON, // SQRSHLv4i16 = 4219 |
| 20787 | CEFBS_HasNEON, // SQRSHLv4i32 = 4220 |
| 20788 | CEFBS_HasNEON, // SQRSHLv8i16 = 4221 |
| 20789 | CEFBS_HasNEON, // SQRSHLv8i8 = 4222 |
| 20790 | CEFBS_HasSVE2, // SQRSHRNB_ZZI_B = 4223 |
| 20791 | CEFBS_HasSVE2, // SQRSHRNB_ZZI_H = 4224 |
| 20792 | CEFBS_HasSVE2, // SQRSHRNB_ZZI_S = 4225 |
| 20793 | CEFBS_HasSVE2, // SQRSHRNT_ZZI_B = 4226 |
| 20794 | CEFBS_HasSVE2, // SQRSHRNT_ZZI_H = 4227 |
| 20795 | CEFBS_HasSVE2, // SQRSHRNT_ZZI_S = 4228 |
| 20796 | CEFBS_HasNEON, // SQRSHRNb = 4229 |
| 20797 | CEFBS_HasNEON, // SQRSHRNh = 4230 |
| 20798 | CEFBS_HasNEON, // SQRSHRNs = 4231 |
| 20799 | CEFBS_HasNEON, // SQRSHRNv16i8_shift = 4232 |
| 20800 | CEFBS_HasNEON, // SQRSHRNv2i32_shift = 4233 |
| 20801 | CEFBS_HasNEON, // SQRSHRNv4i16_shift = 4234 |
| 20802 | CEFBS_HasNEON, // SQRSHRNv4i32_shift = 4235 |
| 20803 | CEFBS_HasNEON, // SQRSHRNv8i16_shift = 4236 |
| 20804 | CEFBS_HasNEON, // SQRSHRNv8i8_shift = 4237 |
| 20805 | CEFBS_HasSVE2, // SQRSHRUNB_ZZI_B = 4238 |
| 20806 | CEFBS_HasSVE2, // SQRSHRUNB_ZZI_H = 4239 |
| 20807 | CEFBS_HasSVE2, // SQRSHRUNB_ZZI_S = 4240 |
| 20808 | CEFBS_HasSVE2, // SQRSHRUNT_ZZI_B = 4241 |
| 20809 | CEFBS_HasSVE2, // SQRSHRUNT_ZZI_H = 4242 |
| 20810 | CEFBS_HasSVE2, // SQRSHRUNT_ZZI_S = 4243 |
| 20811 | CEFBS_HasNEON, // SQRSHRUNb = 4244 |
| 20812 | CEFBS_HasNEON, // SQRSHRUNh = 4245 |
| 20813 | CEFBS_HasNEON, // SQRSHRUNs = 4246 |
| 20814 | CEFBS_HasNEON, // SQRSHRUNv16i8_shift = 4247 |
| 20815 | CEFBS_HasNEON, // SQRSHRUNv2i32_shift = 4248 |
| 20816 | CEFBS_HasNEON, // SQRSHRUNv4i16_shift = 4249 |
| 20817 | CEFBS_HasNEON, // SQRSHRUNv4i32_shift = 4250 |
| 20818 | CEFBS_HasNEON, // SQRSHRUNv8i16_shift = 4251 |
| 20819 | CEFBS_HasNEON, // SQRSHRUNv8i8_shift = 4252 |
| 20820 | CEFBS_HasSVE2, // SQSHLR_ZPmZ_B = 4253 |
| 20821 | CEFBS_HasSVE2, // SQSHLR_ZPmZ_D = 4254 |
| 20822 | CEFBS_HasSVE2, // SQSHLR_ZPmZ_H = 4255 |
| 20823 | CEFBS_HasSVE2, // SQSHLR_ZPmZ_S = 4256 |
| 20824 | CEFBS_HasSVE2, // SQSHLU_ZPmI_B = 4257 |
| 20825 | CEFBS_HasSVE2, // SQSHLU_ZPmI_D = 4258 |
| 20826 | CEFBS_HasSVE2, // SQSHLU_ZPmI_H = 4259 |
| 20827 | CEFBS_HasSVE2, // SQSHLU_ZPmI_S = 4260 |
| 20828 | CEFBS_HasNEON, // SQSHLUb = 4261 |
| 20829 | CEFBS_HasNEON, // SQSHLUd = 4262 |
| 20830 | CEFBS_HasNEON, // SQSHLUh = 4263 |
| 20831 | CEFBS_HasNEON, // SQSHLUs = 4264 |
| 20832 | CEFBS_HasNEON, // SQSHLUv16i8_shift = 4265 |
| 20833 | CEFBS_HasNEON, // SQSHLUv2i32_shift = 4266 |
| 20834 | CEFBS_HasNEON, // SQSHLUv2i64_shift = 4267 |
| 20835 | CEFBS_HasNEON, // SQSHLUv4i16_shift = 4268 |
| 20836 | CEFBS_HasNEON, // SQSHLUv4i32_shift = 4269 |
| 20837 | CEFBS_HasNEON, // SQSHLUv8i16_shift = 4270 |
| 20838 | CEFBS_HasNEON, // SQSHLUv8i8_shift = 4271 |
| 20839 | CEFBS_HasSVE2, // SQSHL_ZPmI_B = 4272 |
| 20840 | CEFBS_HasSVE2, // SQSHL_ZPmI_D = 4273 |
| 20841 | CEFBS_HasSVE2, // SQSHL_ZPmI_H = 4274 |
| 20842 | CEFBS_HasSVE2, // SQSHL_ZPmI_S = 4275 |
| 20843 | CEFBS_HasSVE2, // SQSHL_ZPmZ_B = 4276 |
| 20844 | CEFBS_HasSVE2, // SQSHL_ZPmZ_D = 4277 |
| 20845 | CEFBS_HasSVE2, // SQSHL_ZPmZ_H = 4278 |
| 20846 | CEFBS_HasSVE2, // SQSHL_ZPmZ_S = 4279 |
| 20847 | CEFBS_HasNEON, // SQSHLb = 4280 |
| 20848 | CEFBS_HasNEON, // SQSHLd = 4281 |
| 20849 | CEFBS_HasNEON, // SQSHLh = 4282 |
| 20850 | CEFBS_HasNEON, // SQSHLs = 4283 |
| 20851 | CEFBS_HasNEON, // SQSHLv16i8 = 4284 |
| 20852 | CEFBS_HasNEON, // SQSHLv16i8_shift = 4285 |
| 20853 | CEFBS_HasNEON, // SQSHLv1i16 = 4286 |
| 20854 | CEFBS_HasNEON, // SQSHLv1i32 = 4287 |
| 20855 | CEFBS_HasNEON, // SQSHLv1i64 = 4288 |
| 20856 | CEFBS_HasNEON, // SQSHLv1i8 = 4289 |
| 20857 | CEFBS_HasNEON, // SQSHLv2i32 = 4290 |
| 20858 | CEFBS_HasNEON, // SQSHLv2i32_shift = 4291 |
| 20859 | CEFBS_HasNEON, // SQSHLv2i64 = 4292 |
| 20860 | CEFBS_HasNEON, // SQSHLv2i64_shift = 4293 |
| 20861 | CEFBS_HasNEON, // SQSHLv4i16 = 4294 |
| 20862 | CEFBS_HasNEON, // SQSHLv4i16_shift = 4295 |
| 20863 | CEFBS_HasNEON, // SQSHLv4i32 = 4296 |
| 20864 | CEFBS_HasNEON, // SQSHLv4i32_shift = 4297 |
| 20865 | CEFBS_HasNEON, // SQSHLv8i16 = 4298 |
| 20866 | CEFBS_HasNEON, // SQSHLv8i16_shift = 4299 |
| 20867 | CEFBS_HasNEON, // SQSHLv8i8 = 4300 |
| 20868 | CEFBS_HasNEON, // SQSHLv8i8_shift = 4301 |
| 20869 | CEFBS_HasSVE2, // SQSHRNB_ZZI_B = 4302 |
| 20870 | CEFBS_HasSVE2, // SQSHRNB_ZZI_H = 4303 |
| 20871 | CEFBS_HasSVE2, // SQSHRNB_ZZI_S = 4304 |
| 20872 | CEFBS_HasSVE2, // SQSHRNT_ZZI_B = 4305 |
| 20873 | CEFBS_HasSVE2, // SQSHRNT_ZZI_H = 4306 |
| 20874 | CEFBS_HasSVE2, // SQSHRNT_ZZI_S = 4307 |
| 20875 | CEFBS_HasNEON, // SQSHRNb = 4308 |
| 20876 | CEFBS_HasNEON, // SQSHRNh = 4309 |
| 20877 | CEFBS_HasNEON, // SQSHRNs = 4310 |
| 20878 | CEFBS_HasNEON, // SQSHRNv16i8_shift = 4311 |
| 20879 | CEFBS_HasNEON, // SQSHRNv2i32_shift = 4312 |
| 20880 | CEFBS_HasNEON, // SQSHRNv4i16_shift = 4313 |
| 20881 | CEFBS_HasNEON, // SQSHRNv4i32_shift = 4314 |
| 20882 | CEFBS_HasNEON, // SQSHRNv8i16_shift = 4315 |
| 20883 | CEFBS_HasNEON, // SQSHRNv8i8_shift = 4316 |
| 20884 | CEFBS_HasSVE2, // SQSHRUNB_ZZI_B = 4317 |
| 20885 | CEFBS_HasSVE2, // SQSHRUNB_ZZI_H = 4318 |
| 20886 | CEFBS_HasSVE2, // SQSHRUNB_ZZI_S = 4319 |
| 20887 | CEFBS_HasSVE2, // SQSHRUNT_ZZI_B = 4320 |
| 20888 | CEFBS_HasSVE2, // SQSHRUNT_ZZI_H = 4321 |
| 20889 | CEFBS_HasSVE2, // SQSHRUNT_ZZI_S = 4322 |
| 20890 | CEFBS_HasNEON, // SQSHRUNb = 4323 |
| 20891 | CEFBS_HasNEON, // SQSHRUNh = 4324 |
| 20892 | CEFBS_HasNEON, // SQSHRUNs = 4325 |
| 20893 | CEFBS_HasNEON, // SQSHRUNv16i8_shift = 4326 |
| 20894 | CEFBS_HasNEON, // SQSHRUNv2i32_shift = 4327 |
| 20895 | CEFBS_HasNEON, // SQSHRUNv4i16_shift = 4328 |
| 20896 | CEFBS_HasNEON, // SQSHRUNv4i32_shift = 4329 |
| 20897 | CEFBS_HasNEON, // SQSHRUNv8i16_shift = 4330 |
| 20898 | CEFBS_HasNEON, // SQSHRUNv8i8_shift = 4331 |
| 20899 | CEFBS_HasSVE2, // SQSUBR_ZPmZ_B = 4332 |
| 20900 | CEFBS_HasSVE2, // SQSUBR_ZPmZ_D = 4333 |
| 20901 | CEFBS_HasSVE2, // SQSUBR_ZPmZ_H = 4334 |
| 20902 | CEFBS_HasSVE2, // SQSUBR_ZPmZ_S = 4335 |
| 20903 | CEFBS_HasSVE, // SQSUB_ZI_B = 4336 |
| 20904 | CEFBS_HasSVE, // SQSUB_ZI_D = 4337 |
| 20905 | CEFBS_HasSVE, // SQSUB_ZI_H = 4338 |
| 20906 | CEFBS_HasSVE, // SQSUB_ZI_S = 4339 |
| 20907 | CEFBS_HasSVE2, // SQSUB_ZPmZ_B = 4340 |
| 20908 | CEFBS_HasSVE2, // SQSUB_ZPmZ_D = 4341 |
| 20909 | CEFBS_HasSVE2, // SQSUB_ZPmZ_H = 4342 |
| 20910 | CEFBS_HasSVE2, // SQSUB_ZPmZ_S = 4343 |
| 20911 | CEFBS_HasSVE, // SQSUB_ZZZ_B = 4344 |
| 20912 | CEFBS_HasSVE, // SQSUB_ZZZ_D = 4345 |
| 20913 | CEFBS_HasSVE, // SQSUB_ZZZ_H = 4346 |
| 20914 | CEFBS_HasSVE, // SQSUB_ZZZ_S = 4347 |
| 20915 | CEFBS_HasNEON, // SQSUBv16i8 = 4348 |
| 20916 | CEFBS_HasNEON, // SQSUBv1i16 = 4349 |
| 20917 | CEFBS_HasNEON, // SQSUBv1i32 = 4350 |
| 20918 | CEFBS_HasNEON, // SQSUBv1i64 = 4351 |
| 20919 | CEFBS_HasNEON, // SQSUBv1i8 = 4352 |
| 20920 | CEFBS_HasNEON, // SQSUBv2i32 = 4353 |
| 20921 | CEFBS_HasNEON, // SQSUBv2i64 = 4354 |
| 20922 | CEFBS_HasNEON, // SQSUBv4i16 = 4355 |
| 20923 | CEFBS_HasNEON, // SQSUBv4i32 = 4356 |
| 20924 | CEFBS_HasNEON, // SQSUBv8i16 = 4357 |
| 20925 | CEFBS_HasNEON, // SQSUBv8i8 = 4358 |
| 20926 | CEFBS_HasSVE2, // SQXTNB_ZZ_B = 4359 |
| 20927 | CEFBS_HasSVE2, // SQXTNB_ZZ_H = 4360 |
| 20928 | CEFBS_HasSVE2, // SQXTNB_ZZ_S = 4361 |
| 20929 | CEFBS_HasSVE2, // SQXTNT_ZZ_B = 4362 |
| 20930 | CEFBS_HasSVE2, // SQXTNT_ZZ_H = 4363 |
| 20931 | CEFBS_HasSVE2, // SQXTNT_ZZ_S = 4364 |
| 20932 | CEFBS_HasNEON, // SQXTNv16i8 = 4365 |
| 20933 | CEFBS_HasNEON, // SQXTNv1i16 = 4366 |
| 20934 | CEFBS_HasNEON, // SQXTNv1i32 = 4367 |
| 20935 | CEFBS_HasNEON, // SQXTNv1i8 = 4368 |
| 20936 | CEFBS_HasNEON, // SQXTNv2i32 = 4369 |
| 20937 | CEFBS_HasNEON, // SQXTNv4i16 = 4370 |
| 20938 | CEFBS_HasNEON, // SQXTNv4i32 = 4371 |
| 20939 | CEFBS_HasNEON, // SQXTNv8i16 = 4372 |
| 20940 | CEFBS_HasNEON, // SQXTNv8i8 = 4373 |
| 20941 | CEFBS_HasSVE2, // SQXTUNB_ZZ_B = 4374 |
| 20942 | CEFBS_HasSVE2, // SQXTUNB_ZZ_H = 4375 |
| 20943 | CEFBS_HasSVE2, // SQXTUNB_ZZ_S = 4376 |
| 20944 | CEFBS_HasSVE2, // SQXTUNT_ZZ_B = 4377 |
| 20945 | CEFBS_HasSVE2, // SQXTUNT_ZZ_H = 4378 |
| 20946 | CEFBS_HasSVE2, // SQXTUNT_ZZ_S = 4379 |
| 20947 | CEFBS_HasNEON, // SQXTUNv16i8 = 4380 |
| 20948 | CEFBS_HasNEON, // SQXTUNv1i16 = 4381 |
| 20949 | CEFBS_HasNEON, // SQXTUNv1i32 = 4382 |
| 20950 | CEFBS_HasNEON, // SQXTUNv1i8 = 4383 |
| 20951 | CEFBS_HasNEON, // SQXTUNv2i32 = 4384 |
| 20952 | CEFBS_HasNEON, // SQXTUNv4i16 = 4385 |
| 20953 | CEFBS_HasNEON, // SQXTUNv4i32 = 4386 |
| 20954 | CEFBS_HasNEON, // SQXTUNv8i16 = 4387 |
| 20955 | CEFBS_HasNEON, // SQXTUNv8i8 = 4388 |
| 20956 | CEFBS_HasSVE2, // SRHADD_ZPmZ_B = 4389 |
| 20957 | CEFBS_HasSVE2, // SRHADD_ZPmZ_D = 4390 |
| 20958 | CEFBS_HasSVE2, // SRHADD_ZPmZ_H = 4391 |
| 20959 | CEFBS_HasSVE2, // SRHADD_ZPmZ_S = 4392 |
| 20960 | CEFBS_HasNEON, // SRHADDv16i8 = 4393 |
| 20961 | CEFBS_HasNEON, // SRHADDv2i32 = 4394 |
| 20962 | CEFBS_HasNEON, // SRHADDv4i16 = 4395 |
| 20963 | CEFBS_HasNEON, // SRHADDv4i32 = 4396 |
| 20964 | CEFBS_HasNEON, // SRHADDv8i16 = 4397 |
| 20965 | CEFBS_HasNEON, // SRHADDv8i8 = 4398 |
| 20966 | CEFBS_HasSVE2, // SRI_ZZI_B = 4399 |
| 20967 | CEFBS_HasSVE2, // SRI_ZZI_D = 4400 |
| 20968 | CEFBS_HasSVE2, // SRI_ZZI_H = 4401 |
| 20969 | CEFBS_HasSVE2, // SRI_ZZI_S = 4402 |
| 20970 | CEFBS_HasNEON, // SRId = 4403 |
| 20971 | CEFBS_HasNEON, // SRIv16i8_shift = 4404 |
| 20972 | CEFBS_HasNEON, // SRIv2i32_shift = 4405 |
| 20973 | CEFBS_HasNEON, // SRIv2i64_shift = 4406 |
| 20974 | CEFBS_HasNEON, // SRIv4i16_shift = 4407 |
| 20975 | CEFBS_HasNEON, // SRIv4i32_shift = 4408 |
| 20976 | CEFBS_HasNEON, // SRIv8i16_shift = 4409 |
| 20977 | CEFBS_HasNEON, // SRIv8i8_shift = 4410 |
| 20978 | CEFBS_HasSVE2, // SRSHLR_ZPmZ_B = 4411 |
| 20979 | CEFBS_HasSVE2, // SRSHLR_ZPmZ_D = 4412 |
| 20980 | CEFBS_HasSVE2, // SRSHLR_ZPmZ_H = 4413 |
| 20981 | CEFBS_HasSVE2, // SRSHLR_ZPmZ_S = 4414 |
| 20982 | CEFBS_HasSVE2, // SRSHL_ZPmZ_B = 4415 |
| 20983 | CEFBS_HasSVE2, // SRSHL_ZPmZ_D = 4416 |
| 20984 | CEFBS_HasSVE2, // SRSHL_ZPmZ_H = 4417 |
| 20985 | CEFBS_HasSVE2, // SRSHL_ZPmZ_S = 4418 |
| 20986 | CEFBS_HasNEON, // SRSHLv16i8 = 4419 |
| 20987 | CEFBS_HasNEON, // SRSHLv1i64 = 4420 |
| 20988 | CEFBS_HasNEON, // SRSHLv2i32 = 4421 |
| 20989 | CEFBS_HasNEON, // SRSHLv2i64 = 4422 |
| 20990 | CEFBS_HasNEON, // SRSHLv4i16 = 4423 |
| 20991 | CEFBS_HasNEON, // SRSHLv4i32 = 4424 |
| 20992 | CEFBS_HasNEON, // SRSHLv8i16 = 4425 |
| 20993 | CEFBS_HasNEON, // SRSHLv8i8 = 4426 |
| 20994 | CEFBS_HasSVE2, // SRSHR_ZPmI_B = 4427 |
| 20995 | CEFBS_HasSVE2, // SRSHR_ZPmI_D = 4428 |
| 20996 | CEFBS_HasSVE2, // SRSHR_ZPmI_H = 4429 |
| 20997 | CEFBS_HasSVE2, // SRSHR_ZPmI_S = 4430 |
| 20998 | CEFBS_HasNEON, // SRSHRd = 4431 |
| 20999 | CEFBS_HasNEON, // SRSHRv16i8_shift = 4432 |
| 21000 | CEFBS_HasNEON, // SRSHRv2i32_shift = 4433 |
| 21001 | CEFBS_HasNEON, // SRSHRv2i64_shift = 4434 |
| 21002 | CEFBS_HasNEON, // SRSHRv4i16_shift = 4435 |
| 21003 | CEFBS_HasNEON, // SRSHRv4i32_shift = 4436 |
| 21004 | CEFBS_HasNEON, // SRSHRv8i16_shift = 4437 |
| 21005 | CEFBS_HasNEON, // SRSHRv8i8_shift = 4438 |
| 21006 | CEFBS_HasSVE2, // SRSRA_ZZI_B = 4439 |
| 21007 | CEFBS_HasSVE2, // SRSRA_ZZI_D = 4440 |
| 21008 | CEFBS_HasSVE2, // SRSRA_ZZI_H = 4441 |
| 21009 | CEFBS_HasSVE2, // SRSRA_ZZI_S = 4442 |
| 21010 | CEFBS_HasNEON, // SRSRAd = 4443 |
| 21011 | CEFBS_HasNEON, // SRSRAv16i8_shift = 4444 |
| 21012 | CEFBS_HasNEON, // SRSRAv2i32_shift = 4445 |
| 21013 | CEFBS_HasNEON, // SRSRAv2i64_shift = 4446 |
| 21014 | CEFBS_HasNEON, // SRSRAv4i16_shift = 4447 |
| 21015 | CEFBS_HasNEON, // SRSRAv4i32_shift = 4448 |
| 21016 | CEFBS_HasNEON, // SRSRAv8i16_shift = 4449 |
| 21017 | CEFBS_HasNEON, // SRSRAv8i8_shift = 4450 |
| 21018 | CEFBS_HasSVE2, // SSHLLB_ZZI_D = 4451 |
| 21019 | CEFBS_HasSVE2, // SSHLLB_ZZI_H = 4452 |
| 21020 | CEFBS_HasSVE2, // SSHLLB_ZZI_S = 4453 |
| 21021 | CEFBS_HasSVE2, // SSHLLT_ZZI_D = 4454 |
| 21022 | CEFBS_HasSVE2, // SSHLLT_ZZI_H = 4455 |
| 21023 | CEFBS_HasSVE2, // SSHLLT_ZZI_S = 4456 |
| 21024 | CEFBS_HasNEON, // SSHLLv16i8_shift = 4457 |
| 21025 | CEFBS_HasNEON, // SSHLLv2i32_shift = 4458 |
| 21026 | CEFBS_HasNEON, // SSHLLv4i16_shift = 4459 |
| 21027 | CEFBS_HasNEON, // SSHLLv4i32_shift = 4460 |
| 21028 | CEFBS_HasNEON, // SSHLLv8i16_shift = 4461 |
| 21029 | CEFBS_HasNEON, // SSHLLv8i8_shift = 4462 |
| 21030 | CEFBS_HasNEON, // SSHLv16i8 = 4463 |
| 21031 | CEFBS_HasNEON, // SSHLv1i64 = 4464 |
| 21032 | CEFBS_HasNEON, // SSHLv2i32 = 4465 |
| 21033 | CEFBS_HasNEON, // SSHLv2i64 = 4466 |
| 21034 | CEFBS_HasNEON, // SSHLv4i16 = 4467 |
| 21035 | CEFBS_HasNEON, // SSHLv4i32 = 4468 |
| 21036 | CEFBS_HasNEON, // SSHLv8i16 = 4469 |
| 21037 | CEFBS_HasNEON, // SSHLv8i8 = 4470 |
| 21038 | CEFBS_HasNEON, // SSHRd = 4471 |
| 21039 | CEFBS_HasNEON, // SSHRv16i8_shift = 4472 |
| 21040 | CEFBS_HasNEON, // SSHRv2i32_shift = 4473 |
| 21041 | CEFBS_HasNEON, // SSHRv2i64_shift = 4474 |
| 21042 | CEFBS_HasNEON, // SSHRv4i16_shift = 4475 |
| 21043 | CEFBS_HasNEON, // SSHRv4i32_shift = 4476 |
| 21044 | CEFBS_HasNEON, // SSHRv8i16_shift = 4477 |
| 21045 | CEFBS_HasNEON, // SSHRv8i8_shift = 4478 |
| 21046 | CEFBS_HasSVE2, // SSRA_ZZI_B = 4479 |
| 21047 | CEFBS_HasSVE2, // SSRA_ZZI_D = 4480 |
| 21048 | CEFBS_HasSVE2, // SSRA_ZZI_H = 4481 |
| 21049 | CEFBS_HasSVE2, // SSRA_ZZI_S = 4482 |
| 21050 | CEFBS_HasNEON, // SSRAd = 4483 |
| 21051 | CEFBS_HasNEON, // SSRAv16i8_shift = 4484 |
| 21052 | CEFBS_HasNEON, // SSRAv2i32_shift = 4485 |
| 21053 | CEFBS_HasNEON, // SSRAv2i64_shift = 4486 |
| 21054 | CEFBS_HasNEON, // SSRAv4i16_shift = 4487 |
| 21055 | CEFBS_HasNEON, // SSRAv4i32_shift = 4488 |
| 21056 | CEFBS_HasNEON, // SSRAv8i16_shift = 4489 |
| 21057 | CEFBS_HasNEON, // SSRAv8i8_shift = 4490 |
| 21058 | CEFBS_HasSVE, // SST1B_D_IMM = 4491 |
| 21059 | CEFBS_HasSVE, // SST1B_D_REAL = 4492 |
| 21060 | CEFBS_HasSVE, // SST1B_D_SXTW = 4493 |
| 21061 | CEFBS_HasSVE, // SST1B_D_UXTW = 4494 |
| 21062 | CEFBS_HasSVE, // SST1B_S_IMM = 4495 |
| 21063 | CEFBS_HasSVE, // SST1B_S_SXTW = 4496 |
| 21064 | CEFBS_HasSVE, // SST1B_S_UXTW = 4497 |
| 21065 | CEFBS_HasSVE, // SST1D_IMM = 4498 |
| 21066 | CEFBS_HasSVE, // SST1D_REAL = 4499 |
| 21067 | CEFBS_HasSVE, // SST1D_SCALED_SCALED_REAL = 4500 |
| 21068 | CEFBS_HasSVE, // SST1D_SXTW = 4501 |
| 21069 | CEFBS_HasSVE, // SST1D_SXTW_SCALED = 4502 |
| 21070 | CEFBS_HasSVE, // SST1D_UXTW = 4503 |
| 21071 | CEFBS_HasSVE, // SST1D_UXTW_SCALED = 4504 |
| 21072 | CEFBS_HasSVE, // SST1H_D_IMM = 4505 |
| 21073 | CEFBS_HasSVE, // SST1H_D_REAL = 4506 |
| 21074 | CEFBS_HasSVE, // SST1H_D_SCALED_SCALED_REAL = 4507 |
| 21075 | CEFBS_HasSVE, // SST1H_D_SXTW = 4508 |
| 21076 | CEFBS_HasSVE, // SST1H_D_SXTW_SCALED = 4509 |
| 21077 | CEFBS_HasSVE, // SST1H_D_UXTW = 4510 |
| 21078 | CEFBS_HasSVE, // SST1H_D_UXTW_SCALED = 4511 |
| 21079 | CEFBS_HasSVE, // SST1H_S_IMM = 4512 |
| 21080 | CEFBS_HasSVE, // SST1H_S_SXTW = 4513 |
| 21081 | CEFBS_HasSVE, // SST1H_S_SXTW_SCALED = 4514 |
| 21082 | CEFBS_HasSVE, // SST1H_S_UXTW = 4515 |
| 21083 | CEFBS_HasSVE, // SST1H_S_UXTW_SCALED = 4516 |
| 21084 | CEFBS_HasSVE, // SST1W_D_IMM = 4517 |
| 21085 | CEFBS_HasSVE, // SST1W_D_REAL = 4518 |
| 21086 | CEFBS_HasSVE, // SST1W_D_SCALED_SCALED_REAL = 4519 |
| 21087 | CEFBS_HasSVE, // SST1W_D_SXTW = 4520 |
| 21088 | CEFBS_HasSVE, // SST1W_D_SXTW_SCALED = 4521 |
| 21089 | CEFBS_HasSVE, // SST1W_D_UXTW = 4522 |
| 21090 | CEFBS_HasSVE, // SST1W_D_UXTW_SCALED = 4523 |
| 21091 | CEFBS_HasSVE, // SST1W_IMM = 4524 |
| 21092 | CEFBS_HasSVE, // SST1W_SXTW = 4525 |
| 21093 | CEFBS_HasSVE, // SST1W_SXTW_SCALED = 4526 |
| 21094 | CEFBS_HasSVE, // SST1W_UXTW = 4527 |
| 21095 | CEFBS_HasSVE, // SST1W_UXTW_SCALED = 4528 |
| 21096 | CEFBS_HasSVE2, // SSUBLBT_ZZZ_D = 4529 |
| 21097 | CEFBS_HasSVE2, // SSUBLBT_ZZZ_H = 4530 |
| 21098 | CEFBS_HasSVE2, // SSUBLBT_ZZZ_S = 4531 |
| 21099 | CEFBS_HasSVE2, // SSUBLB_ZZZ_D = 4532 |
| 21100 | CEFBS_HasSVE2, // SSUBLB_ZZZ_H = 4533 |
| 21101 | CEFBS_HasSVE2, // SSUBLB_ZZZ_S = 4534 |
| 21102 | CEFBS_HasSVE2, // SSUBLTB_ZZZ_D = 4535 |
| 21103 | CEFBS_HasSVE2, // SSUBLTB_ZZZ_H = 4536 |
| 21104 | CEFBS_HasSVE2, // SSUBLTB_ZZZ_S = 4537 |
| 21105 | CEFBS_HasSVE2, // SSUBLT_ZZZ_D = 4538 |
| 21106 | CEFBS_HasSVE2, // SSUBLT_ZZZ_H = 4539 |
| 21107 | CEFBS_HasSVE2, // SSUBLT_ZZZ_S = 4540 |
| 21108 | CEFBS_HasNEON, // SSUBLv16i8_v8i16 = 4541 |
| 21109 | CEFBS_HasNEON, // SSUBLv2i32_v2i64 = 4542 |
| 21110 | CEFBS_HasNEON, // SSUBLv4i16_v4i32 = 4543 |
| 21111 | CEFBS_HasNEON, // SSUBLv4i32_v2i64 = 4544 |
| 21112 | CEFBS_HasNEON, // SSUBLv8i16_v4i32 = 4545 |
| 21113 | CEFBS_HasNEON, // SSUBLv8i8_v8i16 = 4546 |
| 21114 | CEFBS_HasSVE2, // SSUBWB_ZZZ_D = 4547 |
| 21115 | CEFBS_HasSVE2, // SSUBWB_ZZZ_H = 4548 |
| 21116 | CEFBS_HasSVE2, // SSUBWB_ZZZ_S = 4549 |
| 21117 | CEFBS_HasSVE2, // SSUBWT_ZZZ_D = 4550 |
| 21118 | CEFBS_HasSVE2, // SSUBWT_ZZZ_H = 4551 |
| 21119 | CEFBS_HasSVE2, // SSUBWT_ZZZ_S = 4552 |
| 21120 | CEFBS_HasNEON, // SSUBWv16i8_v8i16 = 4553 |
| 21121 | CEFBS_HasNEON, // SSUBWv2i32_v2i64 = 4554 |
| 21122 | CEFBS_HasNEON, // SSUBWv4i16_v4i32 = 4555 |
| 21123 | CEFBS_HasNEON, // SSUBWv4i32_v2i64 = 4556 |
| 21124 | CEFBS_HasNEON, // SSUBWv8i16_v4i32 = 4557 |
| 21125 | CEFBS_HasNEON, // SSUBWv8i8_v8i16 = 4558 |
| 21126 | CEFBS_HasSVE, // ST1B = 4559 |
| 21127 | CEFBS_HasSVE, // ST1B_D = 4560 |
| 21128 | CEFBS_HasSVE, // ST1B_D_IMM = 4561 |
| 21129 | CEFBS_HasSVE, // ST1B_H = 4562 |
| 21130 | CEFBS_HasSVE, // ST1B_H_IMM = 4563 |
| 21131 | CEFBS_HasSVE, // ST1B_IMM = 4564 |
| 21132 | CEFBS_HasSVE, // ST1B_S = 4565 |
| 21133 | CEFBS_HasSVE, // ST1B_S_IMM = 4566 |
| 21134 | CEFBS_HasSVE, // ST1D = 4567 |
| 21135 | CEFBS_HasSVE, // ST1D_IMM = 4568 |
| 21136 | CEFBS_HasNEON, // ST1Fourv16b = 4569 |
| 21137 | CEFBS_HasNEON, // ST1Fourv16b_POST = 4570 |
| 21138 | CEFBS_HasNEON, // ST1Fourv1d = 4571 |
| 21139 | CEFBS_HasNEON, // ST1Fourv1d_POST = 4572 |
| 21140 | CEFBS_HasNEON, // ST1Fourv2d = 4573 |
| 21141 | CEFBS_HasNEON, // ST1Fourv2d_POST = 4574 |
| 21142 | CEFBS_HasNEON, // ST1Fourv2s = 4575 |
| 21143 | CEFBS_HasNEON, // ST1Fourv2s_POST = 4576 |
| 21144 | CEFBS_HasNEON, // ST1Fourv4h = 4577 |
| 21145 | CEFBS_HasNEON, // ST1Fourv4h_POST = 4578 |
| 21146 | CEFBS_HasNEON, // ST1Fourv4s = 4579 |
| 21147 | CEFBS_HasNEON, // ST1Fourv4s_POST = 4580 |
| 21148 | CEFBS_HasNEON, // ST1Fourv8b = 4581 |
| 21149 | CEFBS_HasNEON, // ST1Fourv8b_POST = 4582 |
| 21150 | CEFBS_HasNEON, // ST1Fourv8h = 4583 |
| 21151 | CEFBS_HasNEON, // ST1Fourv8h_POST = 4584 |
| 21152 | CEFBS_HasSVE, // ST1H = 4585 |
| 21153 | CEFBS_HasSVE, // ST1H_D = 4586 |
| 21154 | CEFBS_HasSVE, // ST1H_D_IMM = 4587 |
| 21155 | CEFBS_HasSVE, // ST1H_IMM = 4588 |
| 21156 | CEFBS_HasSVE, // ST1H_S = 4589 |
| 21157 | CEFBS_HasSVE, // ST1H_S_IMM = 4590 |
| 21158 | CEFBS_HasNEON, // ST1Onev16b = 4591 |
| 21159 | CEFBS_HasNEON, // ST1Onev16b_POST = 4592 |
| 21160 | CEFBS_HasNEON, // ST1Onev1d = 4593 |
| 21161 | CEFBS_HasNEON, // ST1Onev1d_POST = 4594 |
| 21162 | CEFBS_HasNEON, // ST1Onev2d = 4595 |
| 21163 | CEFBS_HasNEON, // ST1Onev2d_POST = 4596 |
| 21164 | CEFBS_HasNEON, // ST1Onev2s = 4597 |
| 21165 | CEFBS_HasNEON, // ST1Onev2s_POST = 4598 |
| 21166 | CEFBS_HasNEON, // ST1Onev4h = 4599 |
| 21167 | CEFBS_HasNEON, // ST1Onev4h_POST = 4600 |
| 21168 | CEFBS_HasNEON, // ST1Onev4s = 4601 |
| 21169 | CEFBS_HasNEON, // ST1Onev4s_POST = 4602 |
| 21170 | CEFBS_HasNEON, // ST1Onev8b = 4603 |
| 21171 | CEFBS_HasNEON, // ST1Onev8b_POST = 4604 |
| 21172 | CEFBS_HasNEON, // ST1Onev8h = 4605 |
| 21173 | CEFBS_HasNEON, // ST1Onev8h_POST = 4606 |
| 21174 | CEFBS_HasNEON, // ST1Threev16b = 4607 |
| 21175 | CEFBS_HasNEON, // ST1Threev16b_POST = 4608 |
| 21176 | CEFBS_HasNEON, // ST1Threev1d = 4609 |
| 21177 | CEFBS_HasNEON, // ST1Threev1d_POST = 4610 |
| 21178 | CEFBS_HasNEON, // ST1Threev2d = 4611 |
| 21179 | CEFBS_HasNEON, // ST1Threev2d_POST = 4612 |
| 21180 | CEFBS_HasNEON, // ST1Threev2s = 4613 |
| 21181 | CEFBS_HasNEON, // ST1Threev2s_POST = 4614 |
| 21182 | CEFBS_HasNEON, // ST1Threev4h = 4615 |
| 21183 | CEFBS_HasNEON, // ST1Threev4h_POST = 4616 |
| 21184 | CEFBS_HasNEON, // ST1Threev4s = 4617 |
| 21185 | CEFBS_HasNEON, // ST1Threev4s_POST = 4618 |
| 21186 | CEFBS_HasNEON, // ST1Threev8b = 4619 |
| 21187 | CEFBS_HasNEON, // ST1Threev8b_POST = 4620 |
| 21188 | CEFBS_HasNEON, // ST1Threev8h = 4621 |
| 21189 | CEFBS_HasNEON, // ST1Threev8h_POST = 4622 |
| 21190 | CEFBS_HasNEON, // ST1Twov16b = 4623 |
| 21191 | CEFBS_HasNEON, // ST1Twov16b_POST = 4624 |
| 21192 | CEFBS_HasNEON, // ST1Twov1d = 4625 |
| 21193 | CEFBS_HasNEON, // ST1Twov1d_POST = 4626 |
| 21194 | CEFBS_HasNEON, // ST1Twov2d = 4627 |
| 21195 | CEFBS_HasNEON, // ST1Twov2d_POST = 4628 |
| 21196 | CEFBS_HasNEON, // ST1Twov2s = 4629 |
| 21197 | CEFBS_HasNEON, // ST1Twov2s_POST = 4630 |
| 21198 | CEFBS_HasNEON, // ST1Twov4h = 4631 |
| 21199 | CEFBS_HasNEON, // ST1Twov4h_POST = 4632 |
| 21200 | CEFBS_HasNEON, // ST1Twov4s = 4633 |
| 21201 | CEFBS_HasNEON, // ST1Twov4s_POST = 4634 |
| 21202 | CEFBS_HasNEON, // ST1Twov8b = 4635 |
| 21203 | CEFBS_HasNEON, // ST1Twov8b_POST = 4636 |
| 21204 | CEFBS_HasNEON, // ST1Twov8h = 4637 |
| 21205 | CEFBS_HasNEON, // ST1Twov8h_POST = 4638 |
| 21206 | CEFBS_HasSVE, // ST1W = 4639 |
| 21207 | CEFBS_HasSVE, // ST1W_D = 4640 |
| 21208 | CEFBS_HasSVE, // ST1W_D_IMM = 4641 |
| 21209 | CEFBS_HasSVE, // ST1W_IMM = 4642 |
| 21210 | CEFBS_HasNEON, // ST1i16 = 4643 |
| 21211 | CEFBS_HasNEON, // ST1i16_POST = 4644 |
| 21212 | CEFBS_HasNEON, // ST1i32 = 4645 |
| 21213 | CEFBS_HasNEON, // ST1i32_POST = 4646 |
| 21214 | CEFBS_HasNEON, // ST1i64 = 4647 |
| 21215 | CEFBS_HasNEON, // ST1i64_POST = 4648 |
| 21216 | CEFBS_HasNEON, // ST1i8 = 4649 |
| 21217 | CEFBS_HasNEON, // ST1i8_POST = 4650 |
| 21218 | CEFBS_HasSVE, // ST2B = 4651 |
| 21219 | CEFBS_HasSVE, // ST2B_IMM = 4652 |
| 21220 | CEFBS_HasSVE, // ST2D = 4653 |
| 21221 | CEFBS_HasSVE, // ST2D_IMM = 4654 |
| 21222 | CEFBS_HasMTE, // ST2GOffset = 4655 |
| 21223 | CEFBS_HasMTE, // ST2GPostIndex = 4656 |
| 21224 | CEFBS_HasMTE, // ST2GPreIndex = 4657 |
| 21225 | CEFBS_HasSVE, // ST2H = 4658 |
| 21226 | CEFBS_HasSVE, // ST2H_IMM = 4659 |
| 21227 | CEFBS_HasNEON, // ST2Twov16b = 4660 |
| 21228 | CEFBS_HasNEON, // ST2Twov16b_POST = 4661 |
| 21229 | CEFBS_HasNEON, // ST2Twov2d = 4662 |
| 21230 | CEFBS_HasNEON, // ST2Twov2d_POST = 4663 |
| 21231 | CEFBS_HasNEON, // ST2Twov2s = 4664 |
| 21232 | CEFBS_HasNEON, // ST2Twov2s_POST = 4665 |
| 21233 | CEFBS_HasNEON, // ST2Twov4h = 4666 |
| 21234 | CEFBS_HasNEON, // ST2Twov4h_POST = 4667 |
| 21235 | CEFBS_HasNEON, // ST2Twov4s = 4668 |
| 21236 | CEFBS_HasNEON, // ST2Twov4s_POST = 4669 |
| 21237 | CEFBS_HasNEON, // ST2Twov8b = 4670 |
| 21238 | CEFBS_HasNEON, // ST2Twov8b_POST = 4671 |
| 21239 | CEFBS_HasNEON, // ST2Twov8h = 4672 |
| 21240 | CEFBS_HasNEON, // ST2Twov8h_POST = 4673 |
| 21241 | CEFBS_HasSVE, // ST2W = 4674 |
| 21242 | CEFBS_HasSVE, // ST2W_IMM = 4675 |
| 21243 | CEFBS_HasNEON, // ST2i16 = 4676 |
| 21244 | CEFBS_HasNEON, // ST2i16_POST = 4677 |
| 21245 | CEFBS_HasNEON, // ST2i32 = 4678 |
| 21246 | CEFBS_HasNEON, // ST2i32_POST = 4679 |
| 21247 | CEFBS_HasNEON, // ST2i64 = 4680 |
| 21248 | CEFBS_HasNEON, // ST2i64_POST = 4681 |
| 21249 | CEFBS_HasNEON, // ST2i8 = 4682 |
| 21250 | CEFBS_HasNEON, // ST2i8_POST = 4683 |
| 21251 | CEFBS_HasSVE, // ST3B = 4684 |
| 21252 | CEFBS_HasSVE, // ST3B_IMM = 4685 |
| 21253 | CEFBS_HasSVE, // ST3D = 4686 |
| 21254 | CEFBS_HasSVE, // ST3D_IMM = 4687 |
| 21255 | CEFBS_HasSVE, // ST3H = 4688 |
| 21256 | CEFBS_HasSVE, // ST3H_IMM = 4689 |
| 21257 | CEFBS_HasNEON, // ST3Threev16b = 4690 |
| 21258 | CEFBS_HasNEON, // ST3Threev16b_POST = 4691 |
| 21259 | CEFBS_HasNEON, // ST3Threev2d = 4692 |
| 21260 | CEFBS_HasNEON, // ST3Threev2d_POST = 4693 |
| 21261 | CEFBS_HasNEON, // ST3Threev2s = 4694 |
| 21262 | CEFBS_HasNEON, // ST3Threev2s_POST = 4695 |
| 21263 | CEFBS_HasNEON, // ST3Threev4h = 4696 |
| 21264 | CEFBS_HasNEON, // ST3Threev4h_POST = 4697 |
| 21265 | CEFBS_HasNEON, // ST3Threev4s = 4698 |
| 21266 | CEFBS_HasNEON, // ST3Threev4s_POST = 4699 |
| 21267 | CEFBS_HasNEON, // ST3Threev8b = 4700 |
| 21268 | CEFBS_HasNEON, // ST3Threev8b_POST = 4701 |
| 21269 | CEFBS_HasNEON, // ST3Threev8h = 4702 |
| 21270 | CEFBS_HasNEON, // ST3Threev8h_POST = 4703 |
| 21271 | CEFBS_HasSVE, // ST3W = 4704 |
| 21272 | CEFBS_HasSVE, // ST3W_IMM = 4705 |
| 21273 | CEFBS_HasNEON, // ST3i16 = 4706 |
| 21274 | CEFBS_HasNEON, // ST3i16_POST = 4707 |
| 21275 | CEFBS_HasNEON, // ST3i32 = 4708 |
| 21276 | CEFBS_HasNEON, // ST3i32_POST = 4709 |
| 21277 | CEFBS_HasNEON, // ST3i64 = 4710 |
| 21278 | CEFBS_HasNEON, // ST3i64_POST = 4711 |
| 21279 | CEFBS_HasNEON, // ST3i8 = 4712 |
| 21280 | CEFBS_HasNEON, // ST3i8_POST = 4713 |
| 21281 | CEFBS_HasSVE, // ST4B = 4714 |
| 21282 | CEFBS_HasSVE, // ST4B_IMM = 4715 |
| 21283 | CEFBS_HasSVE, // ST4D = 4716 |
| 21284 | CEFBS_HasSVE, // ST4D_IMM = 4717 |
| 21285 | CEFBS_HasNEON, // ST4Fourv16b = 4718 |
| 21286 | CEFBS_HasNEON, // ST4Fourv16b_POST = 4719 |
| 21287 | CEFBS_HasNEON, // ST4Fourv2d = 4720 |
| 21288 | CEFBS_HasNEON, // ST4Fourv2d_POST = 4721 |
| 21289 | CEFBS_HasNEON, // ST4Fourv2s = 4722 |
| 21290 | CEFBS_HasNEON, // ST4Fourv2s_POST = 4723 |
| 21291 | CEFBS_HasNEON, // ST4Fourv4h = 4724 |
| 21292 | CEFBS_HasNEON, // ST4Fourv4h_POST = 4725 |
| 21293 | CEFBS_HasNEON, // ST4Fourv4s = 4726 |
| 21294 | CEFBS_HasNEON, // ST4Fourv4s_POST = 4727 |
| 21295 | CEFBS_HasNEON, // ST4Fourv8b = 4728 |
| 21296 | CEFBS_HasNEON, // ST4Fourv8b_POST = 4729 |
| 21297 | CEFBS_HasNEON, // ST4Fourv8h = 4730 |
| 21298 | CEFBS_HasNEON, // ST4Fourv8h_POST = 4731 |
| 21299 | CEFBS_HasSVE, // ST4H = 4732 |
| 21300 | CEFBS_HasSVE, // ST4H_IMM = 4733 |
| 21301 | CEFBS_HasSVE, // ST4W = 4734 |
| 21302 | CEFBS_HasSVE, // ST4W_IMM = 4735 |
| 21303 | CEFBS_HasNEON, // ST4i16 = 4736 |
| 21304 | CEFBS_HasNEON, // ST4i16_POST = 4737 |
| 21305 | CEFBS_HasNEON, // ST4i32 = 4738 |
| 21306 | CEFBS_HasNEON, // ST4i32_POST = 4739 |
| 21307 | CEFBS_HasNEON, // ST4i64 = 4740 |
| 21308 | CEFBS_HasNEON, // ST4i64_POST = 4741 |
| 21309 | CEFBS_HasNEON, // ST4i8 = 4742 |
| 21310 | CEFBS_HasNEON, // ST4i8_POST = 4743 |
| 21311 | CEFBS_HasLS64, // ST64B = 4744 |
| 21312 | CEFBS_HasLS64, // ST64BV = 4745 |
| 21313 | CEFBS_HasLS64, // ST64BV0 = 4746 |
| 21314 | CEFBS_HasMTE, // STGM = 4747 |
| 21315 | CEFBS_HasMTE, // STGOffset = 4748 |
| 21316 | CEFBS_HasMTE, // STGPi = 4749 |
| 21317 | CEFBS_HasMTE, // STGPostIndex = 4750 |
| 21318 | CEFBS_HasMTE, // STGPpost = 4751 |
| 21319 | CEFBS_HasMTE, // STGPpre = 4752 |
| 21320 | CEFBS_HasMTE, // STGPreIndex = 4753 |
| 21321 | CEFBS_HasLOR, // STLLRB = 4754 |
| 21322 | CEFBS_HasLOR, // STLLRH = 4755 |
| 21323 | CEFBS_HasLOR, // STLLRW = 4756 |
| 21324 | CEFBS_HasLOR, // STLLRX = 4757 |
| 21325 | CEFBS_None, // STLRB = 4758 |
| 21326 | CEFBS_None, // STLRH = 4759 |
| 21327 | CEFBS_None, // STLRW = 4760 |
| 21328 | CEFBS_None, // STLRX = 4761 |
| 21329 | CEFBS_HasRCPC_IMMO, // STLURBi = 4762 |
| 21330 | CEFBS_HasRCPC_IMMO, // STLURHi = 4763 |
| 21331 | CEFBS_HasRCPC_IMMO, // STLURWi = 4764 |
| 21332 | CEFBS_HasRCPC_IMMO, // STLURXi = 4765 |
| 21333 | CEFBS_None, // STLXPW = 4766 |
| 21334 | CEFBS_None, // STLXPX = 4767 |
| 21335 | CEFBS_None, // STLXRB = 4768 |
| 21336 | CEFBS_None, // STLXRH = 4769 |
| 21337 | CEFBS_None, // STLXRW = 4770 |
| 21338 | CEFBS_None, // STLXRX = 4771 |
| 21339 | CEFBS_None, // STNPDi = 4772 |
| 21340 | CEFBS_None, // STNPQi = 4773 |
| 21341 | CEFBS_None, // STNPSi = 4774 |
| 21342 | CEFBS_None, // STNPWi = 4775 |
| 21343 | CEFBS_None, // STNPXi = 4776 |
| 21344 | CEFBS_HasSVE, // STNT1B_ZRI = 4777 |
| 21345 | CEFBS_HasSVE, // STNT1B_ZRR = 4778 |
| 21346 | CEFBS_HasSVE2, // STNT1B_ZZR_D_REAL = 4779 |
| 21347 | CEFBS_HasSVE2, // STNT1B_ZZR_S_REAL = 4780 |
| 21348 | CEFBS_HasSVE, // STNT1D_ZRI = 4781 |
| 21349 | CEFBS_HasSVE, // STNT1D_ZRR = 4782 |
| 21350 | CEFBS_HasSVE2, // STNT1D_ZZR_D_REAL = 4783 |
| 21351 | CEFBS_HasSVE, // STNT1H_ZRI = 4784 |
| 21352 | CEFBS_HasSVE, // STNT1H_ZRR = 4785 |
| 21353 | CEFBS_HasSVE2, // STNT1H_ZZR_D_REAL = 4786 |
| 21354 | CEFBS_HasSVE2, // STNT1H_ZZR_S_REAL = 4787 |
| 21355 | CEFBS_HasSVE, // STNT1W_ZRI = 4788 |
| 21356 | CEFBS_HasSVE, // STNT1W_ZRR = 4789 |
| 21357 | CEFBS_HasSVE2, // STNT1W_ZZR_D_REAL = 4790 |
| 21358 | CEFBS_HasSVE2, // STNT1W_ZZR_S_REAL = 4791 |
| 21359 | CEFBS_None, // STPDi = 4792 |
| 21360 | CEFBS_None, // STPDpost = 4793 |
| 21361 | CEFBS_None, // STPDpre = 4794 |
| 21362 | CEFBS_None, // STPQi = 4795 |
| 21363 | CEFBS_None, // STPQpost = 4796 |
| 21364 | CEFBS_None, // STPQpre = 4797 |
| 21365 | CEFBS_None, // STPSi = 4798 |
| 21366 | CEFBS_None, // STPSpost = 4799 |
| 21367 | CEFBS_None, // STPSpre = 4800 |
| 21368 | CEFBS_None, // STPWi = 4801 |
| 21369 | CEFBS_None, // STPWpost = 4802 |
| 21370 | CEFBS_None, // STPWpre = 4803 |
| 21371 | CEFBS_None, // STPXi = 4804 |
| 21372 | CEFBS_None, // STPXpost = 4805 |
| 21373 | CEFBS_None, // STPXpre = 4806 |
| 21374 | CEFBS_None, // STRBBpost = 4807 |
| 21375 | CEFBS_None, // STRBBpre = 4808 |
| 21376 | CEFBS_None, // STRBBroW = 4809 |
| 21377 | CEFBS_None, // STRBBroX = 4810 |
| 21378 | CEFBS_None, // STRBBui = 4811 |
| 21379 | CEFBS_None, // STRBpost = 4812 |
| 21380 | CEFBS_None, // STRBpre = 4813 |
| 21381 | CEFBS_None, // STRBroW = 4814 |
| 21382 | CEFBS_None, // STRBroX = 4815 |
| 21383 | CEFBS_None, // STRBui = 4816 |
| 21384 | CEFBS_None, // STRDpost = 4817 |
| 21385 | CEFBS_None, // STRDpre = 4818 |
| 21386 | CEFBS_None, // STRDroW = 4819 |
| 21387 | CEFBS_None, // STRDroX = 4820 |
| 21388 | CEFBS_None, // STRDui = 4821 |
| 21389 | CEFBS_None, // STRHHpost = 4822 |
| 21390 | CEFBS_None, // STRHHpre = 4823 |
| 21391 | CEFBS_None, // STRHHroW = 4824 |
| 21392 | CEFBS_None, // STRHHroX = 4825 |
| 21393 | CEFBS_None, // STRHHui = 4826 |
| 21394 | CEFBS_None, // STRHpost = 4827 |
| 21395 | CEFBS_None, // STRHpre = 4828 |
| 21396 | CEFBS_None, // STRHroW = 4829 |
| 21397 | CEFBS_None, // STRHroX = 4830 |
| 21398 | CEFBS_None, // STRHui = 4831 |
| 21399 | CEFBS_None, // STRQpost = 4832 |
| 21400 | CEFBS_None, // STRQpre = 4833 |
| 21401 | CEFBS_None, // STRQroW = 4834 |
| 21402 | CEFBS_None, // STRQroX = 4835 |
| 21403 | CEFBS_None, // STRQui = 4836 |
| 21404 | CEFBS_None, // STRSpost = 4837 |
| 21405 | CEFBS_None, // STRSpre = 4838 |
| 21406 | CEFBS_None, // STRSroW = 4839 |
| 21407 | CEFBS_None, // STRSroX = 4840 |
| 21408 | CEFBS_None, // STRSui = 4841 |
| 21409 | CEFBS_None, // STRWpost = 4842 |
| 21410 | CEFBS_None, // STRWpre = 4843 |
| 21411 | CEFBS_None, // STRWroW = 4844 |
| 21412 | CEFBS_None, // STRWroX = 4845 |
| 21413 | CEFBS_None, // STRWui = 4846 |
| 21414 | CEFBS_None, // STRXpost = 4847 |
| 21415 | CEFBS_None, // STRXpre = 4848 |
| 21416 | CEFBS_None, // STRXroW = 4849 |
| 21417 | CEFBS_None, // STRXroX = 4850 |
| 21418 | CEFBS_None, // STRXui = 4851 |
| 21419 | CEFBS_HasSVE, // STR_PXI = 4852 |
| 21420 | CEFBS_HasSVE, // STR_ZXI = 4853 |
| 21421 | CEFBS_None, // STTRBi = 4854 |
| 21422 | CEFBS_None, // STTRHi = 4855 |
| 21423 | CEFBS_None, // STTRWi = 4856 |
| 21424 | CEFBS_None, // STTRXi = 4857 |
| 21425 | CEFBS_None, // STURBBi = 4858 |
| 21426 | CEFBS_None, // STURBi = 4859 |
| 21427 | CEFBS_None, // STURDi = 4860 |
| 21428 | CEFBS_None, // STURHHi = 4861 |
| 21429 | CEFBS_None, // STURHi = 4862 |
| 21430 | CEFBS_None, // STURQi = 4863 |
| 21431 | CEFBS_None, // STURSi = 4864 |
| 21432 | CEFBS_None, // STURWi = 4865 |
| 21433 | CEFBS_None, // STURXi = 4866 |
| 21434 | CEFBS_None, // STXPW = 4867 |
| 21435 | CEFBS_None, // STXPX = 4868 |
| 21436 | CEFBS_None, // STXRB = 4869 |
| 21437 | CEFBS_None, // STXRH = 4870 |
| 21438 | CEFBS_None, // STXRW = 4871 |
| 21439 | CEFBS_None, // STXRX = 4872 |
| 21440 | CEFBS_HasMTE, // STZ2GOffset = 4873 |
| 21441 | CEFBS_HasMTE, // STZ2GPostIndex = 4874 |
| 21442 | CEFBS_HasMTE, // STZ2GPreIndex = 4875 |
| 21443 | CEFBS_HasMTE, // STZGM = 4876 |
| 21444 | CEFBS_HasMTE, // STZGOffset = 4877 |
| 21445 | CEFBS_HasMTE, // STZGPostIndex = 4878 |
| 21446 | CEFBS_HasMTE, // STZGPreIndex = 4879 |
| 21447 | CEFBS_HasMTE, // SUBG = 4880 |
| 21448 | CEFBS_HasSVE2, // SUBHNB_ZZZ_B = 4881 |
| 21449 | CEFBS_HasSVE2, // SUBHNB_ZZZ_H = 4882 |
| 21450 | CEFBS_HasSVE2, // SUBHNB_ZZZ_S = 4883 |
| 21451 | CEFBS_HasSVE2, // SUBHNT_ZZZ_B = 4884 |
| 21452 | CEFBS_HasSVE2, // SUBHNT_ZZZ_H = 4885 |
| 21453 | CEFBS_HasSVE2, // SUBHNT_ZZZ_S = 4886 |
| 21454 | CEFBS_HasNEON, // SUBHNv2i64_v2i32 = 4887 |
| 21455 | CEFBS_HasNEON, // SUBHNv2i64_v4i32 = 4888 |
| 21456 | CEFBS_HasNEON, // SUBHNv4i32_v4i16 = 4889 |
| 21457 | CEFBS_HasNEON, // SUBHNv4i32_v8i16 = 4890 |
| 21458 | CEFBS_HasNEON, // SUBHNv8i16_v16i8 = 4891 |
| 21459 | CEFBS_HasNEON, // SUBHNv8i16_v8i8 = 4892 |
| 21460 | CEFBS_HasMTE, // SUBP = 4893 |
| 21461 | CEFBS_HasMTE, // SUBPS = 4894 |
| 21462 | CEFBS_HasSVE, // SUBR_ZI_B = 4895 |
| 21463 | CEFBS_HasSVE, // SUBR_ZI_D = 4896 |
| 21464 | CEFBS_HasSVE, // SUBR_ZI_H = 4897 |
| 21465 | CEFBS_HasSVE, // SUBR_ZI_S = 4898 |
| 21466 | CEFBS_HasSVE, // SUBR_ZPmZ_B = 4899 |
| 21467 | CEFBS_HasSVE, // SUBR_ZPmZ_D = 4900 |
| 21468 | CEFBS_HasSVE, // SUBR_ZPmZ_H = 4901 |
| 21469 | CEFBS_HasSVE, // SUBR_ZPmZ_S = 4902 |
| 21470 | CEFBS_None, // SUBSWri = 4903 |
| 21471 | CEFBS_None, // SUBSWrs = 4904 |
| 21472 | CEFBS_None, // SUBSWrx = 4905 |
| 21473 | CEFBS_None, // SUBSXri = 4906 |
| 21474 | CEFBS_None, // SUBSXrs = 4907 |
| 21475 | CEFBS_None, // SUBSXrx = 4908 |
| 21476 | CEFBS_None, // SUBSXrx64 = 4909 |
| 21477 | CEFBS_None, // SUBWri = 4910 |
| 21478 | CEFBS_None, // SUBWrs = 4911 |
| 21479 | CEFBS_None, // SUBWrx = 4912 |
| 21480 | CEFBS_None, // SUBXri = 4913 |
| 21481 | CEFBS_None, // SUBXrs = 4914 |
| 21482 | CEFBS_None, // SUBXrx = 4915 |
| 21483 | CEFBS_None, // SUBXrx64 = 4916 |
| 21484 | CEFBS_HasSVE, // SUB_ZI_B = 4917 |
| 21485 | CEFBS_HasSVE, // SUB_ZI_D = 4918 |
| 21486 | CEFBS_HasSVE, // SUB_ZI_H = 4919 |
| 21487 | CEFBS_HasSVE, // SUB_ZI_S = 4920 |
| 21488 | CEFBS_HasSVE, // SUB_ZPmZ_B = 4921 |
| 21489 | CEFBS_HasSVE, // SUB_ZPmZ_D = 4922 |
| 21490 | CEFBS_HasSVE, // SUB_ZPmZ_H = 4923 |
| 21491 | CEFBS_HasSVE, // SUB_ZPmZ_S = 4924 |
| 21492 | CEFBS_HasSVE, // SUB_ZZZ_B = 4925 |
| 21493 | CEFBS_HasSVE, // SUB_ZZZ_D = 4926 |
| 21494 | CEFBS_HasSVE, // SUB_ZZZ_H = 4927 |
| 21495 | CEFBS_HasSVE, // SUB_ZZZ_S = 4928 |
| 21496 | CEFBS_HasNEON, // SUBv16i8 = 4929 |
| 21497 | CEFBS_HasNEON, // SUBv1i64 = 4930 |
| 21498 | CEFBS_HasNEON, // SUBv2i32 = 4931 |
| 21499 | CEFBS_HasNEON, // SUBv2i64 = 4932 |
| 21500 | CEFBS_HasNEON, // SUBv4i16 = 4933 |
| 21501 | CEFBS_HasNEON, // SUBv4i32 = 4934 |
| 21502 | CEFBS_HasNEON, // SUBv8i16 = 4935 |
| 21503 | CEFBS_HasNEON, // SUBv8i8 = 4936 |
| 21504 | CEFBS_HasSVE_HasMatMulInt8, // SUDOT_ZZZI = 4937 |
| 21505 | CEFBS_HasMatMulInt8, // SUDOTlanev16i8 = 4938 |
| 21506 | CEFBS_HasMatMulInt8, // SUDOTlanev8i8 = 4939 |
| 21507 | CEFBS_HasSVE, // SUNPKHI_ZZ_D = 4940 |
| 21508 | CEFBS_HasSVE, // SUNPKHI_ZZ_H = 4941 |
| 21509 | CEFBS_HasSVE, // SUNPKHI_ZZ_S = 4942 |
| 21510 | CEFBS_HasSVE, // SUNPKLO_ZZ_D = 4943 |
| 21511 | CEFBS_HasSVE, // SUNPKLO_ZZ_H = 4944 |
| 21512 | CEFBS_HasSVE, // SUNPKLO_ZZ_S = 4945 |
| 21513 | CEFBS_HasSVE2, // SUQADD_ZPmZ_B = 4946 |
| 21514 | CEFBS_HasSVE2, // SUQADD_ZPmZ_D = 4947 |
| 21515 | CEFBS_HasSVE2, // SUQADD_ZPmZ_H = 4948 |
| 21516 | CEFBS_HasSVE2, // SUQADD_ZPmZ_S = 4949 |
| 21517 | CEFBS_HasNEON, // SUQADDv16i8 = 4950 |
| 21518 | CEFBS_HasNEON, // SUQADDv1i16 = 4951 |
| 21519 | CEFBS_HasNEON, // SUQADDv1i32 = 4952 |
| 21520 | CEFBS_HasNEON, // SUQADDv1i64 = 4953 |
| 21521 | CEFBS_HasNEON, // SUQADDv1i8 = 4954 |
| 21522 | CEFBS_HasNEON, // SUQADDv2i32 = 4955 |
| 21523 | CEFBS_HasNEON, // SUQADDv2i64 = 4956 |
| 21524 | CEFBS_HasNEON, // SUQADDv4i16 = 4957 |
| 21525 | CEFBS_HasNEON, // SUQADDv4i32 = 4958 |
| 21526 | CEFBS_HasNEON, // SUQADDv8i16 = 4959 |
| 21527 | CEFBS_HasNEON, // SUQADDv8i8 = 4960 |
| 21528 | CEFBS_None, // SVC = 4961 |
| 21529 | CEFBS_HasLSE, // SWPAB = 4962 |
| 21530 | CEFBS_HasLSE, // SWPAH = 4963 |
| 21531 | CEFBS_HasLSE, // SWPALB = 4964 |
| 21532 | CEFBS_HasLSE, // SWPALH = 4965 |
| 21533 | CEFBS_HasLSE, // SWPALW = 4966 |
| 21534 | CEFBS_HasLSE, // SWPALX = 4967 |
| 21535 | CEFBS_HasLSE, // SWPAW = 4968 |
| 21536 | CEFBS_HasLSE, // SWPAX = 4969 |
| 21537 | CEFBS_HasLSE, // SWPB = 4970 |
| 21538 | CEFBS_HasLSE, // SWPH = 4971 |
| 21539 | CEFBS_HasLSE, // SWPLB = 4972 |
| 21540 | CEFBS_HasLSE, // SWPLH = 4973 |
| 21541 | CEFBS_HasLSE, // SWPLW = 4974 |
| 21542 | CEFBS_HasLSE, // SWPLX = 4975 |
| 21543 | CEFBS_HasLSE, // SWPW = 4976 |
| 21544 | CEFBS_HasLSE, // SWPX = 4977 |
| 21545 | CEFBS_HasSVE, // SXTB_ZPmZ_D = 4978 |
| 21546 | CEFBS_HasSVE, // SXTB_ZPmZ_H = 4979 |
| 21547 | CEFBS_HasSVE, // SXTB_ZPmZ_S = 4980 |
| 21548 | CEFBS_HasSVE, // SXTH_ZPmZ_D = 4981 |
| 21549 | CEFBS_HasSVE, // SXTH_ZPmZ_S = 4982 |
| 21550 | CEFBS_HasSVE, // SXTW_ZPmZ_D = 4983 |
| 21551 | CEFBS_None, // SYSLxt = 4984 |
| 21552 | CEFBS_None, // SYSxt = 4985 |
| 21553 | CEFBS_HasSVE2, // TBL_ZZZZ_B = 4986 |
| 21554 | CEFBS_HasSVE2, // TBL_ZZZZ_D = 4987 |
| 21555 | CEFBS_HasSVE2, // TBL_ZZZZ_H = 4988 |
| 21556 | CEFBS_HasSVE2, // TBL_ZZZZ_S = 4989 |
| 21557 | CEFBS_HasSVE, // TBL_ZZZ_B = 4990 |
| 21558 | CEFBS_HasSVE, // TBL_ZZZ_D = 4991 |
| 21559 | CEFBS_HasSVE, // TBL_ZZZ_H = 4992 |
| 21560 | CEFBS_HasSVE, // TBL_ZZZ_S = 4993 |
| 21561 | CEFBS_HasNEON, // TBLv16i8Four = 4994 |
| 21562 | CEFBS_HasNEON, // TBLv16i8One = 4995 |
| 21563 | CEFBS_HasNEON, // TBLv16i8Three = 4996 |
| 21564 | CEFBS_HasNEON, // TBLv16i8Two = 4997 |
| 21565 | CEFBS_HasNEON, // TBLv8i8Four = 4998 |
| 21566 | CEFBS_HasNEON, // TBLv8i8One = 4999 |
| 21567 | CEFBS_HasNEON, // TBLv8i8Three = 5000 |
| 21568 | CEFBS_HasNEON, // TBLv8i8Two = 5001 |
| 21569 | CEFBS_None, // TBNZW = 5002 |
| 21570 | CEFBS_None, // TBNZX = 5003 |
| 21571 | CEFBS_HasSVE2, // TBX_ZZZ_B = 5004 |
| 21572 | CEFBS_HasSVE2, // TBX_ZZZ_D = 5005 |
| 21573 | CEFBS_HasSVE2, // TBX_ZZZ_H = 5006 |
| 21574 | CEFBS_HasSVE2, // TBX_ZZZ_S = 5007 |
| 21575 | CEFBS_HasNEON, // TBXv16i8Four = 5008 |
| 21576 | CEFBS_HasNEON, // TBXv16i8One = 5009 |
| 21577 | CEFBS_HasNEON, // TBXv16i8Three = 5010 |
| 21578 | CEFBS_HasNEON, // TBXv16i8Two = 5011 |
| 21579 | CEFBS_HasNEON, // TBXv8i8Four = 5012 |
| 21580 | CEFBS_HasNEON, // TBXv8i8One = 5013 |
| 21581 | CEFBS_HasNEON, // TBXv8i8Three = 5014 |
| 21582 | CEFBS_HasNEON, // TBXv8i8Two = 5015 |
| 21583 | CEFBS_None, // TBZW = 5016 |
| 21584 | CEFBS_None, // TBZX = 5017 |
| 21585 | CEFBS_HasTME, // TCANCEL = 5018 |
| 21586 | CEFBS_HasTME, // TCOMMIT = 5019 |
| 21587 | CEFBS_HasSVE, // TRN1_PPP_B = 5020 |
| 21588 | CEFBS_HasSVE, // TRN1_PPP_D = 5021 |
| 21589 | CEFBS_HasSVE, // TRN1_PPP_H = 5022 |
| 21590 | CEFBS_HasSVE, // TRN1_PPP_S = 5023 |
| 21591 | CEFBS_HasSVE, // TRN1_ZZZ_B = 5024 |
| 21592 | CEFBS_HasSVE, // TRN1_ZZZ_D = 5025 |
| 21593 | CEFBS_HasSVE, // TRN1_ZZZ_H = 5026 |
| 21594 | CEFBS_HasSVE_HasMatMulFP64, // TRN1_ZZZ_Q = 5027 |
| 21595 | CEFBS_HasSVE, // TRN1_ZZZ_S = 5028 |
| 21596 | CEFBS_HasNEON, // TRN1v16i8 = 5029 |
| 21597 | CEFBS_HasNEON, // TRN1v2i32 = 5030 |
| 21598 | CEFBS_HasNEON, // TRN1v2i64 = 5031 |
| 21599 | CEFBS_HasNEON, // TRN1v4i16 = 5032 |
| 21600 | CEFBS_HasNEON, // TRN1v4i32 = 5033 |
| 21601 | CEFBS_HasNEON, // TRN1v8i16 = 5034 |
| 21602 | CEFBS_HasNEON, // TRN1v8i8 = 5035 |
| 21603 | CEFBS_HasSVE, // TRN2_PPP_B = 5036 |
| 21604 | CEFBS_HasSVE, // TRN2_PPP_D = 5037 |
| 21605 | CEFBS_HasSVE, // TRN2_PPP_H = 5038 |
| 21606 | CEFBS_HasSVE, // TRN2_PPP_S = 5039 |
| 21607 | CEFBS_HasSVE, // TRN2_ZZZ_B = 5040 |
| 21608 | CEFBS_HasSVE, // TRN2_ZZZ_D = 5041 |
| 21609 | CEFBS_HasSVE, // TRN2_ZZZ_H = 5042 |
| 21610 | CEFBS_HasSVE_HasMatMulFP64, // TRN2_ZZZ_Q = 5043 |
| 21611 | CEFBS_HasSVE, // TRN2_ZZZ_S = 5044 |
| 21612 | CEFBS_HasNEON, // TRN2v16i8 = 5045 |
| 21613 | CEFBS_HasNEON, // TRN2v2i32 = 5046 |
| 21614 | CEFBS_HasNEON, // TRN2v2i64 = 5047 |
| 21615 | CEFBS_HasNEON, // TRN2v4i16 = 5048 |
| 21616 | CEFBS_HasNEON, // TRN2v4i32 = 5049 |
| 21617 | CEFBS_HasNEON, // TRN2v8i16 = 5050 |
| 21618 | CEFBS_HasNEON, // TRN2v8i8 = 5051 |
| 21619 | CEFBS_HasTRACEV8_4, // TSB = 5052 |
| 21620 | CEFBS_HasTME, // TSTART = 5053 |
| 21621 | CEFBS_HasTME, // TTEST = 5054 |
| 21622 | CEFBS_HasSVE2, // UABALB_ZZZ_D = 5055 |
| 21623 | CEFBS_HasSVE2, // UABALB_ZZZ_H = 5056 |
| 21624 | CEFBS_HasSVE2, // UABALB_ZZZ_S = 5057 |
| 21625 | CEFBS_HasSVE2, // UABALT_ZZZ_D = 5058 |
| 21626 | CEFBS_HasSVE2, // UABALT_ZZZ_H = 5059 |
| 21627 | CEFBS_HasSVE2, // UABALT_ZZZ_S = 5060 |
| 21628 | CEFBS_HasNEON, // UABALv16i8_v8i16 = 5061 |
| 21629 | CEFBS_HasNEON, // UABALv2i32_v2i64 = 5062 |
| 21630 | CEFBS_HasNEON, // UABALv4i16_v4i32 = 5063 |
| 21631 | CEFBS_HasNEON, // UABALv4i32_v2i64 = 5064 |
| 21632 | CEFBS_HasNEON, // UABALv8i16_v4i32 = 5065 |
| 21633 | CEFBS_HasNEON, // UABALv8i8_v8i16 = 5066 |
| 21634 | CEFBS_HasSVE2, // UABA_ZZZ_B = 5067 |
| 21635 | CEFBS_HasSVE2, // UABA_ZZZ_D = 5068 |
| 21636 | CEFBS_HasSVE2, // UABA_ZZZ_H = 5069 |
| 21637 | CEFBS_HasSVE2, // UABA_ZZZ_S = 5070 |
| 21638 | CEFBS_HasNEON, // UABAv16i8 = 5071 |
| 21639 | CEFBS_HasNEON, // UABAv2i32 = 5072 |
| 21640 | CEFBS_HasNEON, // UABAv4i16 = 5073 |
| 21641 | CEFBS_HasNEON, // UABAv4i32 = 5074 |
| 21642 | CEFBS_HasNEON, // UABAv8i16 = 5075 |
| 21643 | CEFBS_HasNEON, // UABAv8i8 = 5076 |
| 21644 | CEFBS_HasSVE2, // UABDLB_ZZZ_D = 5077 |
| 21645 | CEFBS_HasSVE2, // UABDLB_ZZZ_H = 5078 |
| 21646 | CEFBS_HasSVE2, // UABDLB_ZZZ_S = 5079 |
| 21647 | CEFBS_HasSVE2, // UABDLT_ZZZ_D = 5080 |
| 21648 | CEFBS_HasSVE2, // UABDLT_ZZZ_H = 5081 |
| 21649 | CEFBS_HasSVE2, // UABDLT_ZZZ_S = 5082 |
| 21650 | CEFBS_HasNEON, // UABDLv16i8_v8i16 = 5083 |
| 21651 | CEFBS_HasNEON, // UABDLv2i32_v2i64 = 5084 |
| 21652 | CEFBS_HasNEON, // UABDLv4i16_v4i32 = 5085 |
| 21653 | CEFBS_HasNEON, // UABDLv4i32_v2i64 = 5086 |
| 21654 | CEFBS_HasNEON, // UABDLv8i16_v4i32 = 5087 |
| 21655 | CEFBS_HasNEON, // UABDLv8i8_v8i16 = 5088 |
| 21656 | CEFBS_HasSVE, // UABD_ZPmZ_B = 5089 |
| 21657 | CEFBS_HasSVE, // UABD_ZPmZ_D = 5090 |
| 21658 | CEFBS_HasSVE, // UABD_ZPmZ_H = 5091 |
| 21659 | CEFBS_HasSVE, // UABD_ZPmZ_S = 5092 |
| 21660 | CEFBS_HasNEON, // UABDv16i8 = 5093 |
| 21661 | CEFBS_HasNEON, // UABDv2i32 = 5094 |
| 21662 | CEFBS_HasNEON, // UABDv4i16 = 5095 |
| 21663 | CEFBS_HasNEON, // UABDv4i32 = 5096 |
| 21664 | CEFBS_HasNEON, // UABDv8i16 = 5097 |
| 21665 | CEFBS_HasNEON, // UABDv8i8 = 5098 |
| 21666 | CEFBS_HasSVE2, // UADALP_ZPmZ_D = 5099 |
| 21667 | CEFBS_HasSVE2, // UADALP_ZPmZ_H = 5100 |
| 21668 | CEFBS_HasSVE2, // UADALP_ZPmZ_S = 5101 |
| 21669 | CEFBS_HasNEON, // UADALPv16i8_v8i16 = 5102 |
| 21670 | CEFBS_HasNEON, // UADALPv2i32_v1i64 = 5103 |
| 21671 | CEFBS_HasNEON, // UADALPv4i16_v2i32 = 5104 |
| 21672 | CEFBS_HasNEON, // UADALPv4i32_v2i64 = 5105 |
| 21673 | CEFBS_HasNEON, // UADALPv8i16_v4i32 = 5106 |
| 21674 | CEFBS_HasNEON, // UADALPv8i8_v4i16 = 5107 |
| 21675 | CEFBS_HasSVE2, // UADDLB_ZZZ_D = 5108 |
| 21676 | CEFBS_HasSVE2, // UADDLB_ZZZ_H = 5109 |
| 21677 | CEFBS_HasSVE2, // UADDLB_ZZZ_S = 5110 |
| 21678 | CEFBS_HasNEON, // UADDLPv16i8_v8i16 = 5111 |
| 21679 | CEFBS_HasNEON, // UADDLPv2i32_v1i64 = 5112 |
| 21680 | CEFBS_HasNEON, // UADDLPv4i16_v2i32 = 5113 |
| 21681 | CEFBS_HasNEON, // UADDLPv4i32_v2i64 = 5114 |
| 21682 | CEFBS_HasNEON, // UADDLPv8i16_v4i32 = 5115 |
| 21683 | CEFBS_HasNEON, // UADDLPv8i8_v4i16 = 5116 |
| 21684 | CEFBS_HasSVE2, // UADDLT_ZZZ_D = 5117 |
| 21685 | CEFBS_HasSVE2, // UADDLT_ZZZ_H = 5118 |
| 21686 | CEFBS_HasSVE2, // UADDLT_ZZZ_S = 5119 |
| 21687 | CEFBS_HasNEON, // UADDLVv16i8v = 5120 |
| 21688 | CEFBS_HasNEON, // UADDLVv4i16v = 5121 |
| 21689 | CEFBS_HasNEON, // UADDLVv4i32v = 5122 |
| 21690 | CEFBS_HasNEON, // UADDLVv8i16v = 5123 |
| 21691 | CEFBS_HasNEON, // UADDLVv8i8v = 5124 |
| 21692 | CEFBS_HasNEON, // UADDLv16i8_v8i16 = 5125 |
| 21693 | CEFBS_HasNEON, // UADDLv2i32_v2i64 = 5126 |
| 21694 | CEFBS_HasNEON, // UADDLv4i16_v4i32 = 5127 |
| 21695 | CEFBS_HasNEON, // UADDLv4i32_v2i64 = 5128 |
| 21696 | CEFBS_HasNEON, // UADDLv8i16_v4i32 = 5129 |
| 21697 | CEFBS_HasNEON, // UADDLv8i8_v8i16 = 5130 |
| 21698 | CEFBS_HasSVE, // UADDV_VPZ_B = 5131 |
| 21699 | CEFBS_HasSVE, // UADDV_VPZ_D = 5132 |
| 21700 | CEFBS_HasSVE, // UADDV_VPZ_H = 5133 |
| 21701 | CEFBS_HasSVE, // UADDV_VPZ_S = 5134 |
| 21702 | CEFBS_HasSVE2, // UADDWB_ZZZ_D = 5135 |
| 21703 | CEFBS_HasSVE2, // UADDWB_ZZZ_H = 5136 |
| 21704 | CEFBS_HasSVE2, // UADDWB_ZZZ_S = 5137 |
| 21705 | CEFBS_HasSVE2, // UADDWT_ZZZ_D = 5138 |
| 21706 | CEFBS_HasSVE2, // UADDWT_ZZZ_H = 5139 |
| 21707 | CEFBS_HasSVE2, // UADDWT_ZZZ_S = 5140 |
| 21708 | CEFBS_HasNEON, // UADDWv16i8_v8i16 = 5141 |
| 21709 | CEFBS_HasNEON, // UADDWv2i32_v2i64 = 5142 |
| 21710 | CEFBS_HasNEON, // UADDWv4i16_v4i32 = 5143 |
| 21711 | CEFBS_HasNEON, // UADDWv4i32_v2i64 = 5144 |
| 21712 | CEFBS_HasNEON, // UADDWv8i16_v4i32 = 5145 |
| 21713 | CEFBS_HasNEON, // UADDWv8i8_v8i16 = 5146 |
| 21714 | CEFBS_None, // UBFMWri = 5147 |
| 21715 | CEFBS_None, // UBFMXri = 5148 |
| 21716 | CEFBS_HasFPARMv8, // UCVTFSWDri = 5149 |
| 21717 | CEFBS_HasFullFP16, // UCVTFSWHri = 5150 |
| 21718 | CEFBS_HasFPARMv8, // UCVTFSWSri = 5151 |
| 21719 | CEFBS_HasFPARMv8, // UCVTFSXDri = 5152 |
| 21720 | CEFBS_HasFullFP16, // UCVTFSXHri = 5153 |
| 21721 | CEFBS_HasFPARMv8, // UCVTFSXSri = 5154 |
| 21722 | CEFBS_HasFPARMv8, // UCVTFUWDri = 5155 |
| 21723 | CEFBS_HasFullFP16, // UCVTFUWHri = 5156 |
| 21724 | CEFBS_HasFPARMv8, // UCVTFUWSri = 5157 |
| 21725 | CEFBS_HasFPARMv8, // UCVTFUXDri = 5158 |
| 21726 | CEFBS_HasFullFP16, // UCVTFUXHri = 5159 |
| 21727 | CEFBS_HasFPARMv8, // UCVTFUXSri = 5160 |
| 21728 | CEFBS_HasSVE, // UCVTF_ZPmZ_DtoD = 5161 |
| 21729 | CEFBS_HasSVE, // UCVTF_ZPmZ_DtoH = 5162 |
| 21730 | CEFBS_HasSVE, // UCVTF_ZPmZ_DtoS = 5163 |
| 21731 | CEFBS_HasSVE, // UCVTF_ZPmZ_HtoH = 5164 |
| 21732 | CEFBS_HasSVE, // UCVTF_ZPmZ_StoD = 5165 |
| 21733 | CEFBS_HasSVE, // UCVTF_ZPmZ_StoH = 5166 |
| 21734 | CEFBS_HasSVE, // UCVTF_ZPmZ_StoS = 5167 |
| 21735 | CEFBS_HasNEON, // UCVTFd = 5168 |
| 21736 | CEFBS_HasNEON_HasFullFP16, // UCVTFh = 5169 |
| 21737 | CEFBS_HasNEON, // UCVTFs = 5170 |
| 21738 | CEFBS_HasNEON_HasFullFP16, // UCVTFv1i16 = 5171 |
| 21739 | CEFBS_HasNEON, // UCVTFv1i32 = 5172 |
| 21740 | CEFBS_HasNEON, // UCVTFv1i64 = 5173 |
| 21741 | CEFBS_HasNEON, // UCVTFv2f32 = 5174 |
| 21742 | CEFBS_HasNEON, // UCVTFv2f64 = 5175 |
| 21743 | CEFBS_HasNEON, // UCVTFv2i32_shift = 5176 |
| 21744 | CEFBS_HasNEON, // UCVTFv2i64_shift = 5177 |
| 21745 | CEFBS_HasNEON_HasFullFP16, // UCVTFv4f16 = 5178 |
| 21746 | CEFBS_HasNEON, // UCVTFv4f32 = 5179 |
| 21747 | CEFBS_HasNEON_HasFullFP16, // UCVTFv4i16_shift = 5180 |
| 21748 | CEFBS_HasNEON, // UCVTFv4i32_shift = 5181 |
| 21749 | CEFBS_HasNEON_HasFullFP16, // UCVTFv8f16 = 5182 |
| 21750 | CEFBS_HasNEON_HasFullFP16, // UCVTFv8i16_shift = 5183 |
| 21751 | CEFBS_None, // UDF = 5184 |
| 21752 | CEFBS_HasSVE, // UDIVR_ZPmZ_D = 5185 |
| 21753 | CEFBS_HasSVE, // UDIVR_ZPmZ_S = 5186 |
| 21754 | CEFBS_None, // UDIVWr = 5187 |
| 21755 | CEFBS_None, // UDIVXr = 5188 |
| 21756 | CEFBS_HasSVE, // UDIV_ZPmZ_D = 5189 |
| 21757 | CEFBS_HasSVE, // UDIV_ZPmZ_S = 5190 |
| 21758 | CEFBS_HasSVE, // UDOT_ZZZI_D = 5191 |
| 21759 | CEFBS_HasSVE, // UDOT_ZZZI_S = 5192 |
| 21760 | CEFBS_HasSVE, // UDOT_ZZZ_D = 5193 |
| 21761 | CEFBS_HasSVE, // UDOT_ZZZ_S = 5194 |
| 21762 | CEFBS_HasDotProd, // UDOTlanev16i8 = 5195 |
| 21763 | CEFBS_HasDotProd, // UDOTlanev8i8 = 5196 |
| 21764 | CEFBS_HasDotProd, // UDOTv16i8 = 5197 |
| 21765 | CEFBS_HasDotProd, // UDOTv8i8 = 5198 |
| 21766 | CEFBS_HasSVE2, // UHADD_ZPmZ_B = 5199 |
| 21767 | CEFBS_HasSVE2, // UHADD_ZPmZ_D = 5200 |
| 21768 | CEFBS_HasSVE2, // UHADD_ZPmZ_H = 5201 |
| 21769 | CEFBS_HasSVE2, // UHADD_ZPmZ_S = 5202 |
| 21770 | CEFBS_HasNEON, // UHADDv16i8 = 5203 |
| 21771 | CEFBS_HasNEON, // UHADDv2i32 = 5204 |
| 21772 | CEFBS_HasNEON, // UHADDv4i16 = 5205 |
| 21773 | CEFBS_HasNEON, // UHADDv4i32 = 5206 |
| 21774 | CEFBS_HasNEON, // UHADDv8i16 = 5207 |
| 21775 | CEFBS_HasNEON, // UHADDv8i8 = 5208 |
| 21776 | CEFBS_HasSVE2, // UHSUBR_ZPmZ_B = 5209 |
| 21777 | CEFBS_HasSVE2, // UHSUBR_ZPmZ_D = 5210 |
| 21778 | CEFBS_HasSVE2, // UHSUBR_ZPmZ_H = 5211 |
| 21779 | CEFBS_HasSVE2, // UHSUBR_ZPmZ_S = 5212 |
| 21780 | CEFBS_HasSVE2, // UHSUB_ZPmZ_B = 5213 |
| 21781 | CEFBS_HasSVE2, // UHSUB_ZPmZ_D = 5214 |
| 21782 | CEFBS_HasSVE2, // UHSUB_ZPmZ_H = 5215 |
| 21783 | CEFBS_HasSVE2, // UHSUB_ZPmZ_S = 5216 |
| 21784 | CEFBS_HasNEON, // UHSUBv16i8 = 5217 |
| 21785 | CEFBS_HasNEON, // UHSUBv2i32 = 5218 |
| 21786 | CEFBS_HasNEON, // UHSUBv4i16 = 5219 |
| 21787 | CEFBS_HasNEON, // UHSUBv4i32 = 5220 |
| 21788 | CEFBS_HasNEON, // UHSUBv8i16 = 5221 |
| 21789 | CEFBS_HasNEON, // UHSUBv8i8 = 5222 |
| 21790 | CEFBS_None, // UMADDLrrr = 5223 |
| 21791 | CEFBS_HasSVE2, // UMAXP_ZPmZ_B = 5224 |
| 21792 | CEFBS_HasSVE2, // UMAXP_ZPmZ_D = 5225 |
| 21793 | CEFBS_HasSVE2, // UMAXP_ZPmZ_H = 5226 |
| 21794 | CEFBS_HasSVE2, // UMAXP_ZPmZ_S = 5227 |
| 21795 | CEFBS_HasNEON, // UMAXPv16i8 = 5228 |
| 21796 | CEFBS_HasNEON, // UMAXPv2i32 = 5229 |
| 21797 | CEFBS_HasNEON, // UMAXPv4i16 = 5230 |
| 21798 | CEFBS_HasNEON, // UMAXPv4i32 = 5231 |
| 21799 | CEFBS_HasNEON, // UMAXPv8i16 = 5232 |
| 21800 | CEFBS_HasNEON, // UMAXPv8i8 = 5233 |
| 21801 | CEFBS_HasSVE, // UMAXV_VPZ_B = 5234 |
| 21802 | CEFBS_HasSVE, // UMAXV_VPZ_D = 5235 |
| 21803 | CEFBS_HasSVE, // UMAXV_VPZ_H = 5236 |
| 21804 | CEFBS_HasSVE, // UMAXV_VPZ_S = 5237 |
| 21805 | CEFBS_HasNEON, // UMAXVv16i8v = 5238 |
| 21806 | CEFBS_HasNEON, // UMAXVv4i16v = 5239 |
| 21807 | CEFBS_HasNEON, // UMAXVv4i32v = 5240 |
| 21808 | CEFBS_HasNEON, // UMAXVv8i16v = 5241 |
| 21809 | CEFBS_HasNEON, // UMAXVv8i8v = 5242 |
| 21810 | CEFBS_HasSVE, // UMAX_ZI_B = 5243 |
| 21811 | CEFBS_HasSVE, // UMAX_ZI_D = 5244 |
| 21812 | CEFBS_HasSVE, // UMAX_ZI_H = 5245 |
| 21813 | CEFBS_HasSVE, // UMAX_ZI_S = 5246 |
| 21814 | CEFBS_HasSVE, // UMAX_ZPmZ_B = 5247 |
| 21815 | CEFBS_HasSVE, // UMAX_ZPmZ_D = 5248 |
| 21816 | CEFBS_HasSVE, // UMAX_ZPmZ_H = 5249 |
| 21817 | CEFBS_HasSVE, // UMAX_ZPmZ_S = 5250 |
| 21818 | CEFBS_HasNEON, // UMAXv16i8 = 5251 |
| 21819 | CEFBS_HasNEON, // UMAXv2i32 = 5252 |
| 21820 | CEFBS_HasNEON, // UMAXv4i16 = 5253 |
| 21821 | CEFBS_HasNEON, // UMAXv4i32 = 5254 |
| 21822 | CEFBS_HasNEON, // UMAXv8i16 = 5255 |
| 21823 | CEFBS_HasNEON, // UMAXv8i8 = 5256 |
| 21824 | CEFBS_HasSVE2, // UMINP_ZPmZ_B = 5257 |
| 21825 | CEFBS_HasSVE2, // UMINP_ZPmZ_D = 5258 |
| 21826 | CEFBS_HasSVE2, // UMINP_ZPmZ_H = 5259 |
| 21827 | CEFBS_HasSVE2, // UMINP_ZPmZ_S = 5260 |
| 21828 | CEFBS_HasNEON, // UMINPv16i8 = 5261 |
| 21829 | CEFBS_HasNEON, // UMINPv2i32 = 5262 |
| 21830 | CEFBS_HasNEON, // UMINPv4i16 = 5263 |
| 21831 | CEFBS_HasNEON, // UMINPv4i32 = 5264 |
| 21832 | CEFBS_HasNEON, // UMINPv8i16 = 5265 |
| 21833 | CEFBS_HasNEON, // UMINPv8i8 = 5266 |
| 21834 | CEFBS_HasSVE, // UMINV_VPZ_B = 5267 |
| 21835 | CEFBS_HasSVE, // UMINV_VPZ_D = 5268 |
| 21836 | CEFBS_HasSVE, // UMINV_VPZ_H = 5269 |
| 21837 | CEFBS_HasSVE, // UMINV_VPZ_S = 5270 |
| 21838 | CEFBS_HasNEON, // UMINVv16i8v = 5271 |
| 21839 | CEFBS_HasNEON, // UMINVv4i16v = 5272 |
| 21840 | CEFBS_HasNEON, // UMINVv4i32v = 5273 |
| 21841 | CEFBS_HasNEON, // UMINVv8i16v = 5274 |
| 21842 | CEFBS_HasNEON, // UMINVv8i8v = 5275 |
| 21843 | CEFBS_HasSVE, // UMIN_ZI_B = 5276 |
| 21844 | CEFBS_HasSVE, // UMIN_ZI_D = 5277 |
| 21845 | CEFBS_HasSVE, // UMIN_ZI_H = 5278 |
| 21846 | CEFBS_HasSVE, // UMIN_ZI_S = 5279 |
| 21847 | CEFBS_HasSVE, // UMIN_ZPmZ_B = 5280 |
| 21848 | CEFBS_HasSVE, // UMIN_ZPmZ_D = 5281 |
| 21849 | CEFBS_HasSVE, // UMIN_ZPmZ_H = 5282 |
| 21850 | CEFBS_HasSVE, // UMIN_ZPmZ_S = 5283 |
| 21851 | CEFBS_HasNEON, // UMINv16i8 = 5284 |
| 21852 | CEFBS_HasNEON, // UMINv2i32 = 5285 |
| 21853 | CEFBS_HasNEON, // UMINv4i16 = 5286 |
| 21854 | CEFBS_HasNEON, // UMINv4i32 = 5287 |
| 21855 | CEFBS_HasNEON, // UMINv8i16 = 5288 |
| 21856 | CEFBS_HasNEON, // UMINv8i8 = 5289 |
| 21857 | CEFBS_HasSVE2, // UMLALB_ZZZI_D = 5290 |
| 21858 | CEFBS_HasSVE2, // UMLALB_ZZZI_S = 5291 |
| 21859 | CEFBS_HasSVE2, // UMLALB_ZZZ_D = 5292 |
| 21860 | CEFBS_HasSVE2, // UMLALB_ZZZ_H = 5293 |
| 21861 | CEFBS_HasSVE2, // UMLALB_ZZZ_S = 5294 |
| 21862 | CEFBS_HasSVE2, // UMLALT_ZZZI_D = 5295 |
| 21863 | CEFBS_HasSVE2, // UMLALT_ZZZI_S = 5296 |
| 21864 | CEFBS_HasSVE2, // UMLALT_ZZZ_D = 5297 |
| 21865 | CEFBS_HasSVE2, // UMLALT_ZZZ_H = 5298 |
| 21866 | CEFBS_HasSVE2, // UMLALT_ZZZ_S = 5299 |
| 21867 | CEFBS_HasNEON, // UMLALv16i8_v8i16 = 5300 |
| 21868 | CEFBS_HasNEON, // UMLALv2i32_indexed = 5301 |
| 21869 | CEFBS_HasNEON, // UMLALv2i32_v2i64 = 5302 |
| 21870 | CEFBS_HasNEON, // UMLALv4i16_indexed = 5303 |
| 21871 | CEFBS_HasNEON, // UMLALv4i16_v4i32 = 5304 |
| 21872 | CEFBS_HasNEON, // UMLALv4i32_indexed = 5305 |
| 21873 | CEFBS_HasNEON, // UMLALv4i32_v2i64 = 5306 |
| 21874 | CEFBS_HasNEON, // UMLALv8i16_indexed = 5307 |
| 21875 | CEFBS_HasNEON, // UMLALv8i16_v4i32 = 5308 |
| 21876 | CEFBS_HasNEON, // UMLALv8i8_v8i16 = 5309 |
| 21877 | CEFBS_HasSVE2, // UMLSLB_ZZZI_D = 5310 |
| 21878 | CEFBS_HasSVE2, // UMLSLB_ZZZI_S = 5311 |
| 21879 | CEFBS_HasSVE2, // UMLSLB_ZZZ_D = 5312 |
| 21880 | CEFBS_HasSVE2, // UMLSLB_ZZZ_H = 5313 |
| 21881 | CEFBS_HasSVE2, // UMLSLB_ZZZ_S = 5314 |
| 21882 | CEFBS_HasSVE2, // UMLSLT_ZZZI_D = 5315 |
| 21883 | CEFBS_HasSVE2, // UMLSLT_ZZZI_S = 5316 |
| 21884 | CEFBS_HasSVE2, // UMLSLT_ZZZ_D = 5317 |
| 21885 | CEFBS_HasSVE2, // UMLSLT_ZZZ_H = 5318 |
| 21886 | CEFBS_HasSVE2, // UMLSLT_ZZZ_S = 5319 |
| 21887 | CEFBS_HasNEON, // UMLSLv16i8_v8i16 = 5320 |
| 21888 | CEFBS_HasNEON, // UMLSLv2i32_indexed = 5321 |
| 21889 | CEFBS_HasNEON, // UMLSLv2i32_v2i64 = 5322 |
| 21890 | CEFBS_HasNEON, // UMLSLv4i16_indexed = 5323 |
| 21891 | CEFBS_HasNEON, // UMLSLv4i16_v4i32 = 5324 |
| 21892 | CEFBS_HasNEON, // UMLSLv4i32_indexed = 5325 |
| 21893 | CEFBS_HasNEON, // UMLSLv4i32_v2i64 = 5326 |
| 21894 | CEFBS_HasNEON, // UMLSLv8i16_indexed = 5327 |
| 21895 | CEFBS_HasNEON, // UMLSLv8i16_v4i32 = 5328 |
| 21896 | CEFBS_HasNEON, // UMLSLv8i8_v8i16 = 5329 |
| 21897 | CEFBS_HasMatMulInt8, // UMMLA = 5330 |
| 21898 | CEFBS_HasSVE_HasMatMulInt8, // UMMLA_ZZZ = 5331 |
| 21899 | CEFBS_HasNEON, // UMOVvi16 = 5332 |
| 21900 | CEFBS_HasNEON, // UMOVvi32 = 5333 |
| 21901 | CEFBS_HasNEON, // UMOVvi64 = 5334 |
| 21902 | CEFBS_HasNEON, // UMOVvi8 = 5335 |
| 21903 | CEFBS_None, // UMSUBLrrr = 5336 |
| 21904 | CEFBS_HasSVE, // UMULH_ZPmZ_B = 5337 |
| 21905 | CEFBS_HasSVE, // UMULH_ZPmZ_D = 5338 |
| 21906 | CEFBS_HasSVE, // UMULH_ZPmZ_H = 5339 |
| 21907 | CEFBS_HasSVE, // UMULH_ZPmZ_S = 5340 |
| 21908 | CEFBS_HasSVE2, // UMULH_ZZZ_B = 5341 |
| 21909 | CEFBS_HasSVE2, // UMULH_ZZZ_D = 5342 |
| 21910 | CEFBS_HasSVE2, // UMULH_ZZZ_H = 5343 |
| 21911 | CEFBS_HasSVE2, // UMULH_ZZZ_S = 5344 |
| 21912 | CEFBS_None, // UMULHrr = 5345 |
| 21913 | CEFBS_HasSVE2, // UMULLB_ZZZI_D = 5346 |
| 21914 | CEFBS_HasSVE2, // UMULLB_ZZZI_S = 5347 |
| 21915 | CEFBS_HasSVE2, // UMULLB_ZZZ_D = 5348 |
| 21916 | CEFBS_HasSVE2, // UMULLB_ZZZ_H = 5349 |
| 21917 | CEFBS_HasSVE2, // UMULLB_ZZZ_S = 5350 |
| 21918 | CEFBS_HasSVE2, // UMULLT_ZZZI_D = 5351 |
| 21919 | CEFBS_HasSVE2, // UMULLT_ZZZI_S = 5352 |
| 21920 | CEFBS_HasSVE2, // UMULLT_ZZZ_D = 5353 |
| 21921 | CEFBS_HasSVE2, // UMULLT_ZZZ_H = 5354 |
| 21922 | CEFBS_HasSVE2, // UMULLT_ZZZ_S = 5355 |
| 21923 | CEFBS_HasNEON, // UMULLv16i8_v8i16 = 5356 |
| 21924 | CEFBS_HasNEON, // UMULLv2i32_indexed = 5357 |
| 21925 | CEFBS_HasNEON, // UMULLv2i32_v2i64 = 5358 |
| 21926 | CEFBS_HasNEON, // UMULLv4i16_indexed = 5359 |
| 21927 | CEFBS_HasNEON, // UMULLv4i16_v4i32 = 5360 |
| 21928 | CEFBS_HasNEON, // UMULLv4i32_indexed = 5361 |
| 21929 | CEFBS_HasNEON, // UMULLv4i32_v2i64 = 5362 |
| 21930 | CEFBS_HasNEON, // UMULLv8i16_indexed = 5363 |
| 21931 | CEFBS_HasNEON, // UMULLv8i16_v4i32 = 5364 |
| 21932 | CEFBS_HasNEON, // UMULLv8i8_v8i16 = 5365 |
| 21933 | CEFBS_HasSVE, // UQADD_ZI_B = 5366 |
| 21934 | CEFBS_HasSVE, // UQADD_ZI_D = 5367 |
| 21935 | CEFBS_HasSVE, // UQADD_ZI_H = 5368 |
| 21936 | CEFBS_HasSVE, // UQADD_ZI_S = 5369 |
| 21937 | CEFBS_HasSVE2, // UQADD_ZPmZ_B = 5370 |
| 21938 | CEFBS_HasSVE2, // UQADD_ZPmZ_D = 5371 |
| 21939 | CEFBS_HasSVE2, // UQADD_ZPmZ_H = 5372 |
| 21940 | CEFBS_HasSVE2, // UQADD_ZPmZ_S = 5373 |
| 21941 | CEFBS_HasSVE, // UQADD_ZZZ_B = 5374 |
| 21942 | CEFBS_HasSVE, // UQADD_ZZZ_D = 5375 |
| 21943 | CEFBS_HasSVE, // UQADD_ZZZ_H = 5376 |
| 21944 | CEFBS_HasSVE, // UQADD_ZZZ_S = 5377 |
| 21945 | CEFBS_HasNEON, // UQADDv16i8 = 5378 |
| 21946 | CEFBS_HasNEON, // UQADDv1i16 = 5379 |
| 21947 | CEFBS_HasNEON, // UQADDv1i32 = 5380 |
| 21948 | CEFBS_HasNEON, // UQADDv1i64 = 5381 |
| 21949 | CEFBS_HasNEON, // UQADDv1i8 = 5382 |
| 21950 | CEFBS_HasNEON, // UQADDv2i32 = 5383 |
| 21951 | CEFBS_HasNEON, // UQADDv2i64 = 5384 |
| 21952 | CEFBS_HasNEON, // UQADDv4i16 = 5385 |
| 21953 | CEFBS_HasNEON, // UQADDv4i32 = 5386 |
| 21954 | CEFBS_HasNEON, // UQADDv8i16 = 5387 |
| 21955 | CEFBS_HasNEON, // UQADDv8i8 = 5388 |
| 21956 | CEFBS_HasSVE, // UQDECB_WPiI = 5389 |
| 21957 | CEFBS_HasSVE, // UQDECB_XPiI = 5390 |
| 21958 | CEFBS_HasSVE, // UQDECD_WPiI = 5391 |
| 21959 | CEFBS_HasSVE, // UQDECD_XPiI = 5392 |
| 21960 | CEFBS_HasSVE, // UQDECD_ZPiI = 5393 |
| 21961 | CEFBS_HasSVE, // UQDECH_WPiI = 5394 |
| 21962 | CEFBS_HasSVE, // UQDECH_XPiI = 5395 |
| 21963 | CEFBS_HasSVE, // UQDECH_ZPiI = 5396 |
| 21964 | CEFBS_HasSVE, // UQDECP_WP_B = 5397 |
| 21965 | CEFBS_HasSVE, // UQDECP_WP_D = 5398 |
| 21966 | CEFBS_HasSVE, // UQDECP_WP_H = 5399 |
| 21967 | CEFBS_HasSVE, // UQDECP_WP_S = 5400 |
| 21968 | CEFBS_HasSVE, // UQDECP_XP_B = 5401 |
| 21969 | CEFBS_HasSVE, // UQDECP_XP_D = 5402 |
| 21970 | CEFBS_HasSVE, // UQDECP_XP_H = 5403 |
| 21971 | CEFBS_HasSVE, // UQDECP_XP_S = 5404 |
| 21972 | CEFBS_HasSVE, // UQDECP_ZP_D = 5405 |
| 21973 | CEFBS_HasSVE, // UQDECP_ZP_H = 5406 |
| 21974 | CEFBS_HasSVE, // UQDECP_ZP_S = 5407 |
| 21975 | CEFBS_HasSVE, // UQDECW_WPiI = 5408 |
| 21976 | CEFBS_HasSVE, // UQDECW_XPiI = 5409 |
| 21977 | CEFBS_HasSVE, // UQDECW_ZPiI = 5410 |
| 21978 | CEFBS_HasSVE, // UQINCB_WPiI = 5411 |
| 21979 | CEFBS_HasSVE, // UQINCB_XPiI = 5412 |
| 21980 | CEFBS_HasSVE, // UQINCD_WPiI = 5413 |
| 21981 | CEFBS_HasSVE, // UQINCD_XPiI = 5414 |
| 21982 | CEFBS_HasSVE, // UQINCD_ZPiI = 5415 |
| 21983 | CEFBS_HasSVE, // UQINCH_WPiI = 5416 |
| 21984 | CEFBS_HasSVE, // UQINCH_XPiI = 5417 |
| 21985 | CEFBS_HasSVE, // UQINCH_ZPiI = 5418 |
| 21986 | CEFBS_HasSVE, // UQINCP_WP_B = 5419 |
| 21987 | CEFBS_HasSVE, // UQINCP_WP_D = 5420 |
| 21988 | CEFBS_HasSVE, // UQINCP_WP_H = 5421 |
| 21989 | CEFBS_HasSVE, // UQINCP_WP_S = 5422 |
| 21990 | CEFBS_HasSVE, // UQINCP_XP_B = 5423 |
| 21991 | CEFBS_HasSVE, // UQINCP_XP_D = 5424 |
| 21992 | CEFBS_HasSVE, // UQINCP_XP_H = 5425 |
| 21993 | CEFBS_HasSVE, // UQINCP_XP_S = 5426 |
| 21994 | CEFBS_HasSVE, // UQINCP_ZP_D = 5427 |
| 21995 | CEFBS_HasSVE, // UQINCP_ZP_H = 5428 |
| 21996 | CEFBS_HasSVE, // UQINCP_ZP_S = 5429 |
| 21997 | CEFBS_HasSVE, // UQINCW_WPiI = 5430 |
| 21998 | CEFBS_HasSVE, // UQINCW_XPiI = 5431 |
| 21999 | CEFBS_HasSVE, // UQINCW_ZPiI = 5432 |
| 22000 | CEFBS_HasSVE2, // UQRSHLR_ZPmZ_B = 5433 |
| 22001 | CEFBS_HasSVE2, // UQRSHLR_ZPmZ_D = 5434 |
| 22002 | CEFBS_HasSVE2, // UQRSHLR_ZPmZ_H = 5435 |
| 22003 | CEFBS_HasSVE2, // UQRSHLR_ZPmZ_S = 5436 |
| 22004 | CEFBS_HasSVE2, // UQRSHL_ZPmZ_B = 5437 |
| 22005 | CEFBS_HasSVE2, // UQRSHL_ZPmZ_D = 5438 |
| 22006 | CEFBS_HasSVE2, // UQRSHL_ZPmZ_H = 5439 |
| 22007 | CEFBS_HasSVE2, // UQRSHL_ZPmZ_S = 5440 |
| 22008 | CEFBS_HasNEON, // UQRSHLv16i8 = 5441 |
| 22009 | CEFBS_HasNEON, // UQRSHLv1i16 = 5442 |
| 22010 | CEFBS_HasNEON, // UQRSHLv1i32 = 5443 |
| 22011 | CEFBS_HasNEON, // UQRSHLv1i64 = 5444 |
| 22012 | CEFBS_HasNEON, // UQRSHLv1i8 = 5445 |
| 22013 | CEFBS_HasNEON, // UQRSHLv2i32 = 5446 |
| 22014 | CEFBS_HasNEON, // UQRSHLv2i64 = 5447 |
| 22015 | CEFBS_HasNEON, // UQRSHLv4i16 = 5448 |
| 22016 | CEFBS_HasNEON, // UQRSHLv4i32 = 5449 |
| 22017 | CEFBS_HasNEON, // UQRSHLv8i16 = 5450 |
| 22018 | CEFBS_HasNEON, // UQRSHLv8i8 = 5451 |
| 22019 | CEFBS_HasSVE2, // UQRSHRNB_ZZI_B = 5452 |
| 22020 | CEFBS_HasSVE2, // UQRSHRNB_ZZI_H = 5453 |
| 22021 | CEFBS_HasSVE2, // UQRSHRNB_ZZI_S = 5454 |
| 22022 | CEFBS_HasSVE2, // UQRSHRNT_ZZI_B = 5455 |
| 22023 | CEFBS_HasSVE2, // UQRSHRNT_ZZI_H = 5456 |
| 22024 | CEFBS_HasSVE2, // UQRSHRNT_ZZI_S = 5457 |
| 22025 | CEFBS_HasNEON, // UQRSHRNb = 5458 |
| 22026 | CEFBS_HasNEON, // UQRSHRNh = 5459 |
| 22027 | CEFBS_HasNEON, // UQRSHRNs = 5460 |
| 22028 | CEFBS_HasNEON, // UQRSHRNv16i8_shift = 5461 |
| 22029 | CEFBS_HasNEON, // UQRSHRNv2i32_shift = 5462 |
| 22030 | CEFBS_HasNEON, // UQRSHRNv4i16_shift = 5463 |
| 22031 | CEFBS_HasNEON, // UQRSHRNv4i32_shift = 5464 |
| 22032 | CEFBS_HasNEON, // UQRSHRNv8i16_shift = 5465 |
| 22033 | CEFBS_HasNEON, // UQRSHRNv8i8_shift = 5466 |
| 22034 | CEFBS_HasSVE2, // UQSHLR_ZPmZ_B = 5467 |
| 22035 | CEFBS_HasSVE2, // UQSHLR_ZPmZ_D = 5468 |
| 22036 | CEFBS_HasSVE2, // UQSHLR_ZPmZ_H = 5469 |
| 22037 | CEFBS_HasSVE2, // UQSHLR_ZPmZ_S = 5470 |
| 22038 | CEFBS_HasSVE2, // UQSHL_ZPmI_B = 5471 |
| 22039 | CEFBS_HasSVE2, // UQSHL_ZPmI_D = 5472 |
| 22040 | CEFBS_HasSVE2, // UQSHL_ZPmI_H = 5473 |
| 22041 | CEFBS_HasSVE2, // UQSHL_ZPmI_S = 5474 |
| 22042 | CEFBS_HasSVE2, // UQSHL_ZPmZ_B = 5475 |
| 22043 | CEFBS_HasSVE2, // UQSHL_ZPmZ_D = 5476 |
| 22044 | CEFBS_HasSVE2, // UQSHL_ZPmZ_H = 5477 |
| 22045 | CEFBS_HasSVE2, // UQSHL_ZPmZ_S = 5478 |
| 22046 | CEFBS_HasNEON, // UQSHLb = 5479 |
| 22047 | CEFBS_HasNEON, // UQSHLd = 5480 |
| 22048 | CEFBS_HasNEON, // UQSHLh = 5481 |
| 22049 | CEFBS_HasNEON, // UQSHLs = 5482 |
| 22050 | CEFBS_HasNEON, // UQSHLv16i8 = 5483 |
| 22051 | CEFBS_HasNEON, // UQSHLv16i8_shift = 5484 |
| 22052 | CEFBS_HasNEON, // UQSHLv1i16 = 5485 |
| 22053 | CEFBS_HasNEON, // UQSHLv1i32 = 5486 |
| 22054 | CEFBS_HasNEON, // UQSHLv1i64 = 5487 |
| 22055 | CEFBS_HasNEON, // UQSHLv1i8 = 5488 |
| 22056 | CEFBS_HasNEON, // UQSHLv2i32 = 5489 |
| 22057 | CEFBS_HasNEON, // UQSHLv2i32_shift = 5490 |
| 22058 | CEFBS_HasNEON, // UQSHLv2i64 = 5491 |
| 22059 | CEFBS_HasNEON, // UQSHLv2i64_shift = 5492 |
| 22060 | CEFBS_HasNEON, // UQSHLv4i16 = 5493 |
| 22061 | CEFBS_HasNEON, // UQSHLv4i16_shift = 5494 |
| 22062 | CEFBS_HasNEON, // UQSHLv4i32 = 5495 |
| 22063 | CEFBS_HasNEON, // UQSHLv4i32_shift = 5496 |
| 22064 | CEFBS_HasNEON, // UQSHLv8i16 = 5497 |
| 22065 | CEFBS_HasNEON, // UQSHLv8i16_shift = 5498 |
| 22066 | CEFBS_HasNEON, // UQSHLv8i8 = 5499 |
| 22067 | CEFBS_HasNEON, // UQSHLv8i8_shift = 5500 |
| 22068 | CEFBS_HasSVE2, // UQSHRNB_ZZI_B = 5501 |
| 22069 | CEFBS_HasSVE2, // UQSHRNB_ZZI_H = 5502 |
| 22070 | CEFBS_HasSVE2, // UQSHRNB_ZZI_S = 5503 |
| 22071 | CEFBS_HasSVE2, // UQSHRNT_ZZI_B = 5504 |
| 22072 | CEFBS_HasSVE2, // UQSHRNT_ZZI_H = 5505 |
| 22073 | CEFBS_HasSVE2, // UQSHRNT_ZZI_S = 5506 |
| 22074 | CEFBS_HasNEON, // UQSHRNb = 5507 |
| 22075 | CEFBS_HasNEON, // UQSHRNh = 5508 |
| 22076 | CEFBS_HasNEON, // UQSHRNs = 5509 |
| 22077 | CEFBS_HasNEON, // UQSHRNv16i8_shift = 5510 |
| 22078 | CEFBS_HasNEON, // UQSHRNv2i32_shift = 5511 |
| 22079 | CEFBS_HasNEON, // UQSHRNv4i16_shift = 5512 |
| 22080 | CEFBS_HasNEON, // UQSHRNv4i32_shift = 5513 |
| 22081 | CEFBS_HasNEON, // UQSHRNv8i16_shift = 5514 |
| 22082 | CEFBS_HasNEON, // UQSHRNv8i8_shift = 5515 |
| 22083 | CEFBS_HasSVE2, // UQSUBR_ZPmZ_B = 5516 |
| 22084 | CEFBS_HasSVE2, // UQSUBR_ZPmZ_D = 5517 |
| 22085 | CEFBS_HasSVE2, // UQSUBR_ZPmZ_H = 5518 |
| 22086 | CEFBS_HasSVE2, // UQSUBR_ZPmZ_S = 5519 |
| 22087 | CEFBS_HasSVE, // UQSUB_ZI_B = 5520 |
| 22088 | CEFBS_HasSVE, // UQSUB_ZI_D = 5521 |
| 22089 | CEFBS_HasSVE, // UQSUB_ZI_H = 5522 |
| 22090 | CEFBS_HasSVE, // UQSUB_ZI_S = 5523 |
| 22091 | CEFBS_HasSVE2, // UQSUB_ZPmZ_B = 5524 |
| 22092 | CEFBS_HasSVE2, // UQSUB_ZPmZ_D = 5525 |
| 22093 | CEFBS_HasSVE2, // UQSUB_ZPmZ_H = 5526 |
| 22094 | CEFBS_HasSVE2, // UQSUB_ZPmZ_S = 5527 |
| 22095 | CEFBS_HasSVE, // UQSUB_ZZZ_B = 5528 |
| 22096 | CEFBS_HasSVE, // UQSUB_ZZZ_D = 5529 |
| 22097 | CEFBS_HasSVE, // UQSUB_ZZZ_H = 5530 |
| 22098 | CEFBS_HasSVE, // UQSUB_ZZZ_S = 5531 |
| 22099 | CEFBS_HasNEON, // UQSUBv16i8 = 5532 |
| 22100 | CEFBS_HasNEON, // UQSUBv1i16 = 5533 |
| 22101 | CEFBS_HasNEON, // UQSUBv1i32 = 5534 |
| 22102 | CEFBS_HasNEON, // UQSUBv1i64 = 5535 |
| 22103 | CEFBS_HasNEON, // UQSUBv1i8 = 5536 |
| 22104 | CEFBS_HasNEON, // UQSUBv2i32 = 5537 |
| 22105 | CEFBS_HasNEON, // UQSUBv2i64 = 5538 |
| 22106 | CEFBS_HasNEON, // UQSUBv4i16 = 5539 |
| 22107 | CEFBS_HasNEON, // UQSUBv4i32 = 5540 |
| 22108 | CEFBS_HasNEON, // UQSUBv8i16 = 5541 |
| 22109 | CEFBS_HasNEON, // UQSUBv8i8 = 5542 |
| 22110 | CEFBS_HasSVE2, // UQXTNB_ZZ_B = 5543 |
| 22111 | CEFBS_HasSVE2, // UQXTNB_ZZ_H = 5544 |
| 22112 | CEFBS_HasSVE2, // UQXTNB_ZZ_S = 5545 |
| 22113 | CEFBS_HasSVE2, // UQXTNT_ZZ_B = 5546 |
| 22114 | CEFBS_HasSVE2, // UQXTNT_ZZ_H = 5547 |
| 22115 | CEFBS_HasSVE2, // UQXTNT_ZZ_S = 5548 |
| 22116 | CEFBS_HasNEON, // UQXTNv16i8 = 5549 |
| 22117 | CEFBS_HasNEON, // UQXTNv1i16 = 5550 |
| 22118 | CEFBS_HasNEON, // UQXTNv1i32 = 5551 |
| 22119 | CEFBS_HasNEON, // UQXTNv1i8 = 5552 |
| 22120 | CEFBS_HasNEON, // UQXTNv2i32 = 5553 |
| 22121 | CEFBS_HasNEON, // UQXTNv4i16 = 5554 |
| 22122 | CEFBS_HasNEON, // UQXTNv4i32 = 5555 |
| 22123 | CEFBS_HasNEON, // UQXTNv8i16 = 5556 |
| 22124 | CEFBS_HasNEON, // UQXTNv8i8 = 5557 |
| 22125 | CEFBS_HasSVE2, // URECPE_ZPmZ_S = 5558 |
| 22126 | CEFBS_HasNEON, // URECPEv2i32 = 5559 |
| 22127 | CEFBS_HasNEON, // URECPEv4i32 = 5560 |
| 22128 | CEFBS_HasSVE2, // URHADD_ZPmZ_B = 5561 |
| 22129 | CEFBS_HasSVE2, // URHADD_ZPmZ_D = 5562 |
| 22130 | CEFBS_HasSVE2, // URHADD_ZPmZ_H = 5563 |
| 22131 | CEFBS_HasSVE2, // URHADD_ZPmZ_S = 5564 |
| 22132 | CEFBS_HasNEON, // URHADDv16i8 = 5565 |
| 22133 | CEFBS_HasNEON, // URHADDv2i32 = 5566 |
| 22134 | CEFBS_HasNEON, // URHADDv4i16 = 5567 |
| 22135 | CEFBS_HasNEON, // URHADDv4i32 = 5568 |
| 22136 | CEFBS_HasNEON, // URHADDv8i16 = 5569 |
| 22137 | CEFBS_HasNEON, // URHADDv8i8 = 5570 |
| 22138 | CEFBS_HasSVE2, // URSHLR_ZPmZ_B = 5571 |
| 22139 | CEFBS_HasSVE2, // URSHLR_ZPmZ_D = 5572 |
| 22140 | CEFBS_HasSVE2, // URSHLR_ZPmZ_H = 5573 |
| 22141 | CEFBS_HasSVE2, // URSHLR_ZPmZ_S = 5574 |
| 22142 | CEFBS_HasSVE2, // URSHL_ZPmZ_B = 5575 |
| 22143 | CEFBS_HasSVE2, // URSHL_ZPmZ_D = 5576 |
| 22144 | CEFBS_HasSVE2, // URSHL_ZPmZ_H = 5577 |
| 22145 | CEFBS_HasSVE2, // URSHL_ZPmZ_S = 5578 |
| 22146 | CEFBS_HasNEON, // URSHLv16i8 = 5579 |
| 22147 | CEFBS_HasNEON, // URSHLv1i64 = 5580 |
| 22148 | CEFBS_HasNEON, // URSHLv2i32 = 5581 |
| 22149 | CEFBS_HasNEON, // URSHLv2i64 = 5582 |
| 22150 | CEFBS_HasNEON, // URSHLv4i16 = 5583 |
| 22151 | CEFBS_HasNEON, // URSHLv4i32 = 5584 |
| 22152 | CEFBS_HasNEON, // URSHLv8i16 = 5585 |
| 22153 | CEFBS_HasNEON, // URSHLv8i8 = 5586 |
| 22154 | CEFBS_HasSVE2, // URSHR_ZPmI_B = 5587 |
| 22155 | CEFBS_HasSVE2, // URSHR_ZPmI_D = 5588 |
| 22156 | CEFBS_HasSVE2, // URSHR_ZPmI_H = 5589 |
| 22157 | CEFBS_HasSVE2, // URSHR_ZPmI_S = 5590 |
| 22158 | CEFBS_HasNEON, // URSHRd = 5591 |
| 22159 | CEFBS_HasNEON, // URSHRv16i8_shift = 5592 |
| 22160 | CEFBS_HasNEON, // URSHRv2i32_shift = 5593 |
| 22161 | CEFBS_HasNEON, // URSHRv2i64_shift = 5594 |
| 22162 | CEFBS_HasNEON, // URSHRv4i16_shift = 5595 |
| 22163 | CEFBS_HasNEON, // URSHRv4i32_shift = 5596 |
| 22164 | CEFBS_HasNEON, // URSHRv8i16_shift = 5597 |
| 22165 | CEFBS_HasNEON, // URSHRv8i8_shift = 5598 |
| 22166 | CEFBS_HasSVE2, // URSQRTE_ZPmZ_S = 5599 |
| 22167 | CEFBS_HasNEON, // URSQRTEv2i32 = 5600 |
| 22168 | CEFBS_HasNEON, // URSQRTEv4i32 = 5601 |
| 22169 | CEFBS_HasSVE2, // URSRA_ZZI_B = 5602 |
| 22170 | CEFBS_HasSVE2, // URSRA_ZZI_D = 5603 |
| 22171 | CEFBS_HasSVE2, // URSRA_ZZI_H = 5604 |
| 22172 | CEFBS_HasSVE2, // URSRA_ZZI_S = 5605 |
| 22173 | CEFBS_HasNEON, // URSRAd = 5606 |
| 22174 | CEFBS_HasNEON, // URSRAv16i8_shift = 5607 |
| 22175 | CEFBS_HasNEON, // URSRAv2i32_shift = 5608 |
| 22176 | CEFBS_HasNEON, // URSRAv2i64_shift = 5609 |
| 22177 | CEFBS_HasNEON, // URSRAv4i16_shift = 5610 |
| 22178 | CEFBS_HasNEON, // URSRAv4i32_shift = 5611 |
| 22179 | CEFBS_HasNEON, // URSRAv8i16_shift = 5612 |
| 22180 | CEFBS_HasNEON, // URSRAv8i8_shift = 5613 |
| 22181 | CEFBS_HasSVE_HasMatMulInt8, // USDOT_ZZZ = 5614 |
| 22182 | CEFBS_HasSVE_HasMatMulInt8, // USDOT_ZZZI = 5615 |
| 22183 | CEFBS_HasMatMulInt8, // USDOTlanev16i8 = 5616 |
| 22184 | CEFBS_HasMatMulInt8, // USDOTlanev8i8 = 5617 |
| 22185 | CEFBS_HasMatMulInt8, // USDOTv16i8 = 5618 |
| 22186 | CEFBS_HasMatMulInt8, // USDOTv8i8 = 5619 |
| 22187 | CEFBS_HasSVE2, // USHLLB_ZZI_D = 5620 |
| 22188 | CEFBS_HasSVE2, // USHLLB_ZZI_H = 5621 |
| 22189 | CEFBS_HasSVE2, // USHLLB_ZZI_S = 5622 |
| 22190 | CEFBS_HasSVE2, // USHLLT_ZZI_D = 5623 |
| 22191 | CEFBS_HasSVE2, // USHLLT_ZZI_H = 5624 |
| 22192 | CEFBS_HasSVE2, // USHLLT_ZZI_S = 5625 |
| 22193 | CEFBS_HasNEON, // USHLLv16i8_shift = 5626 |
| 22194 | CEFBS_HasNEON, // USHLLv2i32_shift = 5627 |
| 22195 | CEFBS_HasNEON, // USHLLv4i16_shift = 5628 |
| 22196 | CEFBS_HasNEON, // USHLLv4i32_shift = 5629 |
| 22197 | CEFBS_HasNEON, // USHLLv8i16_shift = 5630 |
| 22198 | CEFBS_HasNEON, // USHLLv8i8_shift = 5631 |
| 22199 | CEFBS_HasNEON, // USHLv16i8 = 5632 |
| 22200 | CEFBS_HasNEON, // USHLv1i64 = 5633 |
| 22201 | CEFBS_HasNEON, // USHLv2i32 = 5634 |
| 22202 | CEFBS_HasNEON, // USHLv2i64 = 5635 |
| 22203 | CEFBS_HasNEON, // USHLv4i16 = 5636 |
| 22204 | CEFBS_HasNEON, // USHLv4i32 = 5637 |
| 22205 | CEFBS_HasNEON, // USHLv8i16 = 5638 |
| 22206 | CEFBS_HasNEON, // USHLv8i8 = 5639 |
| 22207 | CEFBS_HasNEON, // USHRd = 5640 |
| 22208 | CEFBS_HasNEON, // USHRv16i8_shift = 5641 |
| 22209 | CEFBS_HasNEON, // USHRv2i32_shift = 5642 |
| 22210 | CEFBS_HasNEON, // USHRv2i64_shift = 5643 |
| 22211 | CEFBS_HasNEON, // USHRv4i16_shift = 5644 |
| 22212 | CEFBS_HasNEON, // USHRv4i32_shift = 5645 |
| 22213 | CEFBS_HasNEON, // USHRv8i16_shift = 5646 |
| 22214 | CEFBS_HasNEON, // USHRv8i8_shift = 5647 |
| 22215 | CEFBS_HasMatMulInt8, // USMMLA = 5648 |
| 22216 | CEFBS_HasSVE_HasMatMulInt8, // USMMLA_ZZZ = 5649 |
| 22217 | CEFBS_HasSVE2, // USQADD_ZPmZ_B = 5650 |
| 22218 | CEFBS_HasSVE2, // USQADD_ZPmZ_D = 5651 |
| 22219 | CEFBS_HasSVE2, // USQADD_ZPmZ_H = 5652 |
| 22220 | CEFBS_HasSVE2, // USQADD_ZPmZ_S = 5653 |
| 22221 | CEFBS_HasNEON, // USQADDv16i8 = 5654 |
| 22222 | CEFBS_HasNEON, // USQADDv1i16 = 5655 |
| 22223 | CEFBS_HasNEON, // USQADDv1i32 = 5656 |
| 22224 | CEFBS_HasNEON, // USQADDv1i64 = 5657 |
| 22225 | CEFBS_HasNEON, // USQADDv1i8 = 5658 |
| 22226 | CEFBS_HasNEON, // USQADDv2i32 = 5659 |
| 22227 | CEFBS_HasNEON, // USQADDv2i64 = 5660 |
| 22228 | CEFBS_HasNEON, // USQADDv4i16 = 5661 |
| 22229 | CEFBS_HasNEON, // USQADDv4i32 = 5662 |
| 22230 | CEFBS_HasNEON, // USQADDv8i16 = 5663 |
| 22231 | CEFBS_HasNEON, // USQADDv8i8 = 5664 |
| 22232 | CEFBS_HasSVE2, // USRA_ZZI_B = 5665 |
| 22233 | CEFBS_HasSVE2, // USRA_ZZI_D = 5666 |
| 22234 | CEFBS_HasSVE2, // USRA_ZZI_H = 5667 |
| 22235 | CEFBS_HasSVE2, // USRA_ZZI_S = 5668 |
| 22236 | CEFBS_HasNEON, // USRAd = 5669 |
| 22237 | CEFBS_HasNEON, // USRAv16i8_shift = 5670 |
| 22238 | CEFBS_HasNEON, // USRAv2i32_shift = 5671 |
| 22239 | CEFBS_HasNEON, // USRAv2i64_shift = 5672 |
| 22240 | CEFBS_HasNEON, // USRAv4i16_shift = 5673 |
| 22241 | CEFBS_HasNEON, // USRAv4i32_shift = 5674 |
| 22242 | CEFBS_HasNEON, // USRAv8i16_shift = 5675 |
| 22243 | CEFBS_HasNEON, // USRAv8i8_shift = 5676 |
| 22244 | CEFBS_HasSVE2, // USUBLB_ZZZ_D = 5677 |
| 22245 | CEFBS_HasSVE2, // USUBLB_ZZZ_H = 5678 |
| 22246 | CEFBS_HasSVE2, // USUBLB_ZZZ_S = 5679 |
| 22247 | CEFBS_HasSVE2, // USUBLT_ZZZ_D = 5680 |
| 22248 | CEFBS_HasSVE2, // USUBLT_ZZZ_H = 5681 |
| 22249 | CEFBS_HasSVE2, // USUBLT_ZZZ_S = 5682 |
| 22250 | CEFBS_HasNEON, // USUBLv16i8_v8i16 = 5683 |
| 22251 | CEFBS_HasNEON, // USUBLv2i32_v2i64 = 5684 |
| 22252 | CEFBS_HasNEON, // USUBLv4i16_v4i32 = 5685 |
| 22253 | CEFBS_HasNEON, // USUBLv4i32_v2i64 = 5686 |
| 22254 | CEFBS_HasNEON, // USUBLv8i16_v4i32 = 5687 |
| 22255 | CEFBS_HasNEON, // USUBLv8i8_v8i16 = 5688 |
| 22256 | CEFBS_HasSVE2, // USUBWB_ZZZ_D = 5689 |
| 22257 | CEFBS_HasSVE2, // USUBWB_ZZZ_H = 5690 |
| 22258 | CEFBS_HasSVE2, // USUBWB_ZZZ_S = 5691 |
| 22259 | CEFBS_HasSVE2, // USUBWT_ZZZ_D = 5692 |
| 22260 | CEFBS_HasSVE2, // USUBWT_ZZZ_H = 5693 |
| 22261 | CEFBS_HasSVE2, // USUBWT_ZZZ_S = 5694 |
| 22262 | CEFBS_HasNEON, // USUBWv16i8_v8i16 = 5695 |
| 22263 | CEFBS_HasNEON, // USUBWv2i32_v2i64 = 5696 |
| 22264 | CEFBS_HasNEON, // USUBWv4i16_v4i32 = 5697 |
| 22265 | CEFBS_HasNEON, // USUBWv4i32_v2i64 = 5698 |
| 22266 | CEFBS_HasNEON, // USUBWv8i16_v4i32 = 5699 |
| 22267 | CEFBS_HasNEON, // USUBWv8i8_v8i16 = 5700 |
| 22268 | CEFBS_HasSVE, // UUNPKHI_ZZ_D = 5701 |
| 22269 | CEFBS_HasSVE, // UUNPKHI_ZZ_H = 5702 |
| 22270 | CEFBS_HasSVE, // UUNPKHI_ZZ_S = 5703 |
| 22271 | CEFBS_HasSVE, // UUNPKLO_ZZ_D = 5704 |
| 22272 | CEFBS_HasSVE, // UUNPKLO_ZZ_H = 5705 |
| 22273 | CEFBS_HasSVE, // UUNPKLO_ZZ_S = 5706 |
| 22274 | CEFBS_HasSVE, // UXTB_ZPmZ_D = 5707 |
| 22275 | CEFBS_HasSVE, // UXTB_ZPmZ_H = 5708 |
| 22276 | CEFBS_HasSVE, // UXTB_ZPmZ_S = 5709 |
| 22277 | CEFBS_HasSVE, // UXTH_ZPmZ_D = 5710 |
| 22278 | CEFBS_HasSVE, // UXTH_ZPmZ_S = 5711 |
| 22279 | CEFBS_HasSVE, // UXTW_ZPmZ_D = 5712 |
| 22280 | CEFBS_HasSVE, // UZP1_PPP_B = 5713 |
| 22281 | CEFBS_HasSVE, // UZP1_PPP_D = 5714 |
| 22282 | CEFBS_HasSVE, // UZP1_PPP_H = 5715 |
| 22283 | CEFBS_HasSVE, // UZP1_PPP_S = 5716 |
| 22284 | CEFBS_HasSVE, // UZP1_ZZZ_B = 5717 |
| 22285 | CEFBS_HasSVE, // UZP1_ZZZ_D = 5718 |
| 22286 | CEFBS_HasSVE, // UZP1_ZZZ_H = 5719 |
| 22287 | CEFBS_HasSVE_HasMatMulFP64, // UZP1_ZZZ_Q = 5720 |
| 22288 | CEFBS_HasSVE, // UZP1_ZZZ_S = 5721 |
| 22289 | CEFBS_HasNEON, // UZP1v16i8 = 5722 |
| 22290 | CEFBS_HasNEON, // UZP1v2i32 = 5723 |
| 22291 | CEFBS_HasNEON, // UZP1v2i64 = 5724 |
| 22292 | CEFBS_HasNEON, // UZP1v4i16 = 5725 |
| 22293 | CEFBS_HasNEON, // UZP1v4i32 = 5726 |
| 22294 | CEFBS_HasNEON, // UZP1v8i16 = 5727 |
| 22295 | CEFBS_HasNEON, // UZP1v8i8 = 5728 |
| 22296 | CEFBS_HasSVE, // UZP2_PPP_B = 5729 |
| 22297 | CEFBS_HasSVE, // UZP2_PPP_D = 5730 |
| 22298 | CEFBS_HasSVE, // UZP2_PPP_H = 5731 |
| 22299 | CEFBS_HasSVE, // UZP2_PPP_S = 5732 |
| 22300 | CEFBS_HasSVE, // UZP2_ZZZ_B = 5733 |
| 22301 | CEFBS_HasSVE, // UZP2_ZZZ_D = 5734 |
| 22302 | CEFBS_HasSVE, // UZP2_ZZZ_H = 5735 |
| 22303 | CEFBS_HasSVE_HasMatMulFP64, // UZP2_ZZZ_Q = 5736 |
| 22304 | CEFBS_HasSVE, // UZP2_ZZZ_S = 5737 |
| 22305 | CEFBS_HasNEON, // UZP2v16i8 = 5738 |
| 22306 | CEFBS_HasNEON, // UZP2v2i32 = 5739 |
| 22307 | CEFBS_HasNEON, // UZP2v2i64 = 5740 |
| 22308 | CEFBS_HasNEON, // UZP2v4i16 = 5741 |
| 22309 | CEFBS_HasNEON, // UZP2v4i32 = 5742 |
| 22310 | CEFBS_HasNEON, // UZP2v8i16 = 5743 |
| 22311 | CEFBS_HasNEON, // UZP2v8i8 = 5744 |
| 22312 | CEFBS_HasWFxT, // WFET = 5745 |
| 22313 | CEFBS_HasWFxT, // WFIT = 5746 |
| 22314 | CEFBS_HasSVE2, // WHILEGE_PWW_B = 5747 |
| 22315 | CEFBS_HasSVE2, // WHILEGE_PWW_D = 5748 |
| 22316 | CEFBS_HasSVE2, // WHILEGE_PWW_H = 5749 |
| 22317 | CEFBS_HasSVE2, // WHILEGE_PWW_S = 5750 |
| 22318 | CEFBS_HasSVE2, // WHILEGE_PXX_B = 5751 |
| 22319 | CEFBS_HasSVE2, // WHILEGE_PXX_D = 5752 |
| 22320 | CEFBS_HasSVE2, // WHILEGE_PXX_H = 5753 |
| 22321 | CEFBS_HasSVE2, // WHILEGE_PXX_S = 5754 |
| 22322 | CEFBS_HasSVE2, // WHILEGT_PWW_B = 5755 |
| 22323 | CEFBS_HasSVE2, // WHILEGT_PWW_D = 5756 |
| 22324 | CEFBS_HasSVE2, // WHILEGT_PWW_H = 5757 |
| 22325 | CEFBS_HasSVE2, // WHILEGT_PWW_S = 5758 |
| 22326 | CEFBS_HasSVE2, // WHILEGT_PXX_B = 5759 |
| 22327 | CEFBS_HasSVE2, // WHILEGT_PXX_D = 5760 |
| 22328 | CEFBS_HasSVE2, // WHILEGT_PXX_H = 5761 |
| 22329 | CEFBS_HasSVE2, // WHILEGT_PXX_S = 5762 |
| 22330 | CEFBS_HasSVE2, // WHILEHI_PWW_B = 5763 |
| 22331 | CEFBS_HasSVE2, // WHILEHI_PWW_D = 5764 |
| 22332 | CEFBS_HasSVE2, // WHILEHI_PWW_H = 5765 |
| 22333 | CEFBS_HasSVE2, // WHILEHI_PWW_S = 5766 |
| 22334 | CEFBS_HasSVE2, // WHILEHI_PXX_B = 5767 |
| 22335 | CEFBS_HasSVE2, // WHILEHI_PXX_D = 5768 |
| 22336 | CEFBS_HasSVE2, // WHILEHI_PXX_H = 5769 |
| 22337 | CEFBS_HasSVE2, // WHILEHI_PXX_S = 5770 |
| 22338 | CEFBS_HasSVE2, // WHILEHS_PWW_B = 5771 |
| 22339 | CEFBS_HasSVE2, // WHILEHS_PWW_D = 5772 |
| 22340 | CEFBS_HasSVE2, // WHILEHS_PWW_H = 5773 |
| 22341 | CEFBS_HasSVE2, // WHILEHS_PWW_S = 5774 |
| 22342 | CEFBS_HasSVE2, // WHILEHS_PXX_B = 5775 |
| 22343 | CEFBS_HasSVE2, // WHILEHS_PXX_D = 5776 |
| 22344 | CEFBS_HasSVE2, // WHILEHS_PXX_H = 5777 |
| 22345 | CEFBS_HasSVE2, // WHILEHS_PXX_S = 5778 |
| 22346 | CEFBS_HasSVE, // WHILELE_PWW_B = 5779 |
| 22347 | CEFBS_HasSVE, // WHILELE_PWW_D = 5780 |
| 22348 | CEFBS_HasSVE, // WHILELE_PWW_H = 5781 |
| 22349 | CEFBS_HasSVE, // WHILELE_PWW_S = 5782 |
| 22350 | CEFBS_HasSVE, // WHILELE_PXX_B = 5783 |
| 22351 | CEFBS_HasSVE, // WHILELE_PXX_D = 5784 |
| 22352 | CEFBS_HasSVE, // WHILELE_PXX_H = 5785 |
| 22353 | CEFBS_HasSVE, // WHILELE_PXX_S = 5786 |
| 22354 | CEFBS_HasSVE, // WHILELO_PWW_B = 5787 |
| 22355 | CEFBS_HasSVE, // WHILELO_PWW_D = 5788 |
| 22356 | CEFBS_HasSVE, // WHILELO_PWW_H = 5789 |
| 22357 | CEFBS_HasSVE, // WHILELO_PWW_S = 5790 |
| 22358 | CEFBS_HasSVE, // WHILELO_PXX_B = 5791 |
| 22359 | CEFBS_HasSVE, // WHILELO_PXX_D = 5792 |
| 22360 | CEFBS_HasSVE, // WHILELO_PXX_H = 5793 |
| 22361 | CEFBS_HasSVE, // WHILELO_PXX_S = 5794 |
| 22362 | CEFBS_HasSVE, // WHILELS_PWW_B = 5795 |
| 22363 | CEFBS_HasSVE, // WHILELS_PWW_D = 5796 |
| 22364 | CEFBS_HasSVE, // WHILELS_PWW_H = 5797 |
| 22365 | CEFBS_HasSVE, // WHILELS_PWW_S = 5798 |
| 22366 | CEFBS_HasSVE, // WHILELS_PXX_B = 5799 |
| 22367 | CEFBS_HasSVE, // WHILELS_PXX_D = 5800 |
| 22368 | CEFBS_HasSVE, // WHILELS_PXX_H = 5801 |
| 22369 | CEFBS_HasSVE, // WHILELS_PXX_S = 5802 |
| 22370 | CEFBS_HasSVE, // WHILELT_PWW_B = 5803 |
| 22371 | CEFBS_HasSVE, // WHILELT_PWW_D = 5804 |
| 22372 | CEFBS_HasSVE, // WHILELT_PWW_H = 5805 |
| 22373 | CEFBS_HasSVE, // WHILELT_PWW_S = 5806 |
| 22374 | CEFBS_HasSVE, // WHILELT_PXX_B = 5807 |
| 22375 | CEFBS_HasSVE, // WHILELT_PXX_D = 5808 |
| 22376 | CEFBS_HasSVE, // WHILELT_PXX_H = 5809 |
| 22377 | CEFBS_HasSVE, // WHILELT_PXX_S = 5810 |
| 22378 | CEFBS_HasSVE2, // WHILERW_PXX_B = 5811 |
| 22379 | CEFBS_HasSVE2, // WHILERW_PXX_D = 5812 |
| 22380 | CEFBS_HasSVE2, // WHILERW_PXX_H = 5813 |
| 22381 | CEFBS_HasSVE2, // WHILERW_PXX_S = 5814 |
| 22382 | CEFBS_HasSVE2, // WHILEWR_PXX_B = 5815 |
| 22383 | CEFBS_HasSVE2, // WHILEWR_PXX_D = 5816 |
| 22384 | CEFBS_HasSVE2, // WHILEWR_PXX_H = 5817 |
| 22385 | CEFBS_HasSVE2, // WHILEWR_PXX_S = 5818 |
| 22386 | CEFBS_HasSVE, // WRFFR = 5819 |
| 22387 | CEFBS_HasAltNZCV, // XAFLAG = 5820 |
| 22388 | CEFBS_HasSHA3, // XAR = 5821 |
| 22389 | CEFBS_HasSVE2, // XAR_ZZZI_B = 5822 |
| 22390 | CEFBS_HasSVE2, // XAR_ZZZI_D = 5823 |
| 22391 | CEFBS_HasSVE2, // XAR_ZZZI_H = 5824 |
| 22392 | CEFBS_HasSVE2, // XAR_ZZZI_S = 5825 |
| 22393 | CEFBS_HasPAuth, // XPACD = 5826 |
| 22394 | CEFBS_HasPAuth, // XPACI = 5827 |
| 22395 | CEFBS_None, // XPACLRI = 5828 |
| 22396 | CEFBS_HasNEON, // XTNv16i8 = 5829 |
| 22397 | CEFBS_HasNEON, // XTNv2i32 = 5830 |
| 22398 | CEFBS_HasNEON, // XTNv4i16 = 5831 |
| 22399 | CEFBS_HasNEON, // XTNv4i32 = 5832 |
| 22400 | CEFBS_HasNEON, // XTNv8i16 = 5833 |
| 22401 | CEFBS_HasNEON, // XTNv8i8 = 5834 |
| 22402 | CEFBS_HasSVE, // ZIP1_PPP_B = 5835 |
| 22403 | CEFBS_HasSVE, // ZIP1_PPP_D = 5836 |
| 22404 | CEFBS_HasSVE, // ZIP1_PPP_H = 5837 |
| 22405 | CEFBS_HasSVE, // ZIP1_PPP_S = 5838 |
| 22406 | CEFBS_HasSVE, // ZIP1_ZZZ_B = 5839 |
| 22407 | CEFBS_HasSVE, // ZIP1_ZZZ_D = 5840 |
| 22408 | CEFBS_HasSVE, // ZIP1_ZZZ_H = 5841 |
| 22409 | CEFBS_HasSVE_HasMatMulFP64, // ZIP1_ZZZ_Q = 5842 |
| 22410 | CEFBS_HasSVE, // ZIP1_ZZZ_S = 5843 |
| 22411 | CEFBS_HasNEON, // ZIP1v16i8 = 5844 |
| 22412 | CEFBS_HasNEON, // ZIP1v2i32 = 5845 |
| 22413 | CEFBS_HasNEON, // ZIP1v2i64 = 5846 |
| 22414 | CEFBS_HasNEON, // ZIP1v4i16 = 5847 |
| 22415 | CEFBS_HasNEON, // ZIP1v4i32 = 5848 |
| 22416 | CEFBS_HasNEON, // ZIP1v8i16 = 5849 |
| 22417 | CEFBS_HasNEON, // ZIP1v8i8 = 5850 |
| 22418 | CEFBS_HasSVE, // ZIP2_PPP_B = 5851 |
| 22419 | CEFBS_HasSVE, // ZIP2_PPP_D = 5852 |
| 22420 | CEFBS_HasSVE, // ZIP2_PPP_H = 5853 |
| 22421 | CEFBS_HasSVE, // ZIP2_PPP_S = 5854 |
| 22422 | CEFBS_HasSVE, // ZIP2_ZZZ_B = 5855 |
| 22423 | CEFBS_HasSVE, // ZIP2_ZZZ_D = 5856 |
| 22424 | CEFBS_HasSVE, // ZIP2_ZZZ_H = 5857 |
| 22425 | CEFBS_HasSVE_HasMatMulFP64, // ZIP2_ZZZ_Q = 5858 |
| 22426 | CEFBS_HasSVE, // ZIP2_ZZZ_S = 5859 |
| 22427 | CEFBS_HasNEON, // ZIP2v16i8 = 5860 |
| 22428 | CEFBS_HasNEON, // ZIP2v2i32 = 5861 |
| 22429 | CEFBS_HasNEON, // ZIP2v2i64 = 5862 |
| 22430 | CEFBS_HasNEON, // ZIP2v4i16 = 5863 |
| 22431 | CEFBS_HasNEON, // ZIP2v4i32 = 5864 |
| 22432 | CEFBS_HasNEON, // ZIP2v8i16 = 5865 |
| 22433 | CEFBS_HasNEON, // ZIP2v8i8 = 5866 |
| 22434 | }; |
| 22435 | |
| 22436 | assert(Inst.getOpcode() < 5867); |
| 22437 | const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]]; |
| 22438 | FeatureBitset MissingFeatures = |
| 22439 | (AvailableFeatures & RequiredFeatures) ^ |
| 22440 | RequiredFeatures; |
| 22441 | if (MissingFeatures.any()) { |
| 22442 | std::ostringstream Msg; |
| 22443 | Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str() |
| 22444 | << " instruction but the " ; |
| 22445 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 22446 | if (MissingFeatures.test(i)) |
| 22447 | Msg << SubtargetFeatureNames[i] << " " ; |
| 22448 | Msg << "predicate(s) are not met" ; |
| 22449 | report_fatal_error(Msg.str()); |
| 22450 | } |
| 22451 | #else |
| 22452 | // Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF). |
| 22453 | (void)MCII; |
| 22454 | #endif // NDEBUG |
| 22455 | } |
| 22456 | #endif |
| 22457 | |